PD - 99438
IRFPC60LC-P
HEXFET® Power MOSFET
l
l
l
l
l
l
l
Ultra Low Gate Charge
Reduced Gate Drive Requirement
Enhanced 30V Vgs Rating
Reduced Ciss, Coss, Crss
Isolated Central Mounting Hole
Dynamic dv/dt Rated
Repetitive Avalanche Rated
D
VDSS = 600V
RDS(on) = 0.40Ω
G
S
ID = 16A
Description
This new series of Surface Mountable Low Charge HEXFET Power MOSFETs
achieve significantly lower gate charge over conventional MOSFETs. Utilizing
advanced Hexfet technology the device improvements allow for reduced gate
drive requirements, faster switching speeds and increased total system savings.
These device improvements combined with the proven ruggedness and reliability
of HEXFETs offer the designer a new standard in power transistors for switching
applications.
Surface Mountable
TO-247
Absolute Maximum Ratings
ID @ TC = 25°C
ID @ TC = 100°C
IDM
PD @TC = 25°C
VGS
EAS
IAR
EAR
dv/dt
TJ
TSTG
Parameter
Max.
Continuous Drain Current, VGS @ 10V
Continuous Drain Current, VGS @ 10V
Pulsed Drain Current
Power Dissipation
Linear Derating Factor
Gate-to-Source Voltage
Single Pulse Avalanche Energy
Avalanche Current
Repetitive Avalanche Energy
Peak Diode Recovery dv/dt
Operating Junction and
Storage Temperature Range
Max Reflow Temperature
16
10
64
280
2.2
±30
1000
16
28
3.0
-55 to + 150
Units
A
W
W/°C
V
mJ
A
mJ
V/ns
°C
225
Thermal Resistance
Parameter
RθJC
RθCS
RθJA
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Junction-to-Case
Case-to-Sink, Flat, Greased Surface
Junction-to-Ambient
Min.
Typ.
Max.
Units
––––
––––
––––
––––
0.24
––––
0.45
––––
40
°C/W
1
04/25/02
IRFPC60LC-P
Electrical Characteristics @ TJ = 25°C (unless otherwise specified)
RDS(ON)
VGS(th)
gfs
Parameter
Drain-to-Source Breakdown Voltage
Breakdown Voltage Temp. Coefficient
Static Drain-to-Source On-Resistance
Gate Threshold Voltage
Forward Transconductance
Qg
Qgs
Qgd
td(on)
tr
td(off)
tf
Gate-to-Source Forward Leakage
Gate-to-Source Reverse Leakage
Total Gate Charge
Gate-to-Source Charge
Gate-to-Drain ("Miller") Charge
Turn-On Delay Time
Rise Time
Turn-Off Delay Time
Fall Time
Min.
600
–––
–––
2.0
11
–––
–––
–––
–––
–––
–––
–––
–––
–––
–––
–––
IDSS
Drain-to-Source Leakage Current
LD
Internal Drain Inductance
–––
LS
Internal Source Inductance
–––
Ciss
Coss
Crss
Input Capacitance
Output Capacitance
Reverse Transfer Capacitance
–––
–––
–––
V(BR)DSS
∆V(BR)DSS/∆TJ
IGSS
Typ. Max. Units
Conditions
––– –––
V
VGS = 0V, ID = 250µA
0.63 ––– V/°C Reference to 25°C, ID = 1mA
––– 0.40
Ω
VGS = 10V, ID = 9.6A
––– 4.0
V
VDS = VGS, ID = 250µA
––– –––
S
VDS = 50V, ID = 9.6A
––– 25
VDS = 600V, VGS = 0V
µA
––– 250
VDS = 480V, VGS = 0V, TJ = 125°C
––– 100
VGS = 20V
nA
––– -100
VGS = -20V
––– 120
ID = 16A
––– 29
nC
VDS = 360V
––– 48
VGS = 10V, See Fig. 6 and 13
17 –––
VDD = 300V
57 –––
ID = 16A
ns
43 –––
RG = 4.3Ω
38 –––
RD = 18Ω, See Fig. 10
D
Between lead,
5.0 –––
6mm (0.25in.)
nH
G
from package
13
–––
and center of die contact
S
3500 –––
VGS = 0V
400 –––
pF
VDS = 25V
39 –––
ƒ = 1.0MHz, See Fig. 5
Source-Drain Ratings and Characteristics
IS
ISM
VSD
trr
Qrr
ton
Parameter
Continuous Source Current
(Body Diode)
Pulsed Source Current
(Body Diode)
Diode Forward Voltage
Reverse Recovery Time
Reverse RecoveryCharge
Forward Turn-On Time
Min. Typ. Max. Units
–––
–––
16
–––
–––
64
–––
–––
–––
–––
650
6.0
1.8
980
9.0
A
V
ns
µC
Conditions
D
MOSFET symbol
showing the
G
integral reverse
p-n junction diode.
S
TJ = 25°C, IS = 16A, VGS = 0V
TJ = 25°C, IF = 16A
di/dt = 100A/µs
Intrinsic turn-on time is negligible (turn-on is dominated by LS+LD)
Notes:
Repetitive rating; pulse width limited by
max. junction temperature. ( See fig. 11 )
VDD = 25V, starting TJ = 25°C, L = 7.2mH
ISD ≤ 16A, di/dt ≤ 140A/µs, VDD ≤ V(BR)DSS,
T J ≤ 150°C
Pulse width ≤ 300µs; duty cycle ≤ 2%.
R G = 25Ω, IAS = 16A. (See Figure 12)
2
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IRFPC60LC-P
1 00
1 00
VGS
15V
10V
8.0V
7.0V
6.0V
5.5V
5.0V
10
BOTTOM 4.5V
VGS
15V
10V
8.0V
7.0V
6.0V
5.5V
5.0V
10
BOTTOM 4.5V
TOP
I , D rain-to-S ource C urrent (A )
D
I , D rain-to-S ource C urrent (A )
D
TOP
1
0 .1
4 .5V
2 0µ s P U L S E W ID T H
T C = 25 °C
0 .0 1
0 .0 1
0 .1
V
DS
1
10
100
4 .5V
1
0 .1
, D rain-to-So urce Voltage (V)
R D S (o n) , D rain-to-S ource O n R esis tanc e
(No rm alized)
I D , D rain-to-So urce Cu rre nt (A )
T J = 1 50°C
10
T J = 25 °C
0 .1
V D S = 1 00 V
2 0µ s P U L S E W ID TH
4
5
6
7
8
9
V G S , G ate-to-S ourc e V o ltag e (V )
Fig 3. Typical Transfer Characteristics
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DS
1
10
100
, D rain-to-So urce Voltage (V)
Fig 2. Typical Output Characteristics,
TC = 150oC
100
0 .0 1
0 .1
V
Fig 1. Typical Output Characteristics,
TC = 25oC
1
20 µ s P U LS E W ID T H
TC = 150 °C
0 .0 1
0 .0 1
3 .0
ID = 16A
2 .5
2 .0
1 .5
1 .0
0 .5
V G S = 10V
0 .0
10
-6 0
-4 0
-2 0
0
20
40
60
80
100 120 140 160
T J , Junction Te m perature (°C )
Fig 4. Normalized On-Resistance
Vs. Temperature
3
IRFPC60LC-P
20
7 00 0
C , C apacitan ce (pF )
6 00 0
0V,
f = 1MH z
C gs + C g d , C d s S H O R T E D
C gd
C ds + C gd
, G ate-to-S ource V o ltage (V )
V GS =
C is s =
C rs s =
C oss =
5 00 0
4 00 0
C iss
3 00 0
V D S = 3 60 V
V D S = 2 40 V
V D S = 1 20 V
16
12
8
4
V
GS
2 00 0
I D = 1 6A
1 00 0
C o ss
C rss
0
1
F O R TE S T C IR C U IT
S E E FIG U R E 13
0
10
0
1 00
Fig 5. Typical Capacitance Vs.
Drain-to-Source Voltage
60
90
12 0
Fig 6. Typical Gate Charge Vs.
Gate-to-Source Voltage
100
1000
O P E R A TIO N IN TH IS A R E A L IM ITE D
B Y R D S (o n )
10
I D , D rain C urrent (A )
I S D , R everse D rain C urren t (A )
30
Q G , T otal G ate Charge (nC )
V DS , Drain-to-S ource V oltage (V )
T J = 1 50 °C
T J = 25 °C
10µ s
100µ s
10
1m s
VG S = 0 V
1
0
0 .4
0 .8
1 .2
1 .6
V S D , Source -to-D rain V oltag e (V)
Fig 7. Typical Source-Drain Diode
Forward Voltage
4
100
T C = 2 5°C
T J = 1 50 °C
S ingle P ulse
1
2
1
10
10m s
100
1000
100 00
VD S , D rain-to-S ource V oltage (V )
Fig 8. Maximum Safe Operating Area
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IRFPC60LC-P
RD
VDS
VGS
16
D.U.T.
RG
+
ID , D rain C urrent (Am ps)
- VDD
12
10 V
Pulse Width ≤ 1 µs
Duty Factor ≤ 0.1 %
8
Fig 10a. Switching Time Test Circuit
VDS
90%
4
10%
VGS
0
25
50
75
100
125
150
TC , C ase T em perature (°C )
td(on)
Fig 9. Maximum Drain Current Vs.
Case Temperature
tr
t d(off)
tf
Fig 10b. Switching Time Waveforms
Therm al R es po nse (Z thJC )
1
D = 0 .5 0
0 .1
0 .2 0
0 .1 0
0 .0 5
PD M
0 .0 2
0 .0 1
0 .0 1
t
S IN G L E P U L S E
(T H E R M A L R E S P O N S E )
1
t2
N o te s :
1 . D u ty fa c to r D = t
1
/ t2
2 . P e a k TJ = P D M x Z th J C + T C
0 .0 0 1
0 .0 0 0 0 1
0 .0 0 0 1
0 .0 0 1
0 .0 1
0 .1
1
10
t 1 , R ectangular Pulse D uration (sec)
Fig 11. Maximum Effective Transient Thermal Impedance, Junction-to-Case
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5
IRFPC60LC-P
L
VDS
RG
+
-
VDD
IAS
10 V
tp
0.01Ω
Fig 12a. Unclamped Inductive Test Circuit
V(BR)DSS
tp
VDD
VDS
E A S , S ingle P ulse A valan che E nergy (m J )
D.U.T.
2400
ID
7 .2 A
10A
B OT TO M 16A
TOP
2000
1600
1200
800
400
V D D = 5 0V
0
25
50
75
100
125
150
Starting T J , Juntion Te m perature (°C )
IAS
Fig 12b. Unclamped Inductive Waveforms
Fig 12c. Maximum Avalanche Energy
Vs. Drain Current
Current Regulator
Same Type as D.U.T.
50KΩ
QG
.2µF
12V
.3µF
10 V
QGS
D.U.T.
QGD
+
V
- DS
VGS
VG
3mA
IG
Charge
Fig 13a. Basic Gate Charge Waveform
6
ID
Current Sampling Resistors
Fig 13b. Gate Charge Test Circuit
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IRFPC60LC-P
Peak Diode Recovery dv/dt Test Circuit
+
D.U.T
Circuit Layout Considerations
• Low Stray Inductance
• Ground Plane
• Low Leakage Inductance
Current Transformer
+
-
-
+
•
•
•
•
RG
Driver Gate Drive
P.W.
+
dv/dt controlled by RG
Driver same type as D.U.T.
ISD controlled by Duty Factor "D"
D.U.T. - Device Under Test
Period
D=
-
VDD
P.W.
Period
VGS=10V
*
D.U.T. ISD Waveform
Reverse
Recovery
Current
Body Diode Forward
Current
di/dt
D.U.T. VDS Waveform
Diode Recovery
dv/dt
Re-Applied
Voltage
Body Diode
VDD
Forward Drop
Inductor Curent
Ripple ≤ 5%
ISD
* VGS = 5V for Logic Level Devices
Fig 14. For N-Channel HEXFETS
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7
IRFPC60LC-P
TO-247AC Package Outline
Dimensions are shown in millimeters (inches)
-D -
3.6 5 (.14 3)
3.5 5 (.14 0)
1 5.9 0 (.6 26 )
1 5.3 0 (.6 02 )
-B -
0.2 5 (.0 10 ) M
5 .30 (.20 9)
4 .70 (.18 5)
2 .50 (.0 89 )
1 .50 (.0 59 )
4
D B M
-A 5 .50 (.21 7)
2 0 .30 (.80 0)
1 9 .70 (.77 5)
1
2
NO TE S:
5.50 (.2 1 7)
4.50 (.1 7 7)
2X
1 DIM EN SION ING & TO LER AN CING
P ER A N SI Y14.5M , 1982.
2 CON TR OLLIN G D IM EN SIO N : IN CH .
3 CON F OR M S TO JED E C OU TLIN E
TO-247-A C .
3
-C -
14.8 0 (.5 83 )
14.2 0 (.5 59 )
2 .40 (.0 94 )
2 .00 (.0 79 )
2X
5.45 (.2 1 5)
2X
4 .30 (.1 70 )
3 .70 (.1 45 )
0 .8 0 (.0 31 )
3X 0 .4 0 (.0 16 )
1 .4 0 (.0 56 )
3 X 1 .0 0 (.0 39 )
0.2 5 (.01 0) M
3 .40 (.1 33 )
3 .00 (.1 18 )
2.60 (.10 2)
2.20 (.08 7)
C A S
LE AD A S SIG N ME NTS
1
2
3
4
-
G ATE
DR A IN
SO UR C E
DR A IN
TO-247AC Part Marking Information
E X A M P L E : T H IS IS A N IR F P E 30
W IT H A S S E M B L Y
LOT COD E 3A1Q
A
I N T E R N A T IO N A L
R E C T IF IE R
P AR T N UM B E R
IR F P E 3 0
LOGO
3A1Q
ASSEMBLY
LOT COD E
9302
DATE CO DE
(Y Y W W )
YY = YE A R
W W W EEK
Data and specifications subject to change without notice.
This product has been designed and qualified for the Industrial market.
Qualification Standards can be found on IR’s Web site.
IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105
TAC Fax: (310) 252-7903
Visit us at www.irf.com for sales contact information.04/02
8
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