PHILIPS TDF8704T/4

INTEGRATED CIRCUITS
DATA SHEET
TDF8704
8-bit high-speed analog-to-digital
converter
Product specification
Supersedes data of April 1993
File under Integrated Circuits, IC02
Philips Semiconductors
June 1994
Philips Semiconductors
Product specification
8-bit high-speed analog-to-digital converter
TDF8704
FEATURES
APPLICATIONS
• 8-bit resolution
• General purpose high-speed analog-to-digital
conversion for extended temperature applications
• Sampling rate up to 50 MHz
• Automotive
• Extended temperature range (−40 to +85 °C)
• RF, satellite and GPS (Global Positioning System)
• High signal-to-noise ratio over a large analog input
frequency range (7.4 effective bits at 4.43 MHz full-scale
input and at fclk = 50 MHz)
• Medical
• General industrial
• Binary 3-state TTL outputs
• Digital video (VCR, TV and satellite).
• Overflow/underflow 3-state TTL output
• TTL compatible digital inputs
GENERAL DESCRIPTION
• Low-level AC clock input signal allowed
The TDF8704T is an 8-bit high-speed analog-to-digital
converter (ADC) for general industrial applications. It
converts the analog input signal into 8-bit binary-coded
digital words at a maximum sampling rate of 50 MHz. All
digital inputs and outputs are TTL compatible, although a
low-level AC clock input signal is allowed.
• Stable internal reference voltage regulator included
• Power dissipation only 380 mW (typical)
• Low analog input capacitance, no buffer amplifier
required
• No sample-and-hold circuit required.
QUICK REFERENCE DATA
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
VCCA
analog supply voltage
4.75
5.0
5.25
V
VCCD
digital supply voltage
4.75
5.0
5.25
V
VCCO
output stages supply voltage
4.75
5.0
5.25
V
ICCA
analog supply current
−
37
46
mA
ICCD
digital supply current
−
23
35
mA
ICCO
output stages supply current
−
16
21
mA
ILE
DC integral linear error
−
±0.4
±1
LSB
−
±0.2
±0.5
LSB
−
−
±2
LSB
maximum clock frequency
50
−
−
MHz
total power dissipation
−
380
535
mW
DLE
DC differential linearity error
AILE
AC integral linearity error
fclk(max)
Ptot
note 1
Note
1. Full-scale sine wave (fi = 4.43 MHz; fclk = 50 MHz).
ORDERING INFORMATION
PACKAGE
PINS
PIN POSITION
MATERIAL
CODE
SAMPLING
FREQUENCY
TDF8704T/2
24
SO24L
plastic
SOT137-1
20 MHz
TDF8704T/4
24
SO24L
plastic
SOT137-1
40 MHz
TDF8704T/5
24
SO24L
plastic
SOT137-1
50 MHz
TYPE NUMBER
June 1994
2
Philips Semiconductors
Product specification
8-bit high-speed analog-to-digital converter
TDF8704
BLOCK DIAGRAM
handbook, full pagewidth
V CCA
CLK
VCCD
CE
7
16
18
22
STABILIZER
CLOCK DRIVER
DEC 5
VRT 9
TDF8704
12 D7
13 D6
MSB
14 D5
analog
voltage input
VI 8
15 D4
ANALOG - TO - DIGITAL
CONVERTER
LATCHES
TTL OUTPUTS
23 D3
data outputs
24 D2
1 D1
2 D0
VRB 4
19
21
OVERFLOW / UNDERFLOW
LATCH
OGND 20
output ground
6
AGND
analog ground
11
17
DGND
MSA685
digital ground
Fig.1 Block diagram.
June 1994
TTL OUTPUT
3
LSB
VCCO1
VCCO2
overflow / underflow
output
Philips Semiconductors
Product specification
8-bit high-speed analog-to-digital converter
TDF8704
PINNING
SYMBOL
PIN
DESCRIPTION
D1
1
data output; bit 1
D0
2
data output; bit 0 (LSB)
n.c.
3
not connected
VRB
4
reference voltage BOTTOM
(decoupling)
DEC
5
decoupling input (internal
stabilization loop decoupling)
AGND
6
analog ground
VCCA
7
analog supply voltage (+5 V)
VI
8
VRT
n.c.
D1
1
24
D2
D0
2
23
D3
n.c.
3
22
CE
analog input voltage
V RB
4
21
VCCO2
9
reference voltage TOP (decoupling)
DEC
5
20 OGND
10
not connected
AGND
6
O/UF
11
overflow/underflow data output
D7
12
data output; bit 7 (MSB)
D6
13
data output; bit 6
D5
14
data output; bit 5
D4
15
data output; bit 4
CLK
16
clock input
DGND
17
digital ground
VCCD
18
digital supply voltage (+5 V)
VCCO1
19
supply voltage for output stages 1
(+5 V)
OGND
20
output ground
VCCO2
21
supply voltage for output stages 2
(+5 V)
CE
22
chip enable input (TTL level input,
active LOW)
D3
23
data output; bit 3
D2
24
data output; bit 2
June 1994
handbook, halfpage
19
VCCO1
TDF8704
V CCA
7
18
V CCD
VI
8
17
DGND
V RT
9
16
CLK
n.c.
10
15
D4
O/UF
11
14
D5
D7
12
13
D6
MSA686
Fig.2 Pin configuration.
4
Philips Semiconductors
Product specification
8-bit high-speed analog-to-digital converter
TDF8704
LIMITING VALUES
In accordance with the Absolute Maximum Rating System (IEC134).
SYMBOL
PARAMETER
CONDITIONS
MIN.
MAX.
UNIT
VCCA
analog supply voltage
−0.3
+7.0
V
VCCD
digital supply voltage
−0.3
+7.0
V
VCCO
output stages supply voltage
−0.3
+7.0
V
∆VCC
supply voltage differences between VCCA and VCCD
−1.0
+1.0
V
∆VCC
supply voltage differences between VCCO and VCCD
−1.0
+1.0
V
∆VCC
supply voltage differences between VCCA and VCCO
−1.0
+1.0
V
VI
input voltage
referenced to AGND
−0.3
+7.0
V
Vclk(p-p)
AC input voltage for switching (peak-to-peak value)
referenced to DGND
−
VCCD
V
IO
output current
−
10
mA
Tstg
storage temperature
−55
+150
°C
Tamb
operating ambient temperature
−40
+85
°C
Tj
junction temperature
−
+150
°C
HANDLING
Inputs and outputs are protected against electrostatic discharges in normal handling. However, to be totally safe, it is
desirable to take normal precautions appropriate to handling integrated circuits.
THERMAL CHARACTERISTICS
SYMBOL
Rth j-a
June 1994
PARAMETER
thermal resistance from junction to ambient in free air
5
VALUE
UNIT
75
K/W
Philips Semiconductors
Product specification
8-bit high-speed analog-to-digital converter
TDF8704
CHARACTERISTICS (see Tables 1 and 2)
VCCA = V7 to V6 = 4.75 to 5.25 V; VCCD = V18 to V17 = 4.75 to 5.25 V; VCCO = V19 and V21 to V20 = 4.75 to 5.25 V; AGND
and DGND shorted together; VCCA to VCCD = −0.25 to +0.25 V; VCCO to VCCD = −0.25 to +0.25 V;
VCCA to VCCD = −0.25 to +0.25 V; Tamb = −40 to +85 °C; typical readings taken at VCCA = VCCD = 5 V and Tamb = 25 °C;
unless otherwise specified.
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
Supply
VCCA
analog supply voltage
4.75
5.0
5.25
V
VCCD
digital supply voltage
4.75
5.0
5.25
V
VCCO
output stages supply voltage
4.75
5.0
5.25
V
ICCA
analog supply current
−
37
46
mA
ICCD
digital supply current
−
23
35
mA
ICCO
output stages supply current
−
16
21
mA
all outputs LOW
Inputs
CLOCK INPUT CLK (REFERENCED TO DGND)
VIL
LOW level input voltage
0
−
0.8
V
VIH
HIGH level input voltage
2.0
−
VCCD
V
IIL
LOW level input current
Vclk = 0.4 V
−400
−
−
µA
IIH
HIGH level input current
Vclk = 2.7 V
−
−
100
µA
Vclk = VCCD
−
−
300
µA
ZI
input impedance
fclk = 50 MHz
−
2
−
kΩ
CI
input capacitance
fclk = 50 MHz
−
4.5
−
pF
1.25
1.29
V
VI (ANALOG INPUT VOLTAGE REFERENCED TO AGDN; SEE FIGS 3 AND 4 AND TABLE 1)
VI(B)
input voltage (BOTTOM)
VI(0)
input voltage
output code = 0
1.42
1.48
1.51
V
Vos(B)
offset voltage (BOTTOM)
VI(0) to VI(B)
210
225
240
V
VI(T)
input voltage (TOP)
3.37
3.46
3.58
V
VI(255)
input voltage
output code = 255
3.14
3.22
3.30
V
Vos(T)
offset voltage (TOP)
VI(T) to VI(255)
225
240
255
V
VI(p-p)
input voltage amplitude
(peak-to-peak value)
1.69
1.74
1.79
V
IL
load current on VRT and VRB
−300
−
+300
µA
IIL
LOW level input current
VI = 1.25 V
−
0
−
µA
IIH
HIGH level input current
VI = 3.46 V
40
150
400
µA
ZI
input impedance
fi = 4.43 MHz
−
10
−
kΩ
CI
input capacitance
fi = 4.43 MHz
−
14
−
pF
June 1994
1.21
6
Philips Semiconductors
Product specification
8-bit high-speed analog-to-digital converter
SYMBOL
PARAMETER
TDF8704
CONDITIONS
MIN.
TYP.
MAX.
UNIT
INPUT CE (REFERENCED TO DGND) SEE TABLE 2
VIL
LOW level input voltage
0
−
0.8
V
VIH
HIGH level input voltage
2.0
−
VCCD
V
IIL
LOW level input current
VIL = 0.4 V
−400
−
−
µA
IIH
HIGH level input current
VIH = 2.7 V
−
−
20
µA
VRT to VRB
−
200
−
Ω
IO = 1 mA;
Tamb = 0 to +85 °C
0
−
0.4
V
IO = 1 mA;
Tamb = 0 to −40 °C
−
−
0.6
V
Reference resistance
Rref
reference resistance
Outputs
DIGITAL OUTPUTS D7 TO D0 (REFERENCED TO DGND)
VOL
LOW level output voltage
VOH
HIGH level output voltage
IO = −0.4 mA
2.7
−
VCCD
V
IOZ
output current in 3-state
mode
0.4 V < VO < VCCD
−20
−
+20
µA
TDF8704T/2
20
−
−
MHz
TDF8704T/4
40
−
−
MHz
TDF8704T/5
50
−
−
MHz
Switching characteristics
CLOCK INPUT CLK (NOTE 1; SEE FIG.15)
fclk(max)
maximum clock frequency
tCPH
clock pulse width HIGH
7
−
−
ns
tCPL
clock pulse width LOW
7
−
−
ns
Analog signal processing
LINEARITY
ILE
DC integral linearity error
−
±0.4
±1.0
LSB
DLE
DC differential linearity error
−
±0.2
±0.5
LSB
AILE
AC integral linearity error
note 2
−
−
±2.0
LSB
−0.5 dB analog bandwidth
(note 3)
full-scale sine wave
−
12
−
MHz
75% full-scale sine wave
−
16
−
MHz
tSTLH
analog input settling time
LOW-to-HIGH
full-scale square wave;
Fig.8; note 4
−
2.5
3.5
ns
tSTHL
analog input settling time
HIGH-to-LOW
full-scale square wave;
Fig.8; note 4
−
3.0
4.0
ns
BANDWIDTH (fclk = 40 MHZ)
B
June 1994
7
Philips Semiconductors
Product specification
8-bit high-speed analog-to-digital converter
SYMBOL
PARAMETER
TDF8704
CONDITIONS
MIN.
TYP.
MAX.
UNIT
HARMONICS (fclk = 40 MHZ)
h1
fundamental harmonics
(full scale)
fi = 4.43 MHz
hall
harmonics (full scale);
all components
fi = 4.43 MHz
second harmonics
total harmonic distortion
−
0
dB
−
−64
−60
dB
−
−58
−55
dB
fi = 4.43 MHz
−
−56
−
dB
without harmonics;
fclk = 40 MHz;
fi = 4.43 MHz
46
48
−
dB
fi = 1.25 MHz
−
7.8
−
bits
fi = 4.43 MHz
−
7.6
−
bits
fi = 4.43 MHz
−
7.5
−
bits
fi = 7.5 MHz
−
7.3
−
bits
fi = 10 MHz
−
7.0
−
bits
fi = 4.43 MHz
−
7.4
−
bits
fi = 7.5 MHz
−
7.2
−
bits
fi = 10 MHz
−
6.9
−
bits
fclk = 40 MHz
−
−56
−
dB
10−11
−
times/
samples
third harmonics
THD
−
SIGNAL-TO-NOISE RATIO
S/N
signal-to-noise ratio
EFFECTIVE BITS; NOTE 5; SEE FIGS 9, 10 AND 11
EB
effective bits
TDF8704T/2
fclk = 20 MHz
effective bits
TDF8704T/4
fclk = 40 MHz
effective bits
TDF8704T/5
fclk = 50 MHz
TWO-TONE (NOTE 6)
TTIR
two-tone intermodulation
rejection
BIT ERROR RATE
BER
bit error rate
fclk = 40 MHz;
−
fi = 4.43 MHz;
VI = ±16 LSB at code 128
DIFFERENTIAL GAIN (NOTE 7)
Gdiff
differential gain
fclk = 20 MHz;
fi = 4.43 MHz
−
0.6
−
%
fclk = 40 MHz;
fi = 4.43 MHz
−
0.8
−
deg
DIFFERENTIAL PHASE (NOTE 7)
ϕdiff
June 1994
differential phase
8
Philips Semiconductors
Product specification
8-bit high-speed analog-to-digital converter
SYMBOL
PARAMETER
TDF8704
CONDITIONS
MIN.
TYP.
MAX.
UNIT
Timing (note 8; see Figs 5 and 7; fclk = 50 MHz)
−
−
2
ns
output hold time
5
−
−
ns
output delay time
−
12
15
ns
tds
sampling delay time
th
td
3-state output delay times (see Figs 6 and 7)
tdZH
enable HIGH
−
6
10
ns
tdZL
enable LOW
−
12
16
ns
tdHZ
disable HIGH
−
50
54
ns
tdLZ
disable LOW
−
10
14
ns
Notes
1. In addition to a good layout of the digital and analog ground, it is recommended that the rise and fall times of the clock
must be less than 1 ns.
2. Full-scale sine wave (fi = 4.43 MHz; fclk = 50 MHz).
3. Determined by beat frequency method on a reconstructed sine wave signal for no missing codes and no glitches.
4. The analog input settling time is the minimum time required for the input signal to be stabilized after a sharp full-scale
input (square-wave signal) in order to sample the signal and obtain correct output data.
5. Effective bits are obtained via a Fast Fourier Transform (FFT) treatment taking 4K acquisition points per period. The
calculation takes into account all harmonics and noise up to half of the clock frequency (NYQUIST frequency).
Conversion to signal-to-noise ratio: S/N = EB × 6.02 + 1.76 dB.
6. Intermodulation measured relative to either tone with analog input frequencies of 4.43 MHz and 4.53 MHz. The two
input signals have the same amplitude and the total amplitude of both signals provides full scale to the converter.
7. Measurement taken using video analyser VM700A.
8. Output data acquisition: the output data is available after the maximum delay time of td.
MBD868
3.49
handbook, halfpage
MSA689
3.44
1.29
andbook, halfpage
1.28
V I (T)
V I (B)
V I (T)
V I (B)
(V)
(V)
(V)
(V)
1.27
3.47
3.42
0.1 mV/K
1.26
V I (T)
17 mV/V
V I (T)
3.45
0.05 mV/K
1.25
3.40
1.24
V I (B)
7 mV/V
V I (B)
3.43
60
Fig.3
June 1994
20
20
1.23
60
100
Tamb ( o C)
3.38
4.25
Influence of Tamb on VI(T) and VI(B) under
5 V supply.
Fig.4
9
4.75
5.25
1.22
VCC (V) 5.75
Influence of supply voltage on VI(T) and
VI(B) under Tamb = 25 °C.
Philips Semiconductors
Product specification
8-bit high-speed analog-to-digital converter
Table 1
TDF8704
Output coding and input voltage (typical values; referenced to AGND).
BINARY OUTPUT BITS
VI(p-p)
O/UF
Underflow
<1.48
1
0
1.48
1
−
.
.
.
.
STEP
D7
D6
D5
D4
D3
D2
D1
D0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
254
.
0
1
1
1
1
1
1
1
0
255
3.46
0
1
1
1
1
1
1
1
1
Overflow
>3.46
1
1
1
1
1
1
1
1
1
Table 2
Mode selection.
CE
D7 TO D0
O/UF
1
high impedance
high impedance
0
active; binary
active
t CPL
handbook, full pagewidth
t CPH
1.4 V
CLK
sample N
sample N 1
Vl
sample N 2
N
t ds
th
2.4 V
DATA
D0 to D7
DATA
N 2
DATA
N 1
DATA
N
DATA
N 1
1.4 V
0.4 V
td
Fig.5 Timing diagram for data output.
June 1994
10
MSA688 - 1
Philips Semiconductors
Product specification
8-bit high-speed analog-to-digital converter
handbook, full pagewidth
TDF8704
V CCD
CE
50 %
t dHZ
t dZH
HIGH
90 %
output
data
50 %
t dLZ
LOW
t dZL
HIGH
output
data
50 %
LOW
TEST
V CCD
3.3 kΩ
S1
TDF8704
tdLZ
VCCD
tdZL
VCCD
tdHZ
GND
tdZH
GND
15 pF
MLB880
CE
fCE = 100 kHz.
Fig.6 Timing diagram and test conditions of 3-state output delay time.
handbook, halfpage
D0 to D7
15 pF
MBB956 - 1
Fig.7 Load circuit for timing measurement.
June 1994
S1
10 %
11
Philips Semiconductors
Product specification
8-bit high-speed analog-to-digital converter
TDF8704
t STHL
t STLH
handbook, full pagewidth
code 255
VI
50 %
50 %
code 0
2 ns
2 ns
CLK
50 %
50 %
0.5 ns
MBD869
0.5 ns
Fig.8 Analog input settling-time diagram.
MBD870
0
handbook, full pagewidth
amplitude
(dB)
20
40
60
80
100
120
0
1.25
2.49
3.74
4.98
6.23
7.47
Effective bits: 7.89; THD = −61.05 dB.
Harmonic levels (dB): 2nd = −84.07; 3rd = −62.50; 4th = −92.01; 5th = −66.56; 6th = −101.15.
Fig.9 Fast Fourier Transform (fclk = 20 MHz; fi = 1.25 MHz).
June 1994
12
8.72
f (MHz)
9.96
Philips Semiconductors
Product specification
8-bit high-speed analog-to-digital converter
TDF8704
MBD871
0
handbook, full pagewidth
amplitude
(dB)
20
40
60
80
100
120
0
2.48
4.96
7.44
9.93
12.4
14.9
17.4
f (MHz)
19.9
Effective bits: 7.61; THD = −57.11 dB.
Harmonic levels (dB): 2nd = −68.53; 3rd = −58.36; 4th = −74.89; 5th = −65.37; 6th = −76.08.
Fig.10 Fast Fourier Transform (fclk = 40 MHz; fi = 4.43 MHz).
MBD872
0
handbook, full pagewidth
amplitude
(dB)
20
40
60
80
100
120
0
3.12
6.24
9.35
12.5
15.6
18.7
Effective bits: 6.91; THD = −46.13 dB.
Harmonic levels (dB): 2nd = −59.66; 3rd = −46.67; 4th = −70.80; 5th = −57.96; 6th = −72.16.
Fig.11 Fast Fourier Transform (fclk = 50 MHz; fi = 10 MHz).
June 1994
13
21.8
f (MHz)
24.9
Philips Semiconductors
Product specification
8-bit high-speed analog-to-digital converter
TDF8704
INTERNAL PIN CONFIGURATIONS
handbook, halfpage
VCCO1
handbook, halfpage
VCCO2
V CCA
D7 to D0
O/UF
VI
DGND
AGND
(x 90)
MLB037
MLB036
Fig.12 TTL data and overflow/underflow outputs.
Fig.13 Analog inputs.
book, halfpage
VCCO1
CE
DGND
MLB038
Fig.14 CE (3-state) input.
June 1994
14
Philips Semiconductors
Product specification
8-bit high-speed analog-to-digital converter
handbook, full pagewidth
TDF8704
V CCA
VRT
VRB
DEC
AGND
MSA687
Fig.15 VRB, VRT and DEC.
handbook, full pagewidth
VCCD
V ref
CLK
30 kΩ
DGND
MCD189 - 1
Fig.16 CLK input.
June 1994
30 kΩ
15
Philips Semiconductors
Product specification
8-bit high-speed analog-to-digital converter
TDF8704
APPLICATION INFORMATION
handbook, halfpage
D1
1
D0
2
24
23
D2
D3
(2)
n.c.
3
22
(1)
V RB
4
21
CE
VCCO2
47 pF
AGND
DEC
5
10 nF
AGND
6
AGND
20
19
TDF8704
V CCA
7
VI
8
18
17
OGND
VCCO1
VCCD
DGND
(1)
V RT
100 nF
9
16
CLK
(2)
n.c.
10
O / UF
11
D7
12
15
D4
AGND
14
13
D5
D6
MSA684
The analog and digital supplies should be separated and decoupled.
(1) VRB and VRT are decoupling pins for the internal reference ladder; do not draw current from these pins in order to achieve good linearity.
(2) Pins 3 and 10 should be connected to DGND in order to prevent noise influence.
Fig.17 Application diagram.
June 1994
16
Philips Semiconductors
Product specification
8-bit high-speed analog-to-digital converter
TDF8704
PACKAGE OUTLINE
handbook, full pagewidth
15.6
15.2
7.6
7.4
10.65
10.00
0.1 S
S
A
0.9 (4x)
0.4
24
13
2.45
2.25
1.1
1.0
0.3
0.1
2.65
2.35
0.32
0.23
pin 1
index
1
1.1
0.5
12
detail A
1.27
0.49
0.36
0.25 M
(24x)
Dimensions in mm.
Fig.18 Plastic small outline package; 24 leads; large body; SOT137-1.
June 1994
17
0 to 8o
MBC235 - 1
Philips Semiconductors
Product specification
8-bit high-speed analog-to-digital converter
TDF8704
applied to the substrate by screen printing, stencilling or
pressure-syringe dispensing before device placement.
SOLDERING
Plastic small-outline packages
Several techniques exist for reflowing; for example,
thermal conduction by heated belt, infrared, and
vapour-phase reflow. Dwell times vary between 50 and
300 s according to method. Typical reflow temperatures
range from 215 to 250 °C.
BY WAVE
During placement and before soldering, the component
must be fixed with a droplet of adhesive. After curing the
adhesive, the component can be soldered. The adhesive
can be applied by screen printing, pin transfer or syringe
dispensing.
Preheating is necessary to dry the paste and evaporate
the binding agent. Preheating duration: 45 min at 45 °C.
Maximum permissible solder temperature is 260 °C, and
maximum duration of package immersion in solder bath is
10 s, if allowed to cool to less than 150 °C within 6 s.
Typical dwell time is 4 s at 250 °C.
REPAIRING SOLDERED JOINTS (BY HAND-HELD SOLDERING
IRON OR PULSE-HEATED SOLDER TOOL)
Fix the component by first soldering two, diagonally
opposite, end pins. Apply the heating tool to the flat part of
the pin only. Contact time must be limited to 10 s at up to
300 °C. When using proper tools, all other pins can be
soldered in one operation within 2 to 5 s at between 270
and 320 °C. (Pulse-heated soldering is not recommended
for SO packages.)
A modified wave soldering technique is recommended
using two solder waves (dual-wave), in which a turbulent
wave with high upward pressure is followed by a smooth
laminar wave. Using a mildly-activated flux eliminates the
need for removal of corrosive residues in most
applications.
For pulse-heated solder tool (resistance) soldering of VSO
packages, solder is applied to the substrate by dipping or
by an extra thick tin/lead plating before package
placement.
BY SOLDER PASTE REFLOW
Reflow soldering requires the solder paste (a suspension
of fine solder particles, flux and binding agent) to be
DEFINITIONS
Data sheet status
Objective specification
This data sheet contains target or goal specifications for product development.
Preliminary specification
This data sheet contains preliminary data; supplementary data may be published later.
Product specification
This data sheet contains final product specifications.
Limiting values
Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or
more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation
of the device at these or at any other conditions above those given in the Characteristics sections of the specification
is not implied. Exposure to limiting values for extended periods may affect device reliability.
Application information
Where application information is given, it is advisory and does not form part of the specification.
LIFE SUPPORT APPLICATIONS
These products are not designed for use in life support appliances, devices, or systems where malfunction of these
products can reasonably be expected to result in personal injury. Philips customers using or selling these products for
use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such
improper use or sale.
June 1994
18
Philips Semiconductors
Product specification
8-bit high-speed analog-to-digital converter
NOTES
June 1994
19
TDF8704
Philips Semiconductors – a worldwide company
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Philips Semiconductors
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Telex 35000 phtcnl, Fax. +31-40-724825
SCD31
© Philips Electronics N.V. 1994
All rights are reserved. Reproduction in whole or in part is prohibited without the
prior written consent of the copyright owner.
The information presented in this document does not form part of any quotation
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use. Publication thereof does not convey nor imply any license under patent- or
other industrial or intellectual property rights.
Printed in The Netherlands
533061/1500/03/pp20
Document order number:
Date of release: June 1994
9397 734 10011