INTEGRATED CIRCUITS DATA SHEET TDA8761 9-bit analog-to-digital converter for digital video Preliminary specification File under Integrated Circuits, IC02 Philips Semiconductors 1995 Mar 20 Philips Semiconductors Preliminary specification 9-bit analog-to-digital converter for digital video TDA8761 FEATURES APPLICATIONS • 9-bit resolution Analog-to-digital conversion for: • Sampling rate up to 30 MHz • Video data digitizing • DC sampling allowed • Digital Video Broadcasting (DVB) • One clock cycle conversion only • Cable TV. • High signal-to-noise ratio over a large analog input frequency range (8.5 effective bits at 10 MHz full-scale input at fclk = 30 MHz) GENERAL DESCRIPTION The TDA8761 is a 9-bit analog-to-digital converter (ADC) for professional video and digital video set box applications. It converts the analog input signal into 9-bit binary-coded digital words at a maximum sampling rate of 30 MHz. Its linearity performance ensures the required conversion accuracy in case of 256QAM demodulator concept and for all symbol frequencies. All digital inputs and outputs are TTL compatible, although a low-level sine wave clock input signal is allowed. • No missing codes guaranteed • In range (IR) 3-state TTL output • TTL compatible digital inputs and outputs • Low-level AC clock input signal allowed • External reference voltage regulator • Power dissipation only 360 mW (typical) • Low analog input capacitance, no buffer amplifier required • No sample-and-hold circuit required. QUICK REFERENCE DATA SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT VCCA analog supply voltage 4.75 5.0 5.25 V VCCD digital supply voltage 4.75 5.0 5.25 V VCCO output stages supply voltage 4.4 5.0 5.25 V ICCA analog supply current − 30 tbf mA ICCD digital supply current − 22 tbf mA ICCO output stages supply current − 22 tbf mA AINL AC integral non-linearity note 1; full scale input sine wave − ±0.75 tbf LSB note 1; 50% full scale input sine wave − ±0.5 tbf LSB ADNL AC differential non-linearity note 1; full scale input sine wave − ±0.5 tbf LSB note 1; 50% full scale input sine wave − ±0.3 tbf LSB fclk(max) maximum clock frequency 30 − − MHz Ptot total power dissipation − 360 tbf mW Note 1. fi = 11 MHz and fclk = 30 MHz; fi = 8 MHz and fclk = 20 MHz. ORDERING INFORMATION PACKAGE TYPE NUMBER NAME TDA8761M SSOP28 1995 Mar 20 DESCRIPTION plastic shrink small outline package; 28 leads; body width 5.3 mm 2 VERSION SOT341-1 Philips Semiconductors Preliminary specification 9-bit analog-to-digital converter for digital video TDA8761 BLOCK DIAGRAM handbook, full pagewidth V CCA CLK VCCD CE 3 1 11 10 2 CLOCK DRIVER VRT TC TDA8761 9 25 D8 24 D7 MSB 23 D6 22 D5 analog voltage input VI VRM 8 ANALOG -TO - DIGITAL CONVERTER LATCHES TTL OUTPUTS 21 D4 data outputs 20 D3 19 D2 7 18 D1 17 D0 13 VRB 6 LSB VCCO1 28 VCCO2 IN RANGE LATCH 4 AGND1 5 AGND2 analog grounds 12 14 OGND1 digital ground output grounds 3 26 27 DGND Fig.1 Block diagram. 1995 Mar 20 TTL OUTPUT OGND2 MGC355 IR output Philips Semiconductors Preliminary specification 9-bit analog-to-digital converter for digital video TDA8761 PINNING SYMBOL PIN DESCRIPTION CLK 1 clock input TC 2 two’s complement input (active LOW) VCCA 3 analog supply voltage (+5 V) AGND1 4 analog ground 1 AGND2 5 analog ground 2 VRB 6 reference voltage BOTTOM input VRM 7 reference voltage MIDDLE VI 8 analog input voltage VRT 9 reference voltage TOP input CE 10 chip enable input (TTL level input, active LOW) VCCD 11 digital supply voltage (+5 V) DGND 12 digital ground VCCO1 13 supply voltage for output stages 1 (+5 V) OGND1 14 output ground 1 n.c. 15 not connected n.c. 16 not connected D0 17 data output; bit 0 (LSB) D1 18 data output; bit 1 D2 19 data output; bit 2 D3 20 data output; bit 3 D4 21 data output; bit 4 D5 22 data output; bit 5 D6 23 data output; bit 6 D7 24 data output; bit 7 D8 25 data output; bit 8 (MSB) IR 26 in range data output OGND2 27 output ground 2 VCCO2 28 supply voltage for output stages 2 (+5 V) 1995 Mar 20 handbook, halfpage CLK 1 28 VCCO2 TC 2 27 OGND2 VCCA 3 26 IR AGND1 4 25 D8 AGND2 5 24 D7 VRB 6 23 D6 VRM 7 VI 8 21 D4 VRT 9 20 D3 CE 10 19 D2 VCCD 11 18 D1 DGND 12 17 D0 V CCO1 13 16 n.c. OGND1 14 15 n.c. 22 D5 TDA8761 MGC356 Fig.2 Pin configuration. 4 Philips Semiconductors Preliminary specification 9-bit analog-to-digital converter for digital video TDA8761 LIMITING VALUES In accordance with the Absolute Maximum Rating System (IEC 134). SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT VCCA analog supply voltage note 1 −0.3 +7.0 V VCCD digital supply voltage note 1 −0.3 +7.0 V VCCO output stages supply voltage note 1 −0.3 +7.0 V ∆VCC supply voltage differences between VCCA and VCCD −1.0 +1.0 V VCCO and VCCD −1.0 +1.0 V −1.0 +1.0 V VI input voltage referenced to AGND −0.3 +7.0 V Vi(p-p) AC input voltage for switching (peak-to-peak value) referenced to DGND − VCCD V VCCA and VCCO IO output current − 10 mA Tstg storage temperature −55 +150 °C Tamb operating ambient temperature 0 +70 °C Tj junction temperature − +150 °C Note 1. The supply voltages VCCA, VCCD and VCCO may have any value between −0.3 V and +7.0 V provided the difference between VCCA, VCCD and VCCO is between −1 and +1 V. HANDLING Inputs and outputs are protected against electrostatic discharges in normal handling. However, to be totally safe, it is desirable to take normal precautions appropriate to handling integrated circuits. THERMAL CHARACTERISTICS SYMBOL Rth j-a 1995 Mar 20 PARAMETER thermal resistance from junction to ambient in free air 5 VALUE UNIT 110 K/W Philips Semiconductors Preliminary specification 9-bit analog-to-digital converter for digital video TDA8761 CHARACTERISTICS VCCA = V3 to V4 and V5 = 4.75 to 5.25 V; VCCD = V11 to V12 = 4.75 to 5.25 V; VCCO = V13 and V28 to V14 and V27 = 4.4 to 5.25 V; AGND and DGND shorted together; Tamb = 0 to +70 °C; typical values measured at VCCA = VCCD = VCCO = 5 V; Vi(p-p) = 1.5 V; CL = 15 pF and Tamb = 25 °C; unless otherwise specified. SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT Supply VCCA analog supply voltage 4.75 5.0 5.25 V VCCD digital supply voltage 4.75 5.0 5.25 V VCCO output stages supply voltage 4.4 5.0 5.25 V ∆VCC supply voltage differences between VCCA and VCCD −0.25 − +0.25 V VCCA and VCCO −0.4 − +0.4 V VCCD and VCCO −0.4 − +0.4 V ICCA analog supply current − 30 tbf mA ICCD digital supply current − 22 tbf mA ICCO output stages supply current − 22 tbf mA 0 − 0.8 V Inputs CLOCK INPUT CLK (REFERENCED TO DGND); note 1 VIL LOW level input voltage VIH HIGH level input voltage 2.0 − VCCD V IIL LOW level input current Vclk = 0.4 V −1 0 +1 µA IIH HIGH level input current Vclk = 2.7 V − − 20 µA ZI input impedance fclk = 30 MHz − 2 − kΩ CI input capacitance fclk = 30 MHz − 2 − pF INPUT CE (REFERENCED TO DGND); see Table 2 VIL LOW level input voltage 0 − 0.8 V VIH HIGH level input voltage 2.0 − VCCD V IIL LOW level input current VIL = 0.4 V −400 − − µA IIH HIGH level input current VIH = 2.7 V − − 20 µA − 0 − µA VI (ANALOG INPUT VOLTAGE REFERENCED TO AGND) IIL LOW level input current VI = 1.3 V IIH HIGH level input current VI = 3.8 V − 70 − µA ZI input impedance fi = 10 MHz − 5 − kΩ CI input capacitance fi = 10 MHz − 8 − pF 1995 Mar 20 6 Philips Semiconductors Preliminary specification 9-bit analog-to-digital converter for digital video SYMBOL PARAMETER TDA8761 CONDITIONS MIN. TYP. MAX. UNIT Reference voltages for the resistor ladder; see Table 1 VRB reference voltage BOTTOM 1.2 1.3 − VRT reference voltage TOP − 3.3 VCCA − 0.8 V V Vdiff differential reference voltage VRT − VRB 1.8 2.0 3.0 V V Iref reference current − 30 − mA RLAD resistor ladder − 85 − Ω TCRLAD temperature coefficient of the resistor ladder − 1.86 − ppm − 158 − mΩ/K VosB offset voltage BOTTOM note 2 − 250 − mV VosT offset voltage TOP note 2 − 250 − mV Vi(p-p) analog input voltage (peak-to-peak value) note 3 1.3 1.5 2.5 V Outputs DIGITAL OUTPUTS D8 TO D0 AND IR (REFERENCED TO OGND) VOL LOW level output voltage IO = 1 mA 0 − 0.4 V VOH HIGH level output voltage IO = 0 mA 2.7 − VCCO − 0.5 V IO = −0.4 mA 2.7 − VCCO − 1.3 V IOZ output current in 3-state mode IO = −1 mA 2.4 − VCCO − 1.4 V 0.4 V < VO < VCCO −20 − +20 µA Switching characteristics CLOCK INPUT CLK; see Fig.3; note 1 fclk(max) maximum clock frequency 30 − − MHz tCPH clock pulse width HIGH 10 − − ns tCPL clock pulse width LOW 10 − − ns note 5; full scale input sine wave − ±0.75 tbf LSB note 5; 50% full scale input sine wave − ±0.5 tbf LSB note 5; full scale input sine wave − ±0.5 tbf LSB note 5; 50% full scale input sine wave − ±0.3 tbf LSB ±1 − LSB ±0.1 − % Analog signal processing LINEARITY AINL ADNL AC integral non-linearity AC differential non-linearity OFER offset error − middle code; VRB = 1.3 V; VRT = 3.3 V GER gain error (from device to device) VRB = 1.3 V; VRT = 3.3 V; note 4 1995 Mar 20 7 − Philips Semiconductors Preliminary specification 9-bit analog-to-digital converter for digital video SYMBOL PARAMETER TDA8761 CONDITIONS MIN. TYP. MAX. UNIT BANDWIDTH (fclk = 30 MHz) B analog bandwidth full-scale sine wave; note 6 − 40 − MHz 75% full-scale sine wave; note 6 − 55 − MHz small signal at mid-scale; VI = ±10 LSB at code 256; note 6 − 700 − MHz tSTLH analog input settling time LOW-to-HIGH full-scale square wave; Fig.5; note 7 − 2.0 tbf ns tSTHL analog input settling time HIGH-to-LOW full-scale square wave; Fig.5; note 7 − 2.5 tbf ns fi = 10 MHz − −64 − dB without harmonics; fclk = 30 MHz; fi = 10 MHz 53 55 − dB fclk = 30 MHz; fi = 10 MHz − 8.5 − bits fclk = 30 MHz − −64 − dB fclk = 30 MHz; fi = 10 MHz; VI = ±16 LSB at code 256 − 10−13 − times/ sample fclk = 30 MHz; PAL modulated ramp − tbf − % fclk = 30 MHz; PAL modulated ramp − tbf − deg HARMONICS (fclk = 30 MHZ) THD total harmonic distortion SIGNAL-TO-NOISE RATIO; see Fig.7; note 8 S/N signal-to-noise ratio (full scale) EFFECTIVE BITS; see Fig 6; note 8 EB effective bits TWO-TONE; note 9 TTIR two-tone intermodulation rejection BIT ERROR RATE BER bit error rate DIFFERENTIAL GAIN; note 10 Gdiff differential gain DIFFERENTIAL PHASE; note 10 ϕdiff differential phase Timing (fclk = 30 MHz; CL = 15 pF); see Fig.3; note 11 tds sampling delay time − − 2 ns th output hold time 5 − − ns td output delay time − 10 14 ns CL digital output load − 15 40 pF 1995 Mar 20 8 Philips Semiconductors Preliminary specification 9-bit analog-to-digital converter for digital video SYMBOL PARAMETER TDA8761 CONDITIONS MIN. TYP. MAX. UNIT 3-state output delay times; see Fig.4 tdZH enable HIGH − tbf tbf ns tdZL enable LOW − tbf tbf ns tdHZ disable HIGH − tbf tbf ns tdLZ disable LOW − tbf tbf ns Notes 1. In addition to a good layout of the digital and analog ground, it is recommended that the rise and fall times of the clock must not be less than 0.5 ns. 2. Analog input voltages producing code 0 up to and including code 511: a) VosB (voltage offset BOTTOM) is the difference between the analog input which produces data equal to 00 and the reference voltage BOTTOM (VRB) at Tamb = 25 °C. b) VosT (voltage offset TOP) is the difference between VRT (reference voltage TOP) and the analog input which produces data outputs equal to code 511 at Tamb = 25 °C. ( V RT – V RB ) × 8 3. Analog input voltage range can be derived from VRT − VRB difference. It is ------------------------------------------9 4. ( V 511 – V 0 ) – 1.5 V GER = --------------------------------------------------- × 100 1.5 V 5. fi = 11 MHz and fclk = 30 MHz; fi = 8 MHz and fclk = 20 MHz. 6. The analog bandwidth is defined as the maximum input sine wave frequency which can be applied to the device. No glitches greater than 2 LSBs, neither any significant attenuation are observed in the reconstructed signal. 7. The analog input settling time is the minimum time required for the input signal to be stabilized after a sharp full-scale input (square-wave signal) in order to sample the signal and obtain correct output data. 8. Effective bits are obtained via a Fast Fourier Transform (FFT) treatment taking 8K acquisition points per equivalent fundamental period. The calculation takes into account all harmonics and noise up to half of the clock frequency (NYQUIST frequency). Conversion to signal-to-noise ratio: S/N = EB × 6.02 + 1.76 dB. 9. Intermodulation measured relative to either tone with analog input frequencies of 10.0 MHz and 10.10 MHz. The two input signals have the same amplitude and the total amplitude of both signals provides full scale to the converter. 10. Measurement carried out using video analyser VM700A, where the video analog signal is reconstructed through a digital-to-analog converter. 11. Output data acquisition: the output data is available after the maximum delay time of td. 1995 Mar 20 9 Philips Semiconductors Preliminary specification 9-bit analog-to-digital converter for digital video Table 1 TDA8761 Output coding and input voltage (typical values; referenced to AGND, VRB = 1.3 V, VRT = 3.3 V) BINARY OUTPUT BITS STEP VI(p-p) IR U/F <1.55 0 TWO’S COMPLEMENT OUTPUT BITS D8 D7 D6 D5 D4 D3 D2 D1 D0 D8 D7 D6 D5 D4 D3 D2 D1 D0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1.55 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 . 1 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 510 . 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 511 3.05 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 O/F >3.05 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Table 2 Mode selection TC CE D8 TO D0 IR X 1 high impedance 0 0 active; two’s complement active 1 0 active; binary active high impedance t CPL handbook, full pagewidth t CPH 1.4 V CLK sample N sample N + 1 sample N + 2 Vl t ds th 2.4 V DATA D0 to D8 DATA N-2 DATA N-1 DATA N DATA N+1 1.4 V 0.4 V td Fig.3 Timing diagram. 1995 Mar 20 10 MGC357 Philips Semiconductors Preliminary specification 9-bit analog-to-digital converter for digital video handbook, full pagewidth TDA8761 V CCD 50 % CE t dHZ t dZH HIGH 90 % output data 50 % t dLZ LOW t dZL HIGH output data 50 % LOW 10 % V CCD 3.3 kΩ S1 TDA8761 15 pF TEST S1 t dLZ t dZL VCCD VCCD t dHZ GND t dZH GND CE MGC358 f CE = 100 kHz. Fig.4 Timing diagram and test conditions of 3-state output delay time. 1995 Mar 20 11 Philips Semiconductors Preliminary specification 9-bit analog-to-digital converter for digital video TDA8761 t STHL t STLH handbook, full pagewidth code 511 VI 50 % 50 % code 0 2 ns 2 ns CLK 50 % 50 % 0.5 ns MGC359 0.5 ns Fig.5 Analog input settling-time diagram. MGC360 0 handbook, full pagewidth amplitude (dB) 20 40 60 80 100 120 0 1.88 3.75 5.63 7.50 9.37 11.3 Effective bits: 8.58; THD = −61.80 dB. Harmonic levels (dB): 2nd = −64.77; 3rd = −79.30; 4th = −71.90; 5th = −66.12; 6th = −82.29. Fig.6 Fast Fourier Transform (fclk = 30 MHz; fi = 10 MHz). 1995 Mar 20 12 13.1 f (MHz) 15.0 Philips Semiconductors Preliminary specification 9-bit analog-to-digital converter for digital video TDA8761 INTERNAL PIN CONFIGURATIONS handbook, halfpage VCCO2 handbook, halfpage VCCO1 V CCA D8 to D0 O/UF VI OGND1 AGND MGC040 MGC361 Fig.7 TTL data and in-range outputs. Fig.8 Analog inputs. ndbook, halfpage VCCO1 VCCA handbook, halfpage VRT VRM CE (TC) R LAD VRB AGND OGND2 MGC041 Fig.9 CE (TC) 3-state input. 1995 Mar 20 Fig.10 VRB, VRM and VRT. 13 MEA050 Philips Semiconductors Preliminary specification 9-bit analog-to-digital converter for digital video handbook, full pagewidth TDA8761 VCCD V ref (1.3 V) CLK DGND MGC042 Fig.11 CLK input. 1995 Mar 20 14 Philips Semiconductors Preliminary specification 9-bit analog-to-digital converter for digital video TDA8761 APPLICATION INFORMATION handbook, halfpage CLK TC VCCA AGND1 AGND2 V CCO2 1 28 2 27 3 26 4 25 5 24 6 23 D6 7 22 OGND2 IR D8 D7 (1) V RB 100 nF (1) V RM AGND VI 100 nF D5 TDA8761 8 21 9 20 10 19 11 18 12 17 13 16 14 15 D4 (1) V RT AGND D3 100 nF CE D2 AGND V CCD DGND V CCO1 D1 D0 (2) n.c. (2) OGND1 n.c. MGC362 The analog and digital supplies should be separated and decoupled. The external voltage generator must be built such that a good supply voltage ripple rejection is achieved with respect to the LSB value. Eventually, the reference ladder voltages can be derived from a well regulated VCCA supply through a resistor bridge and a decoupled capacitor. For applications where the input signal must remain well centred around middle scale, VRM must be decoupled and connected to analog input signal (pin 8) through a resistor. The values must be defined in accordance with the input signal frequency in order to avoid direct coupling into the ADC ladder (e.g. R = 5 kΩ and C = 100 nF). (1) VRB, VRM and VRT are decoupled to AGND. (2) Pins 15 and 16 should be connected to DGND in order to prevent noise influence. Fig.12 Application diagram. 1995 Mar 20 15 Philips Semiconductors Preliminary specification 9-bit analog-to-digital converter for digital video TDA8761 PACKAGE OUTLINE SSOP28: plastic shrink small outline package; 28 leads; body width 5.3 mm D SOT341-1 E A X c HE y v M A Z 28 15 Q A2 A (A 3) A1 pin 1 index θ Lp L 1 14 w M bp e detail X 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (1) e HE L Lp Q v w y Z (1) θ mm 2.0 0.21 0.05 1.80 1.65 0.25 0.38 0.25 0.20 0.09 10.4 10.0 5.4 5.2 0.65 7.9 7.6 1.25 1.03 0.63 0.9 0.7 0.2 0.13 0.1 1.1 0.7 8 0o Note 1. Plastic or metal protrusions of 0.20 mm maximum per side are not included. OUTLINE VERSION SOT341-1 1995 Mar 20 REFERENCES IEC JEDEC EIAJ EUROPEAN PROJECTION ISSUE DATE 93-09-08 95-02-04 MO-150AH 16 o Philips Semiconductors Preliminary specification 9-bit analog-to-digital converter for digital video TDA8761 Several techniques exist for reflowing; for example, thermal conduction by heated belt, infrared, and vapour-phase reflow. Dwell times vary between 50 and 300 s according to method. Typical reflow temperatures range from 215 to 250 °C. SOLDERING Plastic small outline packages BY WAVE During placement and before soldering, the component must be fixed with a droplet of adhesive. After curing the adhesive, the component can be soldered. The adhesive can be applied by screen printing, pin transfer or syringe dispensing. Preheating is necessary to dry the paste and evaporate the binding agent. Preheating duration: 45 min at 45 °C. REPAIRING SOLDERED JOINTS (BY HAND-HELD SOLDERING IRON OR PULSE-HEATED SOLDER TOOL) Maximum permissible solder temperature is 260 °C, and maximum duration of package immersion in solder bath is 10 s, if allowed to cool to less than 150 °C within 6 s. Typical dwell time is 4 s at 250 °C. Fix the component by first soldering two, diagonally opposite, end pins. Apply the heating tool to the flat part of the pin only. Contact time must be limited to 10 s at up to 300 °C. When using proper tools, all other pins can be soldered in one operation within 2 to 5 s at between 270 and 320 °C. (Pulse-heated soldering is not recommended for SO packages.) A modified wave soldering technique is recommended using two solder waves (dual-wave), in which a turbulent wave with high upward pressure is followed by a smooth laminar wave. Using a mildly-activated flux eliminates the need for removal of corrosive residues in most applications. For pulse-heated solder tool (resistance) soldering of VSO packages, solder is applied to the substrate by dipping or by an extra thick tin/lead plating before package placement. BY SOLDER PASTE REFLOW Reflow soldering requires the solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the substrate by screen printing, stencilling or pressure-syringe dispensing before device placement. DEFINITIONS Data sheet status Objective specification This data sheet contains target or goal specifications for product development. Preliminary specification This data sheet contains preliminary data; supplementary data may be published later. Product specification This data sheet contains final product specifications. Limiting values Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Where application information is given, it is advisory and does not form part of the specification. LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale. 1995 Mar 20 17 Philips Semiconductors Preliminary specification 9-bit analog-to-digital converter for digital video TDA8761 NOTES 1995 Mar 20 18 Philips Semiconductors Preliminary specification 9-bit analog-to-digital converter for digital video TDA8761 NOTES 1995 Mar 20 19 Philips Semiconductors – a worldwide company Argentina: IEROD, Av. Juramento 1992 - 14.b, (1428) BUENOS AIRES, Tel. (541)786 7633, Fax. (541)786 9367 Australia: 34 Waterloo Road, NORTH RYDE, NSW 2113, Tel. (02)805 4455, Fax. (02)805 4466 Austria: Triester Str. 64, A-1101 WIEN, P.O. Box 213, Tel. (01)60 101-1236, Fax. (01)60 101-1211 Belgium: Postbus 90050, 5600 PB EINDHOVEN, The Netherlands, Tel. (31)40 783 749, Fax. (31)40 788 399 Brazil: Rua do Rocio 220 - 5th floor, Suite 51, CEP: 04552-903-SÃO PAULO-SP, Brazil. P.O. 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(02)92 0601 Internet: http://www.semiconductors.philips.com/ps/ For all other countries apply to: Philips Semiconductors, International Marketing and Sales, Building BE-p, P.O. Box 218, 5600 MD EINDHOVEN, The Netherlands, Telex 35000 phtcnl, Fax. +31-40-724825 SCD39 © Philips Electronics N.V. 1995 All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights. Printed in The Netherlands 533061/1500/01/pp20 Document order number: Date of release: 1995 Mar 20 9397 750 00112