INTEGRATED CIRCUITS DATA SHEET TDA8706 6-bit analog-to-digital converter with multiplexer and clamp Preliminary specification Supersedes data of February 1992 File under Integrated Circuits, IC02 1996 Aug 20 Philips Semiconductors Preliminary specification 6-bit analog-to-digital converter with multiplexer and clamp TDA8706 FEATURES GENERAL DESCRIPTION • 6-bit resolution The TDA8706 is a monolithic bipolar 6-bit Analog-to-Digital Converter (ADC) with a 3 analog input multiplexer and a clamp. All digital inputs and outputs are TTL compatible. Regulator with good temperature compensation. • Binary 3-state TTL outputs • TTL compatible digital inputs • 3 multiplexed video inputs • Luminance and colour difference clamps • Internal reference FUNCTIONAL DESCRIPTION • 300 mW power dissipation The TDA8706 is a ‘like-flash’ converter which produces an output code in one clock period. The device can withstand a duty clock cycle of 50 to 66.6% (clock HIGH). Luminance clamping level is fitted with 00H code (output 000000). Chrominance clamping level is fitted with 20H code (output 100000). • 20-pin plastic package. APPLICATIONS • General purpose video applications • Y, U and V signals • Colour Picture-in-Picture (PIPCO) for TV • Videophone • Frame grabber. QUICK REFERENCE DATA Measured over full voltage and temperature ranges. SYMBOL PARAMETER MIN. TYP. MAX. UNIT VCCA analog supply voltage (pin 2) 4.5 5.0 5.5 V VCCD digital supply voltage (pin 10) 4.5 5.0 5.5 V ICCA analog supply current (pin 20) − 32 39 mA ICCD digital supply current (pin 10) − 28 37 mA ILE integral linearity error − − ±0.75 LSB DLE DC differential linearity error − − ±0.5 LSB fCLK maximum clock frequency 20 − − MHz Ptot total power dissipation − 300 418 mW Tamb operating ambient temperature range 0 − +70 °C ORDERING INFORMATION TYPE NUMBER PACKAGE NAME DESCRIPTION VERSION TDA8706 DIP20 plastic dual in-line package; 20 leads (300 mil) SOT146-1 TDA8706T SO20 plastic small outline package; 20 leads; body width 7.5 mm SOT163-1 1996 Aug 20 2 1996 Aug 20 3 clamp input 12 7 6 chrominance input luminance input 5 chrominance input 11 VCCD 2 VCCA TDA8706 LUMINANCE CLAMP CHROMINANCE CLAMP CHROMINANCE CLAMP C 8 B A 10 reference voltage TOP 3 reference voltage BOTTOM 4 REGULATOR 6-BIT ADC 1 ground TTL OUTPUTS 14 13 D0 MCD267 20 D1 19 D3 17 D2 D4 16 18 D5 15 digital voltage outputs 6-bit analog-to-digital converter with multiplexer and clamp handbook, full pagewidth Fig.1 Block diagram. select inputs 9 MULTIPLEXER chip enable clock input Philips Semiconductors Preliminary specification TDA8706 BLOCK DIAGRAM Philips Semiconductors Preliminary specification 6-bit analog-to-digital converter with multiplexer and clamp TDA8706 PINNING SYMBOL PIN DESCRIPTION GND 1 ground VCCA 2 analog positive supply (+5 V) VRT 3 reference voltage TOP decoupling VRB 4 reference voltage BOTTOM decoupling handbook, halfpage GND 1 20 D0 INC 5 chrominance input V CCA 2 19 D1 INB 6 chrominance input V RT 3 18 D2 INA 7 luminance input 17 D3 8 select input VRB 4 C B 9 select input INC 5 A 10 select input INB 6 15 D5 VCCD 11 digital positive supply voltage (+5 V) INA 7 14 CE CLAMP 12 damp pulse input (positive pulse) C 8 13 CLK CLK 13 clock input B 9 12 CLAMP CE 14 chip enable (active LOW) A 10 D5 15 digital voltage output: most significant bit (MSB) D4 16 digital voltage output D3 17 digital voltage output D2 18 digital voltage output D1 19 digital voltage output D0 20 digital voltage output: significant bit (LSB) 1996 Aug 20 16 D4 TDA8706 11 VCCD MCD266 Fig.2 Pin configuration. 4 Philips Semiconductors Preliminary specification 6-bit analog-to-digital converter with multiplexer and clamp TDA8706 LIMITING VALUES In accordance with the Absolute Maximum System (IEC 134). SYMBOL PARAMETER MIN. MAX. UNIT VCCA analog supply voltage range (pin 2) −0.3 +7.0 V VCCD digital supply voltage range (pin 10) −0.3 +7.0 V VCCA − VCCD supply voltage difference 1.0 − V VI input voltage range −0.3 +7.0 V IO output current − 10 mA Tstg storage temperature range −55 +150 °C Tamb operating ambient temperature range 0 +70 °C HANDLING Inputs and outputs are protected against electrostatic discharges in normal handling. However, to be totally safe, it is desirable to take normal precautions appropriate to handling integrated circuits. 1996 Aug 20 5 Philips Semiconductors Preliminary specification 6-bit analog-to-digital converter with multiplexer and clamp TDA8706 CHARACTERISTICS (see Tables 1 and 2) VCCA = 4.5 to 5.5 V; VCCD = 4.5 to 5.5 V = VCCD; Tamb = 0 to +70 °C; CVRB = CVR1 = 100 nF; Typical values measured at VCCA = VCCD = 5 V and Tamb = 25 °C; unless otherwise specified. SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT Supply VCCA analog supply voltage (pin 2) 4.5 5.0 5.5 V VCCD digital supply voltage (pin 10) 4.5 5.0 5.5 V ICCA analog supply current (pin 2) − 32 39 mA ICCD digital supply current (pin 10) all outputs at LOW level − 28 37 mA Inputs CLOCK INPUT (PIN 13) VIL LOW level input voltage 0 − 0.8 V VIH HIGH level input voltage 2.0 − VCCD V IIL LOW level input current VCLK = 0.4 V −400 − − µA IIH HIGH level input current VCLK = 2.7 V − − 100 µA ZI input impedance fCLK = 20 MHz − 4 − kΩ Ci input capacitance fCLK = 20 MHz − 2 − pF A, B, C, CLAMP AND CEN INPUTS (PINS 8, 9, 10, 12 AND 14) VIL LOW level input voltage 0 − 0.8 V VIH HIGH level input voltage 2 − VCCD V IIL LOW level input current VCLK = 0.4 V −400 − − µA IIH HIGH level input current VCLK = 2.7 V − − 20 µA Reference voltage (pins 3 and 4) VRT reference voltage TOP decoupling 3.22 3.35 3.44 V VRB reference voltage BOTTOM decoupling 1.84 1.9 1.96 V 1.36 1.435 1.48 V 840 900 940 mV 100 − − kΩ 1 10 1000 nF VRT − VRB reference voltage TOP − BOTTOM decoupling Analog inputs INA, INB, INC (pins 7, 6 and 5) VI(p-p) input voltage amplitude (peak-to-peak value) ZI input impedance Cclamp coupling clamp capacitance fi = 4.43 MHz Analog signal processing (pins 5, 6 and 7) (fCLK = 20 MHz) f1 fundamental harmonics (full scale) fi = 4.43 MHz − − 0 dB fall harmonics (full scale); all components fi = 4.43 MHz − −45 − dB Gdiff differential gain note 1 − 0.4 − % φdiff differential phase note 1 − 1.0 − deg SVRR supply voltage ripple rejection note 2 − −30 − dB 1996 Aug 20 6 Philips Semiconductors Preliminary specification 6-bit analog-to-digital converter with multiplexer and clamp SYMBOL TDA8706 PARAMETER CONDITIONS MIN. TYP. MAX. UNIT Outputs DIGITAL VOLTAGE OUTPUTS (PINS 15 TO 20) (see Table 2) VOL LOW level input voltage IO = 1 mA 0 − 0.4 V VOH HIGH level output voltage IO = 0.5 mA 2.7 − VCCD V IOZ output current in 3-state mode 0.4 V < VO < VCCD −20 − +20 µA Switching characteristics CLOCK TIMING (see Fig.3) fCLK maximum clock frequency 20 − − MHz fmux maximum multiplexing frequency 10 − − MHZ 50 − − ns duty cycle CLK = VIH 45 50 66.6 % tLOW LOW time at 50% 16 − − ns tHIGH HIGH time at 50% 22.5 − − ns tCLR rise time at 10 to 90% 4 6 − ns tCLF fall time at 90 to 10% 4 6 − ns 35 − − ns tCLK period Select signals, Clamp, Data (see Figs 4 and 5) tS set-up time select A, B and C tr rise time A, B and band C at 10 to 90% 4 6 − ns tf fall time A, B and band C at 90 to 10% 4 6 − ns tCLPS set-up time clamp asynchronous 0 − − tCLPH hold time clamp asynchronous 0 − − tCLPP clamp pulse − 3 − td data output delay time − 15 24 ns tDH data hold time 12 − − ns CCLP = 10 nF µs Transfer function ILE DC integral linearity error − − ±0.75 LSB DLE DC differential linearity error − − ±0.5 LSB AILE AC integral linearity error note 3 − − ±2 LSB EB effective bits note 3 − 5.7 − bits see Fig.6 − 16 25 ns − 2 − ns Timing DIGITAL OUTPUTS Tdt 3-state delay time Tsto sampling time offset 1996 Aug 20 7 Philips Semiconductors Preliminary specification 6-bit analog-to-digital converter with multiplexer and clamp TDA8706 Notes to the characteristics 1. Low frequency ramp signal (VVI(p-p) = 1.8 V and fi = 15 kHz) combined with a sinewave input voltage (VVI(p-p) = 0.5 V and fi = 4.43 MHz) at the input. 2. Supply voltage ripple rejection (SVRR): variation of the input voltage produces output code 31 for a supply voltage variation of 1 V. ∆V Vi ( 31 ) SVRR = 20 log ----------------------∆V CCA 3. Full-scale sinewave; fi = 4.43 MHz, fCLK = 20 MHz. Table 1 Output coding Table 3 Clamp input A VI(1) BINARY OUTPUTS A CLAMP DIGITAL OUTPUTS VinA (TYP. VALUE) D5 TO D0 0 1 X(1) 2.2 Underflow <2.2 V 000000 1 1 0 2.2 0 2.2 V 000000 Note 1 2.215 V 000001 1. X = don’t care. STEP . ...... . ...... . ...... Table 4 Clamp input B and C B/C CLAMP DIGITAL OUTPUTS VinB/VinC 111111 0 1 X(1) 2.65 111111 1 1 32 2.65 62 3.072 V 111110 63 3.086 V Overflow >3.1 V Note Note 1. With clamping capacitance. 1. X = don’t care. Table 2 Mode selection CEN D0 TO D5 1 high impedance 0 active; binary 1996 Aug 20 8 Philips Semiconductors Preliminary specification 6-bit analog-to-digital converter with multiplexer and clamp handbook, full pagewidth TDA8706 VIH 90% 50% 10% VIL t CLF t CLR t CLH t CLL MCD268 t CLP Fig.3 AC clock characteristics. handbook, full pagewidth CLK tS A B C t CLPS t DH t CLPH CLAMP t CLPP td OUTPUT DATA DATA C DATA A DATA B DATA C MCD269 - 1 Fig.4 AC characteristics select signals; Clamp, Data. 1996 Aug 20 9 Philips Semiconductors Preliminary specification 6-bit analog-to-digital converter with multiplexer and clamp handbook, full pagewidth TDA8706 – (B –Y) (C input) digital outputs = 100000 digital outputs = 100000 – (R –Y) (B input) Y (A input) digital outputs = 000000 1 CLAMP input 0 MCD270 Fig.5 AC characteristics select signals; Clamp, Data. Table 5 Clamp characteristic related to TV signals PARAMETER MIN. TYP. MAX. UNIT Clamping time per line (signal active) 2.2 3.0 3.3 µs Input signals clamped to correct level after − 3 10 lines 1996 Aug 20 10 Philips Semiconductors Preliminary specification 6-bit analog-to-digital converter with multiplexer and clamp TDA8706 handbook, full pagewidth reference level (1.3 V) CE input 2.4 V data outputs 0.4 V t dZH t dZL t dHZ t dLZ Fig.6 Timing diagram of 3-state delay. 1996 Aug 20 11 MGD690 Philips Semiconductors Preliminary specification 6-bit analog-to-digital converter with multiplexer and clamp TDA8706 APPLICATION INFORMATION Additional application information will be supplied upon request (please quote reference number FTV/9112). handbook, full pagewidth 1 20 2 19 3 18 4 17 22 nF 22 nF INC 16 5 TDA8706 INB INA C C B C A C 6 15 7 14 8 13 9 12 10 11 clock signal C MGA230 (1) ‘C’ capacitors must be determined on the output capacitance of the circuits driving A, B and C or CLK pins. (2) VRB and VRT are decoupling pins for the internal reference ladder. Do not draw current from these pins in order to achieve good linearity. (3) Analog and digital supplies should be separated and decoupled. Fig.7 Application diagram. 1996 Aug 20 12 Philips Semiconductors Preliminary specification 6-bit analog-to-digital converter with multiplexer and clamp TDA8706 PACKAGE OUTLINES DIP20: plastic dual in-line package; 20 leads (300 mil) SOT146-1 ME seating plane D A2 A A1 L c e Z b1 w M (e 1) b MH 11 20 pin 1 index E 1 10 0 5 10 mm scale DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT A max. A1 min. A2 max. b b1 c mm 4.2 0.51 3.2 1.73 1.30 0.53 0.38 0.36 0.23 26.92 26.54 inches 0.17 0.020 0.13 0.068 0.051 0.021 0.015 0.014 0.009 1.060 1.045 D (1) e e1 L ME MH w Z (1) max. 6.40 6.22 2.54 7.62 3.60 3.05 8.25 7.80 10.0 8.3 0.254 2.0 0.25 0.24 0.10 0.30 0.14 0.12 0.32 0.31 0.39 0.33 0.01 0.078 E (1) Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT146-1 1996 Aug 20 REFERENCES IEC JEDEC EIAJ SC603 13 EUROPEAN PROJECTION ISSUE DATE 92-11-17 95-05-24 Philips Semiconductors Preliminary specification 6-bit analog-to-digital converter with multiplexer and clamp TDA8706 SO20: plastic small outline package; 20 leads; body width 7.5 mm SOT163-1 D E A X c HE y v M A Z 11 20 Q A2 A (A 3) A1 pin 1 index θ Lp L 1 10 e bp detail X w M 0 5 10 mm scale DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (1) e HE L Lp Q v w y mm 2.65 0.30 0.10 2.45 2.25 0.25 0.49 0.36 0.32 0.23 13.0 12.6 7.6 7.4 1.27 10.65 10.00 1.4 1.1 0.4 1.1 1.0 0.25 0.25 0.1 0.9 0.4 0.012 0.096 0.004 0.089 0.01 0.019 0.013 0.014 0.009 0.51 0.49 0.30 0.29 0.050 0.42 0.39 0.055 0.043 0.016 0.043 0.039 0.01 0.01 0.004 0.035 0.016 inches 0.10 Z (1) θ Note 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. REFERENCES OUTLINE VERSION IEC JEDEC SOT163-1 075E04 MS-013AC 1996 Aug 20 EIAJ EUROPEAN PROJECTION ISSUE DATE 92-11-17 95-01-24 14 o 8 0o Philips Semiconductors Preliminary specification 6-bit analog-to-digital converter with multiplexer and clamp TDA8706 Several techniques exist for reflowing; for example, thermal conduction by heated belt. Dwell times vary between 50 and 300 seconds depending on heating method. Typical reflow temperatures range from 215 to 250 °C. SOLDERING Introduction There is no soldering method that is ideal for all IC packages. Wave soldering is often preferred when through-hole and surface mounted components are mixed on one printed-circuit board. However, wave soldering is not always suitable for surface mounted ICs, or for printed-circuits with high population densities. In these situations reflow soldering is often used. Preheating is necessary to dry the paste and evaporate the binding agent. Preheating duration: 45 minutes at 45 °C. WAVE SOLDERING This text gives a very brief insight to a complex technology. A more in-depth account of soldering ICs can be found in our “IC Package Databook” (order code 9398 652 90011). Wave soldering techniques can be used for all SO packages if the following conditions are observed: • A double-wave (a turbulent wave with high upward pressure followed by a smooth laminar wave) soldering technique should be used. DIP SOLDERING BY DIPPING OR BY WAVE • The longitudinal axis of the package footprint must be parallel to the solder flow. The maximum permissible temperature of the solder is 260 °C; solder at this temperature must not be in contact with the joint for more than 5 seconds. The total contact time of successive solder waves must not exceed 5 seconds. • The package footprint must incorporate solder thieves at the downstream end. During placement and before soldering, the package must be fixed with a droplet of adhesive. The adhesive can be applied by screen printing, pin transfer or syringe dispensing. The package can be soldered after the adhesive is cured. The device may be mounted up to the seating plane, but the temperature of the plastic body must not exceed the specified maximum storage temperature (Tstg max). If the printed-circuit board has been pre-heated, forced cooling may be necessary immediately after soldering to keep the temperature within the permissible limit. Maximum permissible solder temperature is 260 °C, and maximum duration of package immersion in solder is 10 seconds, if cooled to less than 150 °C within 6 seconds. Typical dwell time is 4 seconds at 250 °C. REPAIRING SOLDERED JOINTS A mildly-activated flux will eliminate the need for removal of corrosive residues in most applications. Apply a low voltage soldering iron (less than 24 V) to the lead(s) of the package, below the seating plane or not more than 2 mm above it. If the temperature of the soldering iron bit is less than 300 °C it may remain in contact for up to 10 seconds. If the bit temperature is between 300 and 400 °C, contact may be up to 5 seconds. REPAIRING SOLDERED JOINTS Fix the component by first soldering two diagonallyopposite end leads. Use only a low voltage soldering iron (less than 24 V) applied to the flat part of the lead. Contact time must be limited to 10 seconds at up to 300 °C. When using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 °C. SO REFLOW SOLDERING Reflow soldering techniques are suitable for all SO packages. Reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. 1996 Aug 20 15 Philips Semiconductors Preliminary specification 6-bit analog-to-digital converter with multiplexer and clamp TDA8706 DEFINITIONS Data sheet status Objective specification This data sheet contains target or goal specifications for product development. Preliminary specification This data sheet contains preliminary data; supplementary data may be published later. Product specification This data sheet contains final product specifications. Limiting values Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Where application information is given, it is advisory and does not form part of the specification. LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale. 1996 Aug 20 16