PDI1284P11 3.3 V parallel interface transceiver/buffer Rev. 03 — 25 August 2008 Product data sheet 1. General description The PDI1284P11 parallel interface chip is designed to provide an asynchronous, 8-bit, bidirectional, parallel interface for personal computers. The PDI1284P11 includes all 19 signal lines defined by the IEEE 1284 interface specification for Byte, Nibble, EPP, and ECP modes. The PDI1284P11 is designed for hosts or peripherals operating at 3.3 V to interface 3.3 V or 5.0 V devices. The eight transceiver pairs (A/B 1 to 8) allow data transmission from the A-bus to the B-bus, or from the B-bus to the A-bus, depending on the state of the direction pin DIR. The B-bus and the Y9 to Y13 lines have either totem pole or resistor pull-up outputs, depending on the state of the high drive enable pin HD. The A-bus has only totem pole style outputs. All inputs are TTL compatible with at least 400 mV of input hysteresis at VCC = 3.3 V. 2. Features n n n n n n n n n n n n n n Asynchronous operation 8-bit transceivers Six additional buffer/driver lines peripheral to cable Five additional control lines from cable 5 V tolerant ESD protection: u HBM JESD22-A114E exceeds 2000 V u MM JESD22-A115-A exceeds 200 V Latch-up current protection exceeds 500 mA per JEDEC Std 19 Input hysteresis Low-noise operation IEEE 1284 compliant level 1 and 2 Overvoltage protection on B/Y side for off-state A side 3-state option B side active or resistive pull-up option Cable side supply voltage for 5 V or 3 V operation PDI1284P11 NXP Semiconductors 3.3 V parallel interface transceiver/buffer 3. Ordering information Table 1. Ordering information Type number Package Temperature range Name Description Version PDI1284P11DL 0 °C to 70 °C SSOP48 plastic shrink small outline package; 48 leads; body width 7.5 mm SOT370-1 PDI1284P11DGG 0 °C to 70 °C TSSOP48 plastic thin shrink small outline package; 48 leads; body width 6.1 mm SOT362-1 PDI1284P11_3 Product data sheet © NXP B.V. 2008. All rights reserved. Rev. 03 — 25 August 2008 2 of 16 PDI1284P11 NXP Semiconductors 3.3 V parallel interface transceiver/buffer 4. Functional diagram HD HD DIR CNTL OEA HD A9 Y9 HD A10 Y10 HD A11 Y11 HD A12 Y12 HD A13 Y13 HD A1 B1 CNTL HD A2 B2 CNTL HD A3 B3 CNTL HD A4 B4 CNTL HD A5 B5 CNTL HD A6 B6 CNTL HD A7 B7 CNTL HD A8 B8 CNTL PLHI HD PLHO A14 C14 A15 C15 A16 C16 A17 C17 HLHO HLHI 001aai290 Fig 1. Logic symbol PDI1284P11_3 Product data sheet © NXP B.V. 2008. All rights reserved. Rev. 03 — 25 August 2008 3 of 16 PDI1284P11 NXP Semiconductors 3.3 V parallel interface transceiver/buffer 5. Pinning information 5.1 Pinning HD 1 48 DIR A9 2 47 Y9 A10 3 46 Y10 A11 4 45 Y11 A12 5 44 Y12 A13 6 43 Y13 VCC 7 A1 8 42 VCC(B) 41 B1 A2 9 40 B2 GND 10 39 GND A3 11 38 B3 A4 12 37 B4 PDI1284P11 A5 13 36 B5 A6 14 35 B6 GND 15 34 OEA A7 16 33 B7 A8 17 32 B8 VCC 18 31 VCC(B) 30 PLHO PLHI 19 A14 20 29 C14 A15 21 28 C15 A16 22 27 C16 A17 23 26 C17 HLHO 24 25 HLHI 001aai291 Fig 2. Pin configuration 5.2 Pin description Table 2. Pin description Symbol Pin Description HD 1 high drive enable/disable input A1 to A8 8, 9, 11, 12, 13, 14, 16, 17 data input/output B1 to B8 41, 40, 38, 37, 36, 35, 33, 32 IEEE 1284 standard output/input[1] A9 to A13 2, 3, 4, 5, 6 data input Y9 to Y13 47, 46, 45, 44, 43 IEEE 1284 standard output[1] C14 to C17 29, 28, 27, 26 control input (cable)[1] A14 to A17 20, 21, 22, 23 control output (peripheral) VCC 7, 18 supply voltage GND 10, 15, 39 ground (0 V) PLHI 19 peripheral logic high input (peripheral) PDI1284P11_3 Product data sheet © NXP B.V. 2008. All rights reserved. Rev. 03 — 25 August 2008 4 of 16 PDI1284P11 NXP Semiconductors 3.3 V parallel interface transceiver/buffer Table 2. Pin description …continued Symbol Pin Description HLHO 24 host logic high output (cable) HLHI 25 host logic high input (cable) PLHO 30 peripheral logic high output (cable) VCC(B) 31, 42 supply voltage B (cable side 3 V/5 V) OEA 34 A side output enable input (active LOW) DIR 48 direction selection input [1] Pin with pull-up resistor to load cable. 6. Functional description 6.1 Function selection Table 3. Function table[1] DIR OEA HD Input Output Output type X X X C14 to C17 A14 to A17 TP X X X HLHI HLHO TP X X L A9 to A13 Y9 to Y13 RP X X H A9 to A13 Y9 to Y13 TP X X L PLHI PLHO OC X X H PLHI PLHO TP H X L A1 to A8 B1 to B8 RP H X H A1 to A8 B1 to B8 TP L L X B1 to B8 A1 to A8 TP L H X - A1 to A8 Z[2] L H X B1 to B8 - RP[2] [1] An = side driving internal IC; Bn = side driving external cable (bidirectional); Cn = side receiving control signals from external cable; H = HIGH voltage level; L = LOW voltage level; OC = Open Collector; X = don’t care (control signals in); Yn = side driving external cable (unidirectional); Z = high impedance (high-Z) or 3-state; TP = totem pole output; RP = resistive pull-up: 1.4 kΩ (nominal) on B/Y/C cable side and VCC. However, while a B/Y side output is LOW as driven by a LOW signal on the A side, that particular B/Y side resistor is switched off to stop current drain from VCC through it. [2] When DIR = L and OEA = H, the output signal is isolated from the input signal. Signals B1 to B8 maintain a resistive pull-up of 1.4 kΩ on the input for this mode. PDI1284P11_3 Product data sheet © NXP B.V. 2008. All rights reserved. Rev. 03 — 25 August 2008 5 of 16 PDI1284P11 NXP Semiconductors 3.3 V parallel interface transceiver/buffer 7. Limiting values Table 4. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134).[1] Symbol Parameter Conditions Min Max Unit VCC supply voltage pins VCC −0.5 +4.6 V VCC(B) supply voltage B pins VCC(B); cable side 3 V/5 V −0.5 +6.5 V IIK input clamping current VI < 0 V - ±20 mA IOK output clamping current VO < 0 V - ±50 mA −0.5 +5.5 V VI VO input voltage [2] output voltage [2] B/Y side A side Vtrt transient voltage ICC supply current IGND ground current IO output current Tstg storage temperature total power dissipation Ptot B/Y side; 40 ns transient [3] output HIGH or LOW Tamb = 0 °C to +70 °C [4] −0.5 +5.5 V −0.5 VCC + 0.5 V −2 +7 V - 200 mA −200 - mA - ±50 mA −60 +150 °C - 500 mW [1] The performance capability of a high-performance integrated circuit in conjunction with its thermal environment can create junction temperatures which are detrimental to reliability. [2] The input and output voltage ratings may be exceeded if the input and output current ratings are observed. [3] Vtrt guarantees only that the PDI1284P11 will not be damaged by reflections in application so long as the voltage levels remain in the specified range. [4] Above 60 °C the value of Ptot derates linearly with 5.5 mW/K. 8. Recommended operating conditions Table 5. Operating conditions Symbol Parameter Conditions Min Max Unit VCC supply voltage pins VCC 3.0 3.6 V VCC(B) supply voltage B pins VCC(B); cable side 3 V/5 V 3.0 5.5 V VIH HIGH-level input voltage 2.0 - V VIL LOW-level input voltage - 0.8 V VO output voltage pins Bn, Yn −0.5 +5.5 V pins An 0 VCC V IOH HIGH-level output current pins Bn, Yn - −14 mA IOL LOW-level output current pins Bn, Yn - 14 mA Tamb ambient temperature free-air 0 70 °C PDI1284P11_3 Product data sheet © NXP B.V. 2008. All rights reserved. Rev. 03 — 25 August 2008 6 of 16 PDI1284P11 NXP Semiconductors 3.3 V parallel interface transceiver/buffer 9. Static characteristics Table 6. Static characteristics Tamb = 0 °C to 70 °C; ground = 0 V; unless specified otherwise. Symbol Parameter Conditions Min Typ Max Unit An, Bn, Cn and PLHI inputs; VCC = 3.0 V to 3.6 V - - 0.8 V VIL LOW-level input voltage VIH HIGH-level input An, Bn, PLHI inputs; VCC = 3.0 V to 3.6 V voltage Cn inputs; VCC = 3.0 V to 3.6 V HLHI input; VCC = 3.0 V HLHI input; VCC = 3.6 V hysteresis voltage VH LOW-level output voltage VOL VOH HIGH-level output voltage supply current ICC 1.55 V - V 2.3 - - V 2.6 - - V An, Bn inputs; VCC = 3.3 V; VIL = 0.8 V; VIH = 2.0 V 0.4 0.47 - V Cn inputs; VCC = 3.3 V [1] 0.8 0.47 - V pins An, HLHO; IOL = 50 µA; VCC = 3.0 V - - 0.2 V pins An, HLHO; IOL = 4 mA; VCC = 3.0 V - - 0.4 V pins Bn, Yn; IOL = 14 mA; VCC = 3.0 V - - 0.77 V pin PLHO; IOL = 500 µA; VCC = 3.0 V - - 0.8 V pins An, HLHO; IOH = −500 µA; VCC = 3.0 V 2.8 - - V pins An, HLHO; IOH = −4 mA; VCC = 3.0 V 2.4 - - V pins Bn, Yn; IOH = −14 mA; VCC = 3.0 V 2.23 - - V pin PLHO; IOH = 500 µA; VCC = 3.15 V 3.1 - - V - 5 - µA - 0.1 100 µA - 10 15 mA VI = 0 V or VCC; IO = 0 A pins VCC(B); VCC = 3.6 V; VI = 0 V or VCC; pins Cn = 0 V [1] [2] pin DIR = 3.6 V; VCC(B) = 3.6 V power-off leakage current - [1] pins VCC and VCC(B); VCC = 3.6 V; VCC(B) = 3.6 V to 5.5 V; VI = 0 V or VCC; pins Bn = VCC(B); pins Cn = VCC(B) or floating IOFF 2.0 pin DIR = 3.6 V; VCC(B) = 5.5 V - 16 20 mA pin DIR = 0 V; VCC(B) = 3.6 V; pins Bn = 0 V - 30 40 mA pin DIR = 0 V; VCC(B) = 5.5 V; pins Bn = 0 V - 47 60 mA pins Bn, Cn, Yn; VO = 5.5 V; VCC = 0 V VCC(B) = 0 V - - ±100 µA VCC(B) = 4.5 V - - ±100 µA - - ±1 µA II input leakage current VI = 0 V to VCC [3] IOZ OFF-state output current 3-state; VO = VCC or 0 V [3] - - ±20 µA Ro output resistance VCC = 3.3 V; see Figure 9 [1] 35 45 55 Ω [1] 1.15 1.4 1.65 kΩ pull-up resistance RPU [1] VO = 1.65 V ± 0.1 V; B/Y side B/Y side; VCC = 3.3 V; output in high-Z with resistive pull-up Typical values at Tamb = 25 °C. [2] Includes extra ICC(B) current from pull-up resistors, i.e. ICC(B) = (total number of LOW inputs on B and C sides) × (VCC(B) / RPU). [3] The pull-up resistor on the B side outputs makes it impossible to test IOZ on the B side. This applies to the input current on the C side inputs as well. PDI1284P11_3 Product data sheet © NXP B.V. 2008. All rights reserved. Rev. 03 — 25 August 2008 7 of 16 PDI1284P11 NXP Semiconductors 3.3 V parallel interface transceiver/buffer 10. Dynamic characteristics Table 7. Dynamic characteristics VCC = 3.0 V to 3.6 V; ground = 0 V; CL = 50 pF; RL = 500 Ω; Tamb = 0 °C to 70 °C; unless specified otherwise. Symbol Parameter Conditions Min Typ[2] Max Unit tPLH LOW to HIGH propagation delay An to Bn or Yn; see Figure 3 and 8 0 12.5 20 ns tPHL HIGH to LOW propagation delay An to Bn or Yn; see Figure 3 and 8 0 13.9 23 ns tpd propagation delay see Figure 4 and 8 Bn to An 0 - 12 ns Cn to An - - 15 ns PLHI to PLHO - - 20 ns HLHI to HLHO - - 15 ns [1] SR slew rate Bn/Yn; RL = 62 Ω; see Figure 5 and 8 0.05 0.2 0.4 V/ns tdis disable time HD to Yn or Bn; see Figure 6 and 8 [3] - - 20 ns HD to PLHO; see Figure 6 and 7 [3] - - 20 ns RL = 250 Ω; see Figure 6 and 7 [3] DIR to Bn; TP load on B/Y side - - 50 ns DIR to An - - 15 ns OEA to An enable time ten - - 6 ns HD to Yn or Bn; see Figure 6 and 7 [4] - - 20 ns HD to PLHO; see Figure 6 and 7 [4] - - 20 ns RL = 250 Ω; see Figure 6 and 7 [4] DIR to Bn; TP load on B/Y side - - 30 ns DIR to An - - 50 ns OEA to An ∆tPD [1] propagation delay difference tPZH − tPHZ; HD to output - - 12 ns - - 10 ns tpd is the same as tPLH and tPHL. [2] Value at Tamb = 25 °C and VCC = 3.3 V. [3] tdis is the same as tPHZ and tPLZ. [4] ten is the same as tPZH and tPZL. PDI1284P11_3 Product data sheet © NXP B.V. 2008. All rights reserved. Rev. 03 — 25 August 2008 8 of 16 PDI1284P11 NXP Semiconductors 3.3 V parallel interface transceiver/buffer 11. Waveforms 2.4 V input 1.4 V 1.4 V 0.4 V tPLH tPHL VO output VO − 1.4 V 1.4 V 001aai293 Fig 3. Input An to output Bn or Yn propagation delays VI input VM GND tPHL tPLH VOH output VM VOL 001aai292 VM = 1.5 V. VCC never goes below 3.0 V. VOL and VOH are the typical voltage output levels that occur with the output load. Fig 4. Input Bn, Cn to output An propagation delays 2.4 V input 0.4 V 2.4 V 0.9 V output 1.9 V 0.4 V t1 t2 t1 t2 001aai295 Measurement data is given in Table 8. SR is measured for both a LOW-to-HIGH and a HIGH-to-LOW transition. Fig 5. Table 8. tr 3 ns Slew rate on B/Y side Slew rate measurements tf 3 ns tW 150 ns < tW < 10 µs RL VO transition (see Figure 8) 62 Ω Rising Falling from VO = 0.4 V to VO = 0.9 V from VO = 2.4 V to VO = 1.9 V PDI1284P11_3 Product data sheet © NXP B.V. 2008. All rights reserved. Rev. 03 — 25 August 2008 9 of 16 PDI1284P11 NXP Semiconductors 3.3 V parallel interface transceiver/buffer DIR to A VM DIR to B VM VI HD to B VM GND tPLZ tPZL VCC output LOW-to-OFF OFF-to-LOW VM VX VOL tPHZ tPZH VOH VY output HIGH-to-OFF OFF-to-HIGH VM GND outputs enabled outputs enabled outputs disabled 001aai294 Test circuit is shown in Figure 7. Measurement points are given in Table 9. VOL and VOH are the typical voltage output levels that occur with the output load. Fig 6. Enable and disable times VEXT VCC VI RL VO G DUT RT CL RL mna616 Test conditions are given in Table 9. Fig 7. Test circuit for measuring enable and disable times Table 9. Test data for test circuit measuring enable disable times Bn to An Parameter VCC Input Output VEXT VI VM VM VX VY tPZH, tPHZ tPZL, tPLZ DIR to Bn, An; OEA to An < 2.7 V VCC 1.5 V 1.5 V VOL ± 0.3 V VOH − 0.3 V GND 2VCC 2.7 V to 3.6 V 2.7 V 1.5 V 1.5 V VOL ± 0.3 V VOH − 0.3 V GND 2VCC HD to Yn or Bn; HD to PHLO < 2.7 V VCC 1.5 V 1.5 V - VOH − 0.3 V open - 2.7 V to 3.6 V 2.7 V 1.5 V 1.5 V - VOH − 0.3 V open - PDI1284P11_3 Product data sheet © NXP B.V. 2008. All rights reserved. Rev. 03 — 25 August 2008 10 of 16 PDI1284P11 NXP Semiconductors 3.3 V parallel interface transceiver/buffer VI tW 90 % 90 % negative pulse VM 0V 10 % tf tr tr tf VI 90 % positive pulse 0V VM 10 % 90 % VM VM 10 % 10 % tW 001aai298 a. Input pulse definition VCC CL G VI VO VEXT DUT GND RT RL 001aai296 b. Test circuit CL = load capacitance includes jig and probe capacitance. RL = load resistance. RT = termination resistance should be equal to the output impedance of the pulse generator. Test conditions for propagation delays are given in Table 10, test conditions for slew rate are given in Table 8 Fig 8. Table 10. Output Test circuit for An, Bn and Yn outputs; slew rate B/Y side Test conditions for An, Bn and Yn outputs VI VM Repetition rate tW tr tf Switch position tPLH, tPZH tPHL, tPHZ An 3.0 V 1.5 V 1 MHz 500 ns 3 ns 3 ns GND GND Bn, Yn 3.0 V 1.5 V 1 MHz 500 ns 3 ns 3 ns GND VEXT = 2.8 V VCC IO DUT VCC / 2 001aai299 IO is measured by forcing 0.5VCC on the output. The output impedance can then be calculated as Ro = 0.5VCC / |IO|. Fig 9. Output impedance PDI1284P11_3 Product data sheet © NXP B.V. 2008. All rights reserved. Rev. 03 — 25 August 2008 11 of 16 PDI1284P11 NXP Semiconductors 3.3 V parallel interface transceiver/buffer 12. Package outline SSOP48: plastic shrink small outline package; 48 leads; body width 7.5 mm SOT370-1 D E A X c y HE v M A Z 25 48 Q A2 A1 A (A 3) θ pin 1 index Lp L 24 1 detail X w M bp e 0 5 10 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (1) e HE L Lp Q v w y Z (1) θ mm 2.8 0.4 0.2 2.35 2.20 0.25 0.3 0.2 0.22 0.13 16.00 15.75 7.6 7.4 0.635 10.4 10.1 1.4 1.0 0.6 1.2 1.0 0.25 0.18 0.1 0.85 0.40 8 o 0 o Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT370-1 REFERENCES IEC JEDEC JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-19 MO-118 Fig 10. Package outline SOT370-1 (SSOP48) PDI1284P11_3 Product data sheet © NXP B.V. 2008. All rights reserved. Rev. 03 — 25 August 2008 12 of 16 PDI1284P11 NXP Semiconductors 3.3 V parallel interface transceiver/buffer TSSOP48: plastic thin shrink small outline package; 48 leads; body width 6.1 mm SOT362-1 E D A X c HE y v M A Z 48 25 Q A2 (A 3) A1 pin 1 index A θ Lp L 1 detail X 24 w M bp e 2.5 0 5 mm scale DIMENSIONS (mm are the original dimensions). UNIT A max. A1 A2 A3 bp c D (1) E (2) e HE L Lp Q v w y Z θ mm 1.2 0.15 0.05 1.05 0.85 0.25 0.28 0.17 0.2 0.1 12.6 12.4 6.2 6.0 0.5 8.3 7.9 1 0.8 0.4 0.50 0.35 0.25 0.08 0.1 0.8 0.4 8 o 0 o Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT362-1 REFERENCES IEC JEDEC JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-19 MO-153 Fig 11. Package outline SOT362-1 (TSSOP48) PDI1284P11_3 Product data sheet © NXP B.V. 2008. All rights reserved. Rev. 03 — 25 August 2008 13 of 16 PDI1284P11 NXP Semiconductors 3.3 V parallel interface transceiver/buffer 13. Abbreviations Table 11. Abbreviations Acronym Description CDM Charged Device Model CMOS Complementary Metal-Oxide Semiconductor DUT Device Under Test ECP Extended Capability Port EPP Enhanced Parallel Port ESD ElectroStatic Discharge HBM Human Body Model LSTTL Low-power Schottky Transistor-Transistor Logic MM Machine Model TTL Transistor-Transistor Logic 14. Revision history Table 12. Revision history Document ID Release date Data sheet status Change notice Supersedes PDI1284P11_3 20080825 Product data sheet - PDI1284P11_2 Modifications: • The format of this data sheet has been redesigned to comply with the new identity guidelines of NXP Semiconductors. • • • • Legal texts have been adapted to the new company name where appropriate. Quick reference table removed. Table 7, tPHL: Maximum value of 20 ns replaced by 23 ns. Table 11: Abbreviations list added. PDI1284P11_2 19990917 Product specification - PDI1284P11_1 PDI1284P11_1 19970915 Product specification - - PDI1284P11_3 Product data sheet © NXP B.V. 2008. All rights reserved. Rev. 03 — 25 August 2008 14 of 16 PDI1284P11 NXP Semiconductors 3.3 V parallel interface transceiver/buffer 15. Legal information 15.1 Data sheet status Document status[1][2] Product status[3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification. [1] Please consult the most recently issued document before initiating or completing a design. [2] The term ‘short data sheet’ is explained in section “Definitions”. [3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com. 15.2 Definitions Draft — The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet — A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. 15.3 Disclaimers General — Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use — NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk. Applications — Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) may cause permanent damage to the device. Limiting values are stress ratings only and operation of the device at these or any other conditions above those given in the Characteristics sections of this document is not implied. Exposure to limiting values for extended periods may affect device reliability. Terms and conditions of sale — NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, including those pertaining to warranty, intellectual property rights infringement and limitation of liability, unless explicitly otherwise agreed to in writing by NXP Semiconductors. In case of any inconsistency or conflict between information in this document and such terms and conditions, the latter will prevail. No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. 15.4 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. 16. Contact information For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: [email protected] PDI1284P11_3 Product data sheet © NXP B.V. 2008. All rights reserved. Rev. 03 — 25 August 2008 15 of 16 PDI1284P11 NXP Semiconductors 3.3 V parallel interface transceiver/buffer 17. Contents 1 2 3 4 5 5.1 5.2 6 6.1 7 8 9 10 11 12 13 14 15 15.1 15.2 15.3 15.4 16 17 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 3 Pinning information . . . . . . . . . . . . . . . . . . . . . . 4 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4 Functional description . . . . . . . . . . . . . . . . . . . 5 Function selection. . . . . . . . . . . . . . . . . . . . . . . 5 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 6 Recommended operating conditions. . . . . . . . 6 Static characteristics. . . . . . . . . . . . . . . . . . . . . 7 Dynamic characteristics . . . . . . . . . . . . . . . . . . 8 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 12 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Revision history . . . . . . . . . . . . . . . . . . . . . . . . 14 Legal information. . . . . . . . . . . . . . . . . . . . . . . 15 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 15 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Contact information. . . . . . . . . . . . . . . . . . . . . 15 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. © NXP B.V. 2008. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: [email protected] Date of release: 25 August 2008 Document identifier: PDI1284P11_3