CY7C1061DV33 16-Mbit (1 M × 16) Static RAM 16-Mbit (1 M × 16) Static RAM Features Functional Description ■ High speed ❐ tAA = 10 ns The CY7C1061DV33 is a high performance CMOS Static RAM organized as 1,048,576 words by 16 bits. ■ Low active power ❐ ICC = 175 mA at 100 MHz ■ Low CMOS standby power ❐ ISB2 = 25 mA ■ Operating voltages of 3.3 ± 0.3 V To write to the device, take Chip Enables (CE1 LOW and CE2 HIGH) and Write Enable (WE) input LOW. If Byte Low Enable (BLE) is LOW, then data from I/O pins (I/O0 through I/O7), is written into the location specified on the address pins (A0 through A19). If Byte High Enable (BHE) is LOW, then data from I/O pins (I/O8 through I/O15) is written into the location specified on the address pins (A0 through A19). ■ 2.0 V data retention ■ Automatic power down when deselected ■ TTL compatible inputs and outputs ■ Easy memory expansion with CE1 and CE2 features ■ Available in Pb-free 54-pin TSOP II and 48-ball VFBGA packages ■ Offered in single CE and dual CE options To read from the device, take Chip Enables (CE1 LOW and CE2 HIGH) and Output Enable (OE) LOW while forcing the Write Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW, then data from the memory location specified by the address pins appears on I/O0 to I/O7. If Byte High Enable (BHE) is LOW, then data from memory appears on I/O8 to I/O15. See Truth Table on page 12 for a complete description of Read and Write modes. The input or output pins (I/O0 through I/O15) are placed in a high impedance state when the device is deselected (CE1 HIGH/CE2 LOW), the outputs are disabled (OE HIGH), the BHE and BLE are disabled (BHE, BLE HIGH), or during a write operation (CE1 LOW, CE2 HIGH, and WE LOW). The CY7C1061DV33 is available in a 54-pin TSOP II package with center power and ground (revolutionary) pinout, and 48-ball VFBGA packages. For a complete list of related documentation, click here. Logic Block Diagram SENSE AMPS A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 ROW DECODER INPUT BUFFER 1M x 16 ARRAY I/O0 – I/O7 I/O8 – I/O15 A10 A11 A 12 A 13 A 14 A15 A16 A17 A18 A19 COLUMN DECODER BHE WE OE BLE Cypress Semiconductor Corporation Document Number: 38-05476 Rev. *J • 198 Champion Court • CE2 CE1 San Jose, CA 95134-1709 • 408-943-2600 Revised October 27, 2015 CY7C1061DV33 Contents Selection Guide ................................................................ 3 Pin Configurations ........................................................... 3 Maximum Ratings ............................................................. 5 Operating Range ............................................................... 5 DC Electrical Characteristics .......................................... 5 Capacitance ...................................................................... 6 Thermal Resistance .......................................................... 6 AC Test Loads and Waveforms ....................................... 6 Data Retention Characteristics ....................................... 7 Over the Operating Range ............................................... 7 Data Retention Waveform ................................................ 7 AC Switching Characteristics ......................................... 8 Switching Waveforms ...................................................... 9 Truth Table ...................................................................... 12 Truth Table ...................................................................... 12 Document Number: 38-05476 Rev. *J Ordering Information ...................................................... 13 Ordering Code Definitions ......................................... 13 Package Diagrams .......................................................... 14 Acronyms ........................................................................ 16 Document Conventions ................................................. 16 Units of Measure ....................................................... 16 Document History Page ................................................. 17 Sales, Solutions, and Legal Information ...................... 19 Worldwide Sales and Design Support ....................... 19 Products .................................................................... 19 PSoC® Solutions ...................................................... 19 Cypress Developer Community ................................. 19 Technical Support ..................................................... 19 Page 2 of 19 CY7C1061DV33 Selection Guide Description -10 Unit Maximum access time 10 ns Maximum operating current 175 mA Maximum CMOS standby current 25 mA Pin Configurations Figure 1. 48-ball VFBGA (8 × 9.5 × 1 mm) Dual Chip Enable (-BVXI) pinout (Top View) [1, 2] 1 2 3 4 5 6 BLE OE A0 A1 A2 CE2 A I/O8 BHE A3 A4 CE1 I/O0 B I/O9 I/O10 A5 A6 I/O1 I/O2 C VSS I/O11 A17 A7 I/O3 VCC D VCC I/O12 NC A16 I/O4 VSS E I/O14 I/O13 A14 A15 I/O5 I/O6 F I/O15 NC A12 A13 WE I/O7 G A18 A8 A9 A10 A11 A19 H Figure 2. 48-ball VFBGA (8 × 9.5 × 1 mm) Dual Chip Enable (-BVJXI) pinout (Top View) [1, 2] 1 2 3 4 5 6 BLE OE A0 A1 A2 CE2 A I/O8 BHE A3 A4 CE1 I/O0 B I/O9 I/O10 A5 A6 I/O1 I/O2 C VSS I/O11 A17 A7 VCC D VCC NC A16 I/O4 VSS E I/O14 I/O13 A14 A15 I/O5 I/O6 F I/O12 I/O3 I/O15 A19 A12 A13 WE I/O7 G A18 A8 A9 A10 A11 NC H Notes 1. NC pins are not connected on the die. 2. In BVXI package, ball H6 is MSB address A19 and ball G2 is NC; in BVJXI package, ball H6 is NC and ball G2 is MSB address A19. Document Number: 38-05476 Rev. *J Page 3 of 19 CY7C1061DV33 Pin Configurations (continued) Figure 3. 48-ball VFBGA (8 × 9.5 × 1 mm) Single Chip Enable (-BV1XI) pinout (Top View) [3, 4] 1 2 3 4 5 6 BLE OE A0 A1 A2 NC A I/O8 BHE A3 A4 CE I/O0 B I/O9 I/O10 A5 A6 I/O1 I/O2 C VSS I/O11 A17 A7 VCC D VCC NC A16 I/O4 VSS E I/O14 I/O13 A14 A15 I/O5 I/O6 F I/O12 I/O3 I/O15 A19 A12 A13 WE I/O7 G A18 A8 A9 A10 A11 NC H Figure 4. 54-pin TSOP II (22.4 × 11.84 × 1.0 mm) pinout (Top View) [3] I/O12 VCC I/O13 I/O14 VSS I/O15 A4 A3 A2 A1 A0 BHE CE1 VCC WE CE2 A19 A18 A17 A16 A15 I/O0 VCC I/O1 I/O2 VSS I/O3 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 45 44 I/O11 VSS I/O10 I/O9 VCC I/O8 A5 A6 A7 A8 A9 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 NC OE VSS NC BLE A10 A11 A12 A13 A14 I/O7 VSS I/O6 I/O5 VCC I/O4 54 53 52 51 50 49 48 47 46 Notes 3. NC pins are not connected on the die. 4. In BV1XI package, ball A6 is NC, ball H6 is NC and ball G2 is MSB address A19. BV1XI package has only single Chip Enable (CE). Document Number: 38-05476 Rev. *J Page 4 of 19 CY7C1061DV33 DC Input Voltage [5] ............................ –0.5 V to VCC + 0.5 V Maximum Ratings Current into Outputs (LOW) ........................................ 20 mA Exceeding maximum ratings may impair the useful life of the device. These user guidelines are not tested. Static Discharge Voltage (MIL-STD-883, Method 3015) .................................. >2001 V Storage Temperature ............................... –65 C to +150 C Latch Up Current .................................................... >200 mA Ambient Temperature with Power Applied .................................. –55 C to +125 C Operating Range Supply Voltage on VCC relative to GND [5] ...........................–0.5 V to +4.6 V DC Voltage Applied to Outputs in High Z State [5] ................................ –0.5 V to VCC + 0.5 V Range Ambient Temperature VCC Industrial –40 C to +85 C 3.3 V 0.3 V DC Electrical Characteristics Over the Operating Range Parameter Description Test Conditions VOH Output HIGH voltage VCC = Min, IOH = –4.0 mA -10 Min Max 2.4 – Unit V VOL Output LOW voltage VCC = Min, IOL = 8.0 mA – 0.4 V VIH Input HIGH voltage – 2.0 VCC + 0.3 V VIL Input LOW voltage [5] – –0.3 0.8 V IIX Input leakage current GND < VI < VCC –1 +1 A IOZ Output leakage current GND < VOUT < VCC, Output disabled –1 +1 A ICC VCC operating supply current VCC = Max, f = fMAX = 1/tRC, IOUT = 0 mA, CMOS levels – 175 mA ISB1 Automatic CE power down current – TTL inputs Max VCC, CE1 > VIH, CE2 < VIL, VIN > VIH or VIN < VIL, f = fMAX – 30 mA ISB2 Automatic CE power down current – CMOS inputs Max VCC, CE1 > VCC – 0.3 V, CE2 < 0.3 V, VIN > VCC – 0.3 V, or VIN < 0.3 V, f = 0 – 25 mA Note 5. VIL(min) = –2.0 V and VIH(max) = VCC + 2 V for pulse durations of less than 20 ns. Document Number: 38-05476 Rev. *J Page 5 of 19 CY7C1061DV33 Capacitance Parameter [6] Description CIN Input capacitance COUT I/O capacitance Test Conditions 54-pin TSOP II 48-ball VFBGA Unit TA = 25 C, f = 1 MHz, VCC = 3.3 V 6 8 pF 8 10 pF Thermal Resistance Parameter [6] Description JA Thermal resistance (junction to ambient) JC Thermal resistance (junction to case) Test Conditions 54-pin TSOP II 48-ball VFBGA Unit Still air, soldered on a 3 × 4.5 inch, four-layer printed circuit board 76.15 28.37 C/W 14.15 5.79 C/W AC Test Loads and Waveforms Figure 5. AC Test Loads and Waveforms [7] High-Z Characteristics: 3.3 V 50 VTH = 1.5 V Output Z0 = 50 Output 30 pF* Including JIG and Scope (b) All Input Pulses 3.0 V GND R2 351 5 pF* (a) * Capacitive Load Consists of all Components of the Test Environment R1 317 90% 90% 10% Rise Time: > 1 V/ns 10% (c) Fall Time: > 1 V/ns Notes 6. Tested initially and after any design or process changes that may affect these parameters. 7. Valid SRAM operation does not occur until the power supplies have reached the minimum operating VDD (3.0 V). 100 s (tpower) after reaching the minimum operating VDD, normal SRAM operation begins including reduction in VDD to the data retention (VCCDR, 2.0 V) voltage. Document Number: 38-05476 Rev. *J Page 6 of 19 CY7C1061DV33 Data Retention Characteristics Over the Operating Range Parameter Description Conditions Min Max Unit VDR VCC for data retention – 2 – V ICCDR Data retention current VCC = 2 V, CE1 > VCC – 0.2 V, CE2 < 0.2 V, VIN > VCC – 0.2 V or VIN < 0.2 V – 25 mA tCDR [8] Chip deselect to data retention time – 0 – ns tR[9] Operation recovery time – tRC – ns Data Retention Waveform Figure 6. Data Retention Waveform [10] Data Retention Mode VCC 3.0 V tCDR VDR > 2 V 3.0 V tR CE Notes 8. Tested initially and after any design or process changes that may affect these parameters. 9. Full device operation requires linear VCC ramp from VDR to VCC(min.) > 50 s or stable at VCC(min.) > 50 s. 10. For all packages except -BV1XI, CE is the logical combination of CE1 and CE2. When CE1 is LOW and CE2 is HIGH, CE is LOW; when CE1 is HIGH or CE2 is LOW, CE is HIGH. For -BV1XI package, CE refers to CE. Document Number: 38-05476 Rev. *J Page 7 of 19 CY7C1061DV33 AC Switching Characteristics Over the Operating Range Parameter [11] Description -10 Min Max Unit Read Cycle tpower VCC(typical) to the first access [12] 100 – s tRC Read cycle time 10 – ns tAA Address to data valid – 10 ns tOHA Data hold from address change 3 – ns tACE CE1 LOW/CE2 HIGH to data valid – 10 ns tDOE OE LOW to data valid – 5 ns 1 – ns – 5 ns 3 – ns – 5 ns 0 – ns tLZOE OE LOW to low Z [13] [13] tHZOE OE HIGH to high Z tLZCE CE1 LOW/CE2 HIGH to low Z [13] tHZCE tPU CE1 HIGH/CE2 LOW to high Z [13] CE1 LOW/CE2 HIGH to power-up [14] [14] tPD CE1 HIGH/CE2 LOW to power-down – 10 ns tDBE Byte enable to data valid – 5 ns tLZBE Byte enable to low Z 1 – ns Byte disable to high Z – 5 ns tHZBE Write Cycle [15, 16] tWC Write cycle time 10 – ns tSCE CE1 LOW/CE2 HIGH to write end 7 – ns tAW Address setup to write end 7 – ns tHA Address hold from write end 0 – ns tSA Address setup to write start 0 – ns tPWE WE pulse width 7 – ns tSD Data setup to write end 5.5 – ns tHD Data hold from write end 0 – ns tLZWE WE HIGH to low Z [13] 3 – ns tHZWE WE LOW to high Z [13] – 5 ns tBW Byte Enable to End of Write 7 – ns Notes 11. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5 V, and input pulse levels of 0 to 3.0 V. Test conditions for the read cycle use output loading shown in part (a) of Figure 5 on page 6, unless specified otherwise. 12. tPOWER gives the minimum amount of time that the power supply is at typical VCC values until the first memory access is performed. 13. tHZOE, tHZCE, tHZWE, tHZBE, tLZOE, tLZCE, tLZWE, and tLZBE are specified with a load capacitance of 5 pF as in (b) of Figure 5 on page 6. Transition is measured 200 mV from steady state voltage. 14. These parameters are guaranteed by design and are not tested. 15. The internal write time of the memory is defined by the overlap of WE, CE1 = VIL, and CE2 = VIH. Chip enables must be active and WE and byte enables must be LOW to initiate a write, and the transition of any of these signals can terminate. The input data setup and hold timing should be referenced to the edge of the signal that terminates the write. 16. The minimum write cycle time for Write Cycle No. 2 (WE Controlled, OE LOW) is the sum of tHZWE and tSD. Document Number: 38-05476 Rev. *J Page 8 of 19 CY7C1061DV33 Switching Waveforms Figure 7. Read Cycle No. 1 (Address Transition Controlled) [17, 18] tRC RC Address tAA tOHA Data Out Previous Data Valid Data Valid Figure 8. Read Cycle No. 2 (OE Controlled) [18, 19, 20] Address tRC CE tACE OE tHZOE tDOE BHE, BLE tLZOE tHZCE tDBE tLZBE Data Out High Impedance Data Valid tLZCE VCC Supply Current tHZBE High Impedance tPD tPU 50% 50% IICC CC IISB SB Notes 17. The device is continuously selected. OE, CE = VIL, BHE, BLE or both = VIL. 18. WE is HIGH for read cycle. 19. For all packages except -BV1XI, CE is the logical combination of CE1 and CE2. When CE1 is LOW and CE2 is HIGH, CE is LOW; when CE1 is HIGH or CE2 is LOW, CE is HIGH. For -BV1XI package, CE refers to CE. 20. Address valid before or similar to CE transition LOW. Document Number: 38-05476 Rev. *J Page 9 of 19 CY7C1061DV33 Switching Waveforms (continued) Figure 9. Write Cycle No. 1 (CE Controlled) [21, 22, 23] tWC Address tSA CE tSCE tAW tHA tPWE WE tBW BHE, BLE tSD tHD Data I/O Figure 10. Write Cycle No. 2 (WE Controlled, OE LOW) [21, 22, 23, 24] tWC Address tSCE CE tAW tHA tSA tPWE WE tBW BHE, BLE tHZWE tSD tHD Data I/O tLZWE Notes 21. For all packages except -BV1XI, CE is the logical combination of CE1 and CE2. When CE1 is LOW and CE2 is HIGH, CE is LOW; when CE1 is HIGH or CE2 is LOW, CE is HIGH. For -BV1XI package, CE refers to CE. 22. Data I/O is high impedance if OE, BHE, and/or BLE = VIH. 23. If CE goes HIGH simultaneously with WE going HIGH, the output remains in a high-impedance state. 24. The minimum write cycle time is the sum of tHZWE and tSD. Document Number: 38-05476 Rev. *J Page 10 of 19 CY7C1061DV33 Switching Waveforms (continued) Figure 11. Write Cycle No. 3 (BLE or BHE Controlled) [25] tWC Address tSA tBW BHE, BLE tAW tHA tPWE WE tSCE CE tSD tHD Data I/O Note 25. For all packages except -BV1XI, CE is the logical combination of CE1 and CE2. When CE1 is LOW and CE2 is HIGH, CE is LOW; when CE1 is HIGH or CE2 is LOW, CE is HIGH. For -BV1XI package, CE refers to CE. Document Number: 38-05476 Rev. *J Page 11 of 19 CY7C1061DV33 Truth Table For all packages except -BV1XI CE1 CE2 OE WE BLE BHE I/O0–I/O7 I/O8–I/O15 Mode Power H X X X X X High Z High Z Power down Standby (ISB) X L X X X X High Z High Z Power down Standby (ISB) L H L H L L Data out Data out Read all bits Active (ICC) L H L H L H Data out High Z Read lower bits only Active (ICC) L H L H H L High Z Data out Read upper bits only Active (ICC) L H X L L L Data in Data in Write all bits Active (ICC) L H X L L H Data in High Z Write lower bits only Active (ICC) L H X L H L High Z Data in Write upper bits only Active (ICC) L H H H X X High Z High Z Selected, outputs disabled Active (ICC) I/O0–I/O7 Truth Table For -BV1XI package only CE OE WE BLE BHE H X X X X High Z High Z Power down Standby (ISB) L L H L L Data out Data out Read all bits Active (ICC) L L H L H Data out High Z Read lower bits only Active (ICC) L L H H L High Z Data out Read upper bits only Active (ICC) L X L L L Data in Data in Write all bits Active (ICC) L X L L H Data in High Z Write lower bits only Active (ICC) L X L H L High Z Data in Write upper bits only Active (ICC) L H H X X High Z High Z Selected, outputs disabled Active (ICC) Document Number: 38-05476 Rev. *J I/O8–I/O15 Mode Power Page 12 of 19 CY7C1061DV33 Ordering Information Speed (ns) 10 Ordering Code Package Diagram Operating Range Package Type CY7C1061DV33-10ZSXI 51-85160 54-pin TSOP II (22.4 × 11.84 × 1.0 mm) (Pb-free) CY7C1061DV33-10BVXI 51-85178 48-ball VFBGA (8 × 9.5 × 1 mm) (Pb-free) (Dual Chip Enable) CY7C1061DV33-10BVJXI 48-ball VFBGA (8 × 9.5 × 1 mm) (Pb-free) (Dual Chip Enable JEDEC compatible) CY7C1061DV33-10BV1XI 48-ball VFBGA (8 × 9.5 × 1 mm) (Pb-free) (Single Chip Enable) Industrial Ordering Code Definitions CY 7 C 1 06 1 D V33 - 10 XXX X I Temperature Range: I = Industrial Pb-free Package Type: XXX = ZS or BV or BVJ ZS = 54-pin TSOP II BV = 48-ball VFBGA (Dual Chip Enable) BVJ = 48-ball VFBGA (Dual Chip Enable - JEDEC compatible) Speed: 10 ns V33 = Voltage range (3 V to 3.6 V) D = C9, 90 nm Technology Data Width: 1 = × 16-bits Density: 06 = 16-Mbit density Family Code: 1 = Fast Asynchronous SRAM family Technology Code: C = CMOS Marketing Code: 7 = SRAM Company ID: CY = Cypress Document Number: 38-05476 Rev. *J Page 13 of 19 CY7C1061DV33 Package Diagrams Figure 12. 54-pin TSOP II (22.4 × 11.84 × 1.0 mm) Z54-II Package Outline, 51-85160 51-85160 *E Document Number: 38-05476 Rev. *J Page 14 of 19 CY7C1061DV33 Package Diagrams (continued) Figure 13. 48-ball VFBGA (8 × 9.5 × 1.0 mm) BV48B Package Outline, 51-85178 51-85178 *C Document Number: 38-05476 Rev. *J Page 15 of 19 CY7C1061DV33 Acronyms Acronym Document Conventions Description Units of Measure BHE Byte High Enable BLE Byte Low Enable °C degree Celsius CE Chip Enable MHz megahertz CMOS Complementary Metal Oxide Semiconductor A microampere I/O Input/Output s microsecond OE Output Enable mA milliampere SRAM Static Random Access Memory mm millimeter TSOP Thin Small Outline Package ns nanosecond TTL Transistor-Transistor Logic ohm VFBGA Very Fine-Pitch Ball Grid Array % percent WE Write Enable pF picofarad V volt W watt Document Number: 38-05476 Rev. *J Symbol Unit of Measure Page 16 of 19 CY7C1061DV33 Document History Page Document Title: CY7C1061DV33, 16-Mbit (1 M × 16) Static RAM Document Number: 38-05476 Rev. ECN No. Orig. of Change Submission Date ** 201560 SWI See ECN Advance data sheet for C9 IPP *A 233748 RKF See ECN Updated AC and DC parameters as per EROS (Specification Number 01-02165). Updated Ordering Information (Added Pb-free devices). *B 469420 NXR See ECN Changed status from Advance Information to Preliminary. Updated Document Title (Corrected typo). Removed 8 ns and 12 ns speed bins related information in all instances across the document. Removed Commercial Temperature Range related information in all instances across the document. Updated Selection Guide: Changed value of “Maximum Operating Current” corresponding to 10 ns speed bin from 176 mA to 125 mA. Changed value of “Maximum CMOS Standby Current” corresponding to 10 ns speed bin from 40 mA to 25 mA. Updated Pin Configurations: Changed ball 2G of FBGA and pin 40 of TSOP II from DNU to NC. Updated Maximum Ratings: Included details corresponding to “Static Discharge Voltage” and “Latch-Up Current”. Updated DC Electrical Characteristics: Updated Note 5 (Specified the Overshoot specification). Changed maximum value of ICC parameter corresponding to 10 ns speed bin from 176 mA to 125 mA Changed maximum value of ISB1 parameter corresponding to 10 ns speed bin from 70 mA to 30 mA. Changed maximum value of ISB2 parameter corresponding to 10 ns speed bin from 40 mA to 25 mA. Updated Ordering Information. *C 499604 NXR See ECN Updated Pin Configurations: Added Note 1 and referred the same note in Pin Configurations. Updated DC Electrical Characteristics: Updated details in “Test Condition” column corresponding to ICC parameter. Updated Package Diagrams: Updated figure corresponding to 48-ball FBGA Package (Removed spec 51-85150 *D and added spec 51-85178 **). *D 1462583 VKN / AESA See ECN Changed status from Preliminary to Final. Updated Selection Guide: Changed value of “Maximum Operating Current” from 125 mA to 175 mA corresponding to 10 ns speed bin. Updated DC Electrical Characteristics: Changed maximum value of ICC parameter from 125 mA to 175 mA corresponding to 10 ns speed bin. Updated Thermal Resistance: Replaced TBD with values for all packages. *E 2704415 VKN / PYRS 05/11/09 Included 48-ball FBGA Dual Chip Enable - JEDEC compatible package related information in all instances across the document. Updated Pin Configurations: Added Note 2 and referred the same note in Figure 1 and Figure 2. *F 3109102 AJU 12/13/2010 Document Number: 38-05476 Rev. *J Description of Change Added Ordering Code Definitions under Ordering Information. Updated Package Diagrams. Page 17 of 19 CY7C1061DV33 Document History Page (continued) Document Title: CY7C1061DV33, 16-Mbit (1 M × 16) Static RAM Document Number: 38-05476 Rev. ECN No. Orig. of Change Submission Date Description of Change *G 3126531 PRAS 01/03/2011 Added 48-ball VFBGA Single Chip Enable package related information in all instances across the document. Updated Ordering Information. Added Acronyms. *H 3414708 TAVA 10/19/2011 Updated Features. Updated DC Electrical Characteristics. Updated Switching Waveforms. Updated Package Diagrams. Added Units of Measure. Updated to new template. *I 4574311 TAVA 11/19/2014 Updated Functional Description: Added “For a complete list of related documentation, click here.” at the end. Updated Package Diagrams: spec 51-85160 – Changed revision from *C to *E. spec 51-85178 – Changed revision from *A to *C. *J 4990813 NILE 10/27/2015 Updated Thermal Resistance: Changed value of JA parameter corresponding to 54-pin TSOP II package from 24.18 C/W to 76.15 C/W. Changed value of JC parameter corresponding to 54-pin TSOP II package from 5.40 C/W to 14.15 C/W. Updated Switching Waveforms: Added Note 24 and referred the same note in Figure 10. Updated to new template. Completing Sunset Review. Document Number: 38-05476 Rev. *J Page 18 of 19 CY7C1061DV33 Sales, Solutions, and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office closest to you, visit us at Cypress Locations. PSoC® Solutions Products Automotive cypress.com/go/automotive Clocks & Buffers Interface Lighting & Power Control Memory cypress.com/go/clocks cypress.com/go/interface cypress.com/go/powerpsoc cypress.com/go/memory PSoC cypress.com/go/psoc Touch Sensing cypress.com/go/touch USB Controllers Wireless/RF psoc.cypress.com/solutions PSoC 1 | PSoC 3 | PSoC 4 | PSoC 5LP Cypress Developer Community Community | Forums | Blogs | Video | Training Technical Support cypress.com/go/support cypress.com/go/USB cypress.com/go/wireless © Cypress Semiconductor Corporation, 2004-2015. The information contained herein is subject to change without notice. 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Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Use may be limited by and subject to the applicable Cypress software license agreement. Document Number: 38-05476 Rev. *J Revised October 27, 2015 All products and company names mentioned in this document may be the trademarks of their respective holders. Page 19 of 19