ONSEMI BD809

ON Semiconductor NPN
BD809
Plastic High Power Silicon
Transistor
PNP
BD810
. . . designed for use in high power audio amplifiers utilizing
complementary or quasi complementary circuits.
• DC Current Gain —
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hFE = 30 (Min) @ IC = 2.0 Adc
MAXIMUM RATINGS
Symbol
Value
Unit
Collector–Emitter Voltage
Rating
VCEO
80
Vdc
Collector–Base Voltage
VCBO
80
Vdc
Emitter–Base Voltage
VEBO
5.0
Vdc
Collector Current
IC
10
Adc
Base Current
IB
6.0
Adc
Total Device Dissipation TC = 25C
Derate above 25C
PD
90
720
Watts
mW/C
TJ, Tstg
–55 to +150
C
Operating and Storage Junction
Temperature Range
10 AMPERE
POWER TRANSISTORS
PNP SILICON
60, 80 VOLTS
90 WATTS
4
1
2
STYLE 1:
PIN 1.
2.
3.
4.
BASE
COLLECTOR
EMITTER
COLLECTOR
3
THERMAL CHARACTERISTICS
Characteristic
Thermal Resistance, Junction to Case
 Semiconductor Components Industries, LLC, 2002
April, 2002 – Rev. 1
Symbol
Max
Unit
θJC
1.39
C/W
1
CASE 221A–09
TO–220AB
Publication Order Number:
BD809/D
BD809 BD810
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ELECTRICAL CHARACTERISTICS (TC = 25C unless otherwise noted)
Characteristic
Symbol
Collector–Emitter Sustaining Voltage*
(IC = 0.1 Adc, IB = 0)
Min
Max
Unit
—
—
Vdc
80
—
1.0
—
2.0
30
15
—
—
BVCEO
Collector Cutoff Current
(VCB = 80 Vdc, IE = 0)
ICBO
Emitter Cutoff Current
(VBE = 5.0 Vdc, IC = 0)
IEBO
DC Current Gain
(IC = 2.0 A, VCE = 2.0 V)
(IC = 4.0 A, VCE = 2.0 V)
hFE
mAdc
mAdc
Collector–Emitter Saturation Voltage*
(IC = 3.0 Adc, IB = 0.3 Adc)
VCE(sat)
—
1.1
Vdc
Base–Emitter On Voltage*
(IC = 4.0 Adc, VCE = 2.0 Vdc)
VBE(on)
—
1.6
Vdc
fT
1.5
—
MHz
Current–Gain Bandwidth Product
(IC = 1.0 Adc, VCE = 10 Vdc, f = 1.0 MHz)
*Pulse Test: Pulse Width 300 µs, Duty Cycle 2.0%.
1 ms
5 ms
10
3
PD, POWER DISSIPATION (WATTS)
IC, COLLECTOR CURRENT (AMP)
90
.5 ms
1 ms
dc
1
0.3
0.1
1
3
10
30
VCE, COLLECTOR-EMITTER VOLTAGE (VOLTS)
80
70
60
50
40
30
20
10
0
100
0
25
50
75
100
125
150
175
TC, CASE TEMPERATURE (°C)
Figure 1. Active Region DC Safe Operating Area
(see Note 1)
Figure 2. Power–Temperature Derating Curve
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2
BD809 BD810
NPN
BD809
PNP
BD810
500
500
TJ = 150°C
100
-55°C
50
20
VCE = 2.0 V
10
5.0
0.2
25°C
100
-55°C
50
20
10
5.0
1.0
2.0
IC, COLLECTOR CURRENT (AMP)
0.5
TJ = 150°C
200
25°C
hFE, DC CURRENT GAIN
hFE, DC CURRENT GAIN
200
10
5.0
20
VCE = 2.0 V
0.2
0.5
1.0
2.0
5.0
IC, COLLECTOR CURRENT (AMP)
10
20
2.0
VCE , COLLECTOR-EMITTER VOLTAGE (VOLTS)
VCE , COLLECTOR-EMITTER VOLTAGE (VOLTS)
Figure 3. DC Current Gain
TJ = 25°C
1.8
1.6
1.4
1.2
1.0
IC = 1.0 A
0.8
4.0 A
0.6
8.0 A
0.4
0.2
0
5.0
10
20
50 100
200 500 1000
IB, BASE CURRENT (mA)
2000 5000
2.0
TJ = 25°C
1.8
1.6
1.4
1.2
IC = 1.0 A
1.0
4.0 A
8.0 A
0.8
0.6
0.4
0.2
0
5.0
20
10
50 100
200 500 1000
IB, BASE CURRENT (mA)
2000 5000
Figure 4. Collector Saturation Region
2.8
2.8
V, VOLTAGE (VOLTS)
V, VOLTAGE (VOLTS)
2.0
1.6
1.2
VBE(sat) = IC/IB = 10
0.8
0
0.5
1.0
1.6
1.2
VBE(sat) @ IC/IB = 10
VBE @ VCE = 2.0 V
0.4
VCE(sat) @ IC/IB = 10
0.2
2.0
0.8
VBE @ VCE = 2.0 V
0.4
TJ = 25°C
2.4
TJ = 25°C
2.4
2.0
5.0
10
0
20
VCE(sat) @ IC/IB = 10
0.2
IC, COLLECTOR CURRENT (AMP)
0.5
1.0
2.0
5.0
IC, COLLECTOR CURRENT (AMP)
Figure 5. “On” Voltages
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3
10
20
r(t), NORMALIZED EFFECTIVE TRANSIENT
THERMAL RESISTANCE
BD809 BD810
1.0
0.7
0.5
D = 0.5
0.2
0.3
0.2
0.1
0.07
0.05
0.1
SINGLE P(pk)
PULSE
0.05
0.03
0.02
0.01
0.01
θJC(t) = r(t) θJC
D CURVES APPLY FOR POWER
PULSE TRAIN SHOWN
READ TIME AT t1
TJ(pk) - TC = P(pk) θJC(t)
0.02
SINGLE PULSE
0.01
0.02 0.03
0.05
0.1
0.2 0.3
0.5
1.0
2.0 3.0 5.0
t, PULSE WIDTH (ms)
20
30
50
t1
t2
DUTY CYCLE, D = t1/t2
100
200 300
500
1000
Figure 6. Thermal Response
Note 1:
The data of Figure 1 is based on T J(pk) = 150C; TC is
variable depending on conditions. Second breakdown pulse
limits are valid for duty cycles to 10% provided T J(pk)
150C. At high case temperatures, thermal limitations
will reduce the power that can be handled to values less than
the limitations imposed by second breakdown.
There are two limitations on the power handling ability of
a transistor: average junction temperature and second
breakdown. Safe operating area curves indicate IC – VCE
limits of the transistor that must be observed for reliable
operation, i.e., the transistor must not be subjected to greater
dissipation than the curves indicate.
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4
BD809 BD810
Notes
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5
BD809 BD810
Notes
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6
BD809 BD810
PACKAGE DIMENSIONS
TO–220
CASE 221A–09
ISSUE AA
–T–
B
SEATING
PLANE
C
F
T
S
4
DIM
A
B
C
D
F
G
H
J
K
L
N
Q
R
S
T
U
V
Z
A
Q
1 2 3
U
H
K
Z
L
R
V
J
G
D
N
STYLE 1:
PIN 1.
2.
3.
4.
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION Z DEFINES A ZONE WHERE ALL
BODY AND LEAD IRREGULARITIES ARE
ALLOWED.
BASE
COLLECTOR
EMITTER
COLLECTOR
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7
INCHES
MIN
MAX
0.570
0.620
0.380
0.405
0.160
0.190
0.025
0.035
0.142
0.147
0.095
0.105
0.110
0.155
0.018
0.025
0.500
0.562
0.045
0.060
0.190
0.210
0.100
0.120
0.080
0.110
0.045
0.055
0.235
0.255
0.000
0.050
0.045
----0.080
MILLIMETERS
MIN
MAX
14.48
15.75
9.66
10.28
4.07
4.82
0.64
0.88
3.61
3.73
2.42
2.66
2.80
3.93
0.46
0.64
12.70
14.27
1.15
1.52
4.83
5.33
2.54
3.04
2.04
2.79
1.15
1.39
5.97
6.47
0.00
1.27
1.15
----2.04
BD809 BD810
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make
changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any
particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all
liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or
specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be
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may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC
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8
BD809/D