NTD80N02 Power MOSFET 24 V, 80 A, N−Channel DPAK Designed for low voltage, high speed switching applications in power supplies, converters and power motor controls and bridge circuits. http://onsemi.com Features • Pb−Free Packages are Available Typical Applications RDS(on) TYP ID MAX 24 V 5.0 m 80 A Power Supplies Converters Power Motor Controls Bridge Circuits N−Channel D G MAXIMUM RATINGS (TJ = 25°C unless otherwise noted) Symbol Value Unit Drain−to−Source Voltage VDSS 24 Vdc Gate−to−Source Voltage − Continuous VGS ±20 Vdc ID Adc Drain Current − Continuous @ TC = 25°C Drain Current − Single Pulse (tp = 10 s) IDM 80* 200 Total Power Dissipation @ TC = 25°C PD 75 Watts TJ, Tstg −55 to 150 °C EAS 733 mJ RθJC RθJA RθJA 1.65 67 120 TL 260 Operating and Storage Temperature Range Single Pulse Drain−to−Source Avalanche Energy − Starting TJ = 25°C (VDD = 24 Vdc, VGS = 10 Vdc, IL = 17 Apk, L = 5.0 mH, RG = 25 Ω) Thermal Resistance − Junction−to−Case − Junction−to−Ambient (Note 1) − Junction−to−Ambient (Note 2) Maximum Lead Temperature for Soldering Purposes, 1/8″ from case for 10 seconds S 4 4 4 °C/W 1 2 3 3 12 3 CASE 369C CASE 369D CASE 369AA DPAK DPAK DPAK (Surface Mount) (Surface Mount) (Straight Lead) STYLE 2 STYLE 2 STYLE 2 MARKING DIAGRAMS & PIN ASSIGNMENTS °C Maximum ratings are those values beyond which device damage can occur. Maximum ratings applied to the device are individual stress limit values (not normal operating conditions) and are not valid simultaneously. If these limits are exceeded, device functional operation is not implied, damage may occur and reliability may be affected. 1. When surface mounted to an FR4 board using 1″ pad size, (Cu Area 1.127 in2). 2. When surface mounted to an FR4 board using the minimum recommended pad size, (Cu Area 0.412 in2). *Chip current capability limited by package. 1 2 4 Drain 4 Drain YWW 80 N02 Rating YWW 80 N02 • • • • V(BR)DSS 1 Gate 2 Drain 3 Source Y WW 80N02 1 Gate 2 Drain 3 Source = Year = Work Week = Device Code ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page 5 of this data sheet. Semiconductor Components Industries, LLC, 2004 December, 2004 − Rev. 4 1 Publication Order Number: NTD80N02/D NTD80N02 ELECTRICAL CHARACTERISTICS (TJ = 25°C unless otherwise noted) Characteristic Symbol Min Typ Max Unit 24 − 27 25 − − − − − − 1.0 10 − − ±100 1.0 − 1.9 −3.8 3.0 − − − − 5.0 7.5 5.0 7.5 5.8 9.0 5.8 9.0 gFS − 20 − Mhos pF OFF CHARACTERISTICS Drain−to−Source Breakdown Voltage (Note 3) (VGS = 0 Vdc, ID = 250 Adc) Positive Temperature Coefficient V(BR)DSS Zero Gate Voltage Drain Current (VGS = 0 Vdc, VDS = 24 Vdc) (VGS = 0 Vdc, VDS = 24 Vdc, TJ = 125°C) IDSS Gate−Body Leakage Current (VGS = ±20 Vdc, VDS = 0 Vdc) IGSS Vdc mV/°C Adc nAdc ON CHARACTERISTICS (Note 3) Gate Threshold Voltage (Note 3) (VDS = VGS, ID = 250 Adc) Negative Threshold Temperature Coefficient VGS(th) Static Drain−to−Source On−Resistance (Note 3) (VGS = 10 Vdc, ID = 80 Adc) (VGS = 4.5 Vdc, ID = 40 Adc) (VGS = 10 Vdc, ID = 20 Adc) (VGS = 4.5 Vdc, ID = 20 Adc) RDS(on) Forward Transconductance (VDS = 15 Vdc, ID = 10 Adc) (Note 3) Vdc mV/°C mΩ DYNAMIC CHARACTERISTICS Input Capacitance (VDS = 20 Vdc, VGS = 0 V, f = 1.0 MHz) Output Capacitance Transfer Capacitance Ciss − 2250 2600 Coss − 900 1100 Crss − 400 525 td(on) − 17 30 SWITCHING CHARACTERISTICS (Note 4) Turn−On Delay Time (VGS = 4.5 4 5 Vdc, Vdc VDD = 20 Vdc, ID = 20 Adc, RG = 2 2.5 5 Ω) Rise Time Turn−Off Delay Time Fall Time Gate Charge Ga eC a ge (VGS = 4.5 Vdc, ID = 20 Adc, VDS = 20 Vdc) (Note 3) tr − 67 125 td(off) − 28 45 tf − 40 75 QT − 30 42 Q1 − 7.0 12 Q2 − 18 28 − − − 0.92 1.05 0.70 1.2 − − trr − 38 52 ta − 20 − tb − 18 − Qrr − 0.038 − ns nC SOURCE−DRAIN DIODE CHARACTERISTICS Forward On−Voltage (IS = 20 Adc, VGS = 0 Vdc) (Note 3) (IS = 40 Adc, VGS = 0 Vdc) (IS = 20 Adc, VGS = 0 Vdc, TJ = 150°C) VSD Reverse e e se Recovery eco e y Time e Ad VGS = 0 Vdc, Vd (IS = 20 Adc, dIS/dt = 100 A/s) (Note 3) Reverse Recovery Stored Charge 3. Pulse Test: Pulse Width ≤ 300 s, Duty Cycle ≤ 2%. 4. Switching characteristics are independent of operating junction temperatures. http://onsemi.com 2 Vdc nss C NTD80N02 100 ID, DRAIN CURRENT (AMPS) 4.4 V 4.6 V 8V 80 TJ = 25°C 4.2 V 4.8 V 5V 70 60 6.5 V 50 4V 5.2 V 6V ID, DRAIN CURRENT (AMPS) 9V 90 3.8 V 3.6 V 40 30 3.4 V 20 3.2 V 10 VGS = 3.0 V 0 0.5 1 1.5 2 2.5 3.5 3 4 VDS ≥ 24 V TJ = 25°C TJ = 125°C TJ = −55°C 2 3 4 5 6 VGS, GATE−TO−SOURCE VOLTAGE (V) Figure 1. On−Region Characteristics Figure 2. Transfer Characteristics 0.07 ID = 10 A TJ = 25°C 0.06 0.05 0.04 0.03 0.02 0.01 0 0 2 4 6 8 10 RDS(on), DRAIN−TO−SOURCE RESISTANCE (Ω) VDS, DRAIN−TO−SOURCE VOLTAGE (V) 0.015 TJ = 25°C 0.01 VGS = 4.5 V VGS = 10 V 0.005 0 55 60 65 70 75 80 VGS, GATE−TO−SOURCE VOLTAGE (V) ID, DRAIN CURRENT (A) Figure 3. On−Resistance versus Gate−To−Source Voltage Figure 4. On−Resistance versus Drain Current and Gate Voltage 0.015 1000 VGS = 0 V 0.0125 0.01 0.0075 ID = 80 A VDS = 10 V 0.005 0.0025 0 −50 −25 0 25 50 75 100 125 TJ = 125°C 100 ID = 80 A VDS = 4.5 V IDSS, LEAKAGE (nA) RDS(on), DRAIN−TO−SOURCE RESISTANCE RDS(on), DRAIN−TO−SOURCE RESISTANCE (Ω) 0 160 150 140 130 120 110 100 90 80 70 60 50 40 30 20 10 0 150 TJ = 100°C 10 1 TJ = 25°C 0.1 0.01 4 8 12 16 TJ, JUNCTION TEMPERATURE (°C) VDS, DRAIN−TO−SOURCE VOLTAGE (V) Figure 5. On−Resistance Variation with Temperature Figure 6. Drain−To−Source Leakage Current versus Voltage http://onsemi.com 3 20 VGS = 0 V TJ = 25°C 4000 3000 Ciss 2000 Coss 1000 Crss 0 −8 −6 −4 −2 0 2 4 VGS VDS 6 8 10 12 14 16 18 20 22 24 10 28 QT 8 20 VGS VD 6 16 Q1 4 Q2 12 8 2 ID = 1.0 A TJ = 25°C 0 0 10 20 30 40 4 0 50 Qg, TOTAL GATE CHARGE (nC) GATE−TO−SOURCE OR DRAIN−TO−SOURCE VOLTAGE (V) Figure 7. Capacitance Variation Figure 8. Gate−to−Source and Drain−to−Source Voltage versus Total Charge 80 1000 IS, SOURCE CURRENT (AMPS) VDD = 20 V ID = 20 A VGS = 10 V t, TIME (ns) 24 −VDS, DRAIN−TO−SOURCE VOLTAGE (V) C, CAPACITANCE (pF) 5000 VGS, GATE−TO−SOURCE VOLTAGE (V) NTD80N02 tr 100 tf td(off) td(on) 10 1 1 10 70 VGS = 0 V TJ = 25°C 60 50 40 30 20 10 0.55 0.60 0.65 0.70 0.75 0.80 0.85 0.90 0.95 1.00 100 RG, GATE RESISTANCE (Ω) VSD, SOURCE−TO−DRAIN VOLTAGE (V) Figure 9. Resistive Switching Time Variation versus Gate Resistance Figure 10. Diode Forward Voltage versus Current http://onsemi.com 4 NTD80N02 ID , DRAIN CURRENT (AMPS) 100 100 s di/dt 1 ms VGS = 10 V SINGLE PULSE TC = 25°C 10 tb 10 ms TIME dc 0.25 IS tp IS 1 0.1 trr ta RDS(on) LIMIT THERMAL LIMIT PACKAGE LIMIT 1 IS 10 100 VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS) Figure 12. Diode Reverse Recovery Waveform Figure 11. Maximum Rated Forward Biased Safe Operating Area Rthja(t), EFFECTIVE TRANSIENT THERMAL RESISTANCE 1000 MOUNTED TO MINIMUM RECOMMENDED FOOTPRINT DUTY CYCLE 100 D = 0.5 0.2 0.1 0.05 0.02 0.01 10 1 P(pk) t1 0.1 t2 DUTY CYCLE, D = t1/t2 SINGLE PULSE RθJA(t) = r(t) RθJA D CURVES APPLY FOR POWER PULSE TRAIN SHOWN READ TIME AT t1 TJ(pk) − TA = P(pk) RθJA(t) 0.01 1E−05 1E−04 1E−03 1E−02 1E−01 t, TIME (seconds) 1E+00 1E+01 1E+02 1E+03 Figure 13. Thermal Response − Various Duty Cycles ORDERING INFORMATION Order Number NTD80N02 Package Shipping† DPAK−3 75 Units / Rail NTD80N02G DPAK−3 (Pb−Free) 75 Units / Rail NTD80N02T4 DPAK−3 2500 / Tape & Reel NTD80N02T4G DPAK−3 (Pb−Free) 2500 / Tape & Reel NTD80N02−001 DPAK−3 Straight Lead 75 Units / Rail NTD80N02−1G DPAK−3 Straight Lead (Pb−Free) 75 Units / Rail NTD80N02−032 DPAK−3 Straight Lead (3.2 ± 0.5 mm) 75 Units / Rail NTD80N02−032G DPAK−3 Straight Lead (3.2 ± 0.5 mm) (Pb−Free) 75 Units / Rail †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. http://onsemi.com 5 NTD80N02 PACKAGE DIMENSIONS DPAK CASE 369AA−01 ISSUE O C B V NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. SEATING PLANE −T− E R 4 Z A S 1 2 DIM A B C D E F J L R S U V Z 3 U F J L D STYLE 2: PIN 1. GATE 2. DRAIN 3. SOURCE 4. DRAIN 2 PL 0.13 (0.005) M INCHES MIN MAX 0.235 0.245 0.250 0.265 0.086 0.094 0.025 0.035 0.018 0.024 0.033 0.045 0.018 0.023 0.090 BSC 0.180 0.215 0.025 0.040 0.020 −−− 0.035 0.050 0.155 −−− T SOLDERING FOOTPRINT* 6.20 0.244 3.0 0.118 2.58 0.101 5.80 0.228 1.6 0.063 6.172 0.243 SCALE 3:1 mm inches *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. http://onsemi.com 6 MILLIMETERS MIN MAX 5.97 6.22 6.35 6.73 2.19 2.38 0.63 0.88 0.46 0.61 0.83 1.14 0.46 0.58 2.29 BSC 4.57 5.45 0.63 1.01 0.51 −−− 0.89 1.27 3.93 −−− NTD80N02 PACKAGE DIMENSIONS DPAK CASE 369C−01 ISSUE O −T− C B V NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. SEATING PLANE E R 4 Z A S 1 2 DIM A B C D E F G H J K L R S U V Z 3 U K F J L H D G 2 PL 0.13 (0.005) M T INCHES MIN MAX 0.235 0.245 0.250 0.265 0.086 0.094 0.027 0.035 0.018 0.023 0.037 0.045 0.180 BSC 0.034 0.040 0.018 0.023 0.102 0.114 0.090 BSC 0.180 0.215 0.025 0.040 0.020 −−− 0.035 0.050 0.155 −−− STYLE 2: PIN 1. GATE 2. DRAIN 3. SOURCE 4. DRAIN SOLDERING FOOTPRINT* 6.20 0.244 3.0 0.118 2.58 0.101 5.80 0.228 1.6 0.063 6.172 0.243 SCALE 3:1 mm inches *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. http://onsemi.com 7 MILLIMETERS MIN MAX 5.97 6.22 6.35 6.73 2.19 2.38 0.69 0.88 0.46 0.58 0.94 1.14 4.58 BSC 0.87 1.01 0.46 0.58 2.60 2.89 2.29 BSC 4.57 5.45 0.63 1.01 0.51 −−− 0.89 1.27 3.93 −−− NTD80N02 PACKAGE DIMENSIONS DPAK CASE 369D−01 ISSUE B C B V NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. E R 4 Z A S 1 2 3 −T− SEATING PLANE K J F H D G DIM A B C D E F G H J K R S V Z INCHES MIN MAX 0.235 0.245 0.250 0.265 0.086 0.094 0.027 0.035 0.018 0.023 0.037 0.045 0.090 BSC 0.034 0.040 0.018 0.023 0.350 0.380 0.180 0.215 0.025 0.040 0.035 0.050 0.155 −−− MILLIMETERS MIN MAX 5.97 6.35 6.35 6.73 2.19 2.38 0.69 0.88 0.46 0.58 0.94 1.14 2.29 BSC 0.87 1.01 0.46 0.58 8.89 9.65 4.45 5.45 0.63 1.01 0.89 1.27 3.93 −−− 3 PL 0.13 (0.005) M STYLE 2: PIN 1. GATE 2. DRAIN 3. SOURCE 4. DRAIN T ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. 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