STL6NK55Z N-CHANNEL 550V - 1.2Ω - 5.2A PowerFLAT™ Zener-Protected SuperMESH™Power MOSFET ■ ■ ■ ■ ■ ■ ■ TYPE VDSS RDS(on) ID (1) Pw (1) STL6NK55Z 550 V < 1.4 Ω 5.2 A 75 W TYPICAL RDS(on) = 1.2 Ω EXTREMELY HIGH dv/dt CAPABILITY IMPROVED ESD CAPABILITY 100% AVALANCHE RATED GATE CHARGE MINIMIZED VERY LOW INTRINSIC CAPACITANCES VERY GOOD MANUFACTURING REPEATIBILITY DESCRIPTION The SuperMESH™ series is obtained through an extreme optimization of ST’s well established stripbased PowerMESH™ layout. In addition to pushing on-resistance significantly down, special care is taken to ensure a very good dv/dt capability for the most demanding applications. Such series complements ST full range of high voltage MOSFETs including revolutionary MDmesh™ products. PowerFLAT™(5x5) (Chip Scale Package) INTERNAL SCHEMATIC DIAGRAM APPLICATIONS ■ LIGHTING ■ IDEAL FOR OFF-LINE POWER SUPPLIES, ADAPTORS AND PFC ORDERING INFORMATION SALES TYPE MARKING PACKAGE PACKAGING STL6NK55Z L6NK55Z PowerFLAT™ (5x5) TAPE & REEL July 2002 1/8 STL6NK55Z ABSOLUTE MAXIMUM RATINGS Symbol VDS VDGR Parameter Value Unit Drain-source Voltage (VGS = 0) 550 V Drain-gate Voltage (RGS = 20 kΩ) 550 V VGS Gate- source Voltage ± 30 V ID (2) Drain Current (continuous) at TC = 25°C (Steady State) Drain Current (continuous) at TC = 100°C 0.86 0.54 A A IDM (2) Drain Current (pulsed) 3.44 A PTOT (2) Total Dissipation at TC = 25°C (Steady State) 2.5 W PTOT (1) Total Dissipation at TC = 25°C (Steady State) 75 W Derating Factor (2) 0.02 W/°C Gate source ESD(HBM-C=100pF, R=1.5KΩ) 3000 V/ns 4.5 V/ns –55 to 150 °C VESD(G-S) dv/dt (4) Tstg Tj Peak Diode Recovery voltage slope Storage Temperature Max. Operating Junction Temperature THERMAL DATA Symbol Rthj-F Parameter Thermal Resistance Junction-Foot (Drain) Rthj-amb (2) Thermal Resistance Junction-ambient Note: 1. 2. 3. 4. Max. Unit 1.67 °C/W 50 °C/W The value is rated according to Rthj-F. When Mounted on FR-4 Board of 1inch2, 2 oz Cu Pulse width limited by safe operating area ISD<5.7A, di/dt<300A/µs, VDD<V(BR)DSS , TJ<TJMAX AVALANCHE CHARACTERISTICS Symbol Parameter Max Value Unit IAR Avalanche Current, Repetitive or Not-Repetitive (pulse width limited by Tj max) 5.2 A EAS Single Pulse Avalanche Energy (starting Tj = 25 °C, ID = IAR, VDD = 50 V) 160 mJ GATE-SOURCE ZENER DIODE Symbol BVGSO Parameter Gate-Source Breakdown Voltage Test Conditions Igs=± 1mA (Open Drain) Min. 30 Typ. Max. Unit V PROTECTION FEATURES OF GATE-TO-SOURCE ZENER DIODES The built-in back-to-back Zener diodes have specifically been designed to enhance not only the device’s ESD capability, but also to make them safely absorb possible voltage transients that may occasionally be applied from gate to source. In this respect the Zener voltage is appropriate to achieve an efficient and cost-effective intervention to protect the device’s integrity. These integrated Zener diodes thus avoid the usage of external components. 2/8 STL6NK55Z ELECTRICAL CHARACTERISTICS (TCASE =25°C UNLESS OTHERWISE SPECIFIED) ON/OFF Symbol Parameter Test Conditions Min. Typ. Max. Drain-source Breakdown Voltage ID = 1 mA, VGS = 0 IDSS Zero Gate Voltage Drain Current (VGS = 0) VDS = Max Rating VDS = Max Rating, TC = 125 °C 1 50 µA µA IGSS Gate-body Leakage Current (VDS = 0) VGS = ± 20V ±10 µA VGS(th) Gate Threshold Voltage VDS = VGS, ID = 50µA 3.75 4.5 V RDS(on) Static Drain-source On Resistance VGS = 10V, ID = 2.6 A 1.2 1.4 Ω Typ. Max. Unit V(BR)DSS 550 Unit 3 V DYNAMIC Symbol gfs (1) Ciss Coss Crss Coss eq. (3) RG Parameter Forward Transconductance Input Capacitance Output Capacitance Reverse Transfer Capacitance Test Conditions Min. VDS = 10 V, ID = 2.6 A VDS = 25V, f = 1 MHz, VGS = 0 Equivalent Output Capacitance VGS = 0V, VDS = 0V to 440 V Gate Input Resistance f=1 MHz Gate DC Bias = 0 Test Signal Level = 20mV Open Drain 3.5 S 695 88 20 pF pF pF 48 pF 3 Ω SWITCHING Symbol Parameter Test Conditions Min. Typ. Max. Unit td(on) tr td(off) tf Turn-on Delay Time Rise time Turn-off Delay Time Fall Time VDD = 275 V, ID = 2.6 A RG = 4.7Ω VGS = 10 V (Resistive Load see, Figure 3) 14 20 31.5 18 Qg Qgs Qgd Total Gate Charge Gate-Source Charge Gate-Drain Charge VDD = 440V, ID = 5.2 A, VGS = 10V 25 4.5 14 35 nC nC nC Typ. Max. Unit 0.86 3.44 A A 1.6 V ns ns ns ns SOURCE DRAIN DIODE Symbol Parameter Test Conditions ISD ISDM (2) Source-drain Current Source-drain Current (pulsed) VSD (1) Forward On Voltage ISD =5.2 A, VGS = 0 Reverse Recovery Time Reverse Recovery Charge Reverse Recovery Current ISD = 5.2 A, di/dt = 100A/µs VDD =40V, Tj = 150°C (see test circuit, Figure 5) trr Qrr IRRM Min. 350 2.2 12.5 ns µC A Note: 1. Pulsed: Pulse duration = 300 µs, duty cycle 1.5 %. 2. Pulse width limited by safe operating area. 3. Coss eq. is defined as a constant equivalent capacitance giving the same charging time as Coss when VDS increases from 0 to 80% VDSS. 3/8 STL6NK55Z Output Characteristics Transconductance Gate Charge vs Gate-source Voltage 4/8 Transfer Characteristics Static Drain-source On Resistance Capacitance Variations STL6NK55Z Normalized Gate Thereshold Voltage vs Temp. Normalized On Resistance vs Temperature Source-drain Diode Forward Characteristics Normalized BVDSS vs Temperature 5/8 STL6NK55Z Fig. 1: Unclamped Inductive Load Test Circuit Fig. 2: Unclamped Inductive Waveform Fig. 3: Switching Times Test Circuit For Resistive Load Fig. 4: Gate Charge test Circuit Fig. 5: Test Circuit For Inductive Load Switching And Diode Recovery Times 6/8 STL6NK55Z PowerFLAT™(5x5) MECHANICAL DATA mm. inch DIM. MIN. TYP MAX. A 0.90 A1 MIN. TYP. MAX. 1.00 0.035 0.039 0.02 0.05 0.001 0.002 b 0.43 0.51 0.58 0.017 0.020 0.023 c 0.64 0.71 0.79 0.025 0.028 0.031 D 5.00 0.197 E 5.00 0.197 E2 e 2.49 2.57 1.27 2.64 0.098 0.101 0.104 0.050 7/8 STL6NK55Z Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. 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