Revised November 1999 74AC157 • 74ACT157 Quad 2-Input Multiplexer General Description Features The AC/ACT157 is a high-speed quad 2-input multiplexer. Four bits of data from two sources can be selected using the common Select and Enable inputs. The four outputs present the selected data in the true (noninverted) form. The AC/ACT157 can also be used as a function generator. ■ ICC and IOZ reduced by 50% ■ Outputs source/sink 24 mA ■ ACT157 has TTL-compatible inputs Ordering Code: Order Number 74AC157SC 74AC157SJ 74AC157MTC Package Number Package Description M16A 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150” Narrow Body M16D 16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide MTC16 74AC157PC N16E 16 -Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide 74ACT157SC M16A 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150” Narrow Body 74ACT157SJ M16D 16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide 74ACT157MTC MTC16 74ACT157PC N16E 16 -Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code. Logic Symbols Connection Diagram IEEE/IEC Pin Descriptions Pin Names Description I0a–I0d Source 0 Data Inputs I1a–I1d Source 1 Data Inputs E Enable Input S Select Input Za–Zd Outputs FACT is a trademark of Fairchild Semiconductor Corporation. © 1999 Fairchild Semiconductor Corporation DS009929 www.fairchildsemi.com 74AC157 • 74ACT157 Quad 2-Input Multiplexer November 1988 74AC157 • 74ACT157 Functional Description Truth Table The AC/ACT157 is a quad 2-input multiplexer. It selects four bits of data from two sources under the control of a common Select input (S). The Enable input (E) is activeLOW. When E is HIGH, all of the outputs (Z) are forced LOW regardless of all other inputs. The AC/ACT157 is the logic implementation of a 4-pole, 2-position switch where the position of the switch is determined by the logic levels supplied to the Select input. The logic equations for the outputs are shown below: Inputs Za = E • (I1a • S + I0a • S) Outputs E S I0 I1 H X X X L L H X L L L H X H H L L L X L L L H X H H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial Zb = E • (I1b • S + I0b • S) Zc = E • (I1c • S + I0c • S) Zd = E • (I1d • S + I0d • S) A common use of the AC/ACT157 is the moving of data from two groups of registers to four common output busses. The particular register from which the data comes is determined by the state of the Select input. A less obvious use is as a function generator. The AC/ACT157 can generate any four of the sixteen different functions of two variables with one variable common. This is useful for implementing gating functions. Logic Diagram Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays. www.fairchildsemi.com 2 Z Supply Voltage (VCC) Recommended Operating Conditions −0.5V to +7.0V DC Input Diode Current (IIK) VI = −0.5V −20 mA VI = VCC + 0.5V +20 mA DC Input Voltage (VI) Supply Voltage (VCC) −0.5V to VCC + 0.5V DC Output Diode Current (IOK) VO = −0.5V −20 mA VO = VCC + 0.5V +20 mA DC Output Voltage (VO) 4.5V to 5.5V 0V to VCC Output Voltage (VO) 0V to VCC −40°C to +85°C Operating Temperature (TA) Minimum Input Edge Rate (∆V/∆t) −0.5V to VCC + 0.5V AC Devices VIN from 30% to 70% of VCC ±50 mA VCC @ 3.3V, 4.5V, 5.5V DC VCC or Ground Current 125 mV/ns Minimum Input Edge Rate (∆V/∆t) ±50 mA per Output Pin (ICC or IGND) Storage Temperature (TSTG) 2.0V to 6.0V ACT Input Voltage (VI) DC Output Source or Sink Current (IO) AC ACT Devices −65°C to +150°C VIN from 0.8V to 2.0V Junction Temperature (TJ) VCC @ 4.5V, 5.5V PDIP 140°C 125 mV/ns Note 1: Absolute maximum ratings are those values beyond which damage to the device may occur. The databook specifications should be met, without exception, to ensure that the system design is reliable over its power supply, temperature, and output/input loading variables. Fairchild does not recommend operation of FACT circuits outside databook specifications. DC Electrical Characteristics for AC Symbol VIH Parameter Minimum HIGH Level Input Voltage VIL VOH VCC TA = +25°C (V) Typ 3.0 1.5 TA = −40°C to +85°C Guaranteed Limits 2.1 Units 4.5 2.25 3.15 3.15 5.5 2.75 3.85 3.85 Maximum LOW Level 3.0 1.5 0.9 0.9 Input Voltage 4.5 2.25 1.35 1.35 5.5 2.75 1.65 1.65 Minimum HIGH Level 3.0 2.99 2.9 2.9 Output Voltage 4.5 4.49 4.4 4.4 5.5 5.49 5.4 5.4 3.0 2.56 2.46 4.5 3.86 3.76 Conditions VOUT = 0.1V 2.1 V or VCC − 0.1V V OUT = 0.1V V or VCC − 0.1V V IOUT = −50 µA VIN = VIL or VIH 5.5 VOL 4.86 4.76 Maximum LOW Level 3.0 0.002 0.1 0.1 Output Voltage 4.5 0.001 0.1 0.1 5.5 0.001 0.1 0.1 3.0 0.36 0.44 4.5 0.36 0.44 5.5 0.36 0.44 5.5 ±0.1 IOH = −12 mA V IOH = −24 mA IOH = −24 mA (Note 2) V IOUT = 50 µA VIN = VIL or VIH IIN Maximum Input IOL = 12 mA V IOL = 24 mA IOL = 24 mA (Note 2) (Note 4) Leakage Current ±1.0 µA IOLD Minimum Dynamic 5.5 75 mA V OLD = 1.65V Max IOHD Output Current (Note 3) 5.5 −75 mA V OHD = 3.85V Min 40.0 µA ICC Maximum Quiescent (Note 4) Supply Current 5.5 4.0 V I = VCC, GND V IN = VCC or GND Note 2: All outputs loaded; thresholds on input associated with output under test. Note 3: Maximum test duration 2.0 ms, one output loaded at a time. Note 4: IIN and ICC @ 3.0V are guaranteed to be less than or equal to the respective limit @ 5.5V VCC. 3 www.fairchildsemi.com 74AC157 • 74ACT157 Absolute Maximum Ratings(Note 1) 74AC157 • 74ACT157 DC Characteristics for ACT Symbol Parameter Minimum HIGH Level VIH VIL VOH TA = +25°C VCC (V) Typ 4.5 1.5 TA = −40°C to +85°C Guaranteed Limits 2.0 Units 2.0 Input Voltage 5.5 1.5 2.0 2.0 Maximum LOW Level 4.5 1.5 0.8 0.8 Input Voltage 5.5 1.5 0.8 0.8 Minimum HIGH Level 4.5 4.49 4.4 4.4 Output Voltage 5.5 5.49 5.4 5.4 V V V Conditions VOUT = 0.1V or VCC − 0.1V VOUT = 0.1V or VCC − 0.1V IOUT = −50 µA VIN = VIL or VIH VOL 4.5 3.86 3.76 5.5 4.86 4.76 Maximum LOW Level 4.5 0.001 0.1 0.1 Output Voltage 5.5 0.001 0.1 0.1 4.5 0.36 0.44 5.5 0.36 0.44 5.5 ±0.1 ±1.0 V IOH = −24 mA IOH = −24 mA (Note 5) V IOUT = 50 µA VIN = VIL or VIH IIN Maximum Input Leakage Current ICCT Maximum V IOL = 24 mA IOL = 24 mA (Note 5) µA VI = VCC, GND 1.5 mA VI = VCC − 2.1V IOLD Minimum Dynamic 5.5 75 mA VOLD = 1.65V Max IOHD Output Current (Note 6) 5.5 −75 mA VOHD = 3.85V Min ICC Maximum Quiescent 40.0 µA 5.5 ICC/Input Supply Current 0.6 5.5 4.0 VIN = V CC or GND Note 5: All outputs loaded; thresholds on input associated with output under test. Note 6: Maximum test duration 2.0 ms, one output loaded at a time. AC Electrical Characteristics for AC Symbol tPLH tPHL tPLH tPHL tPLH tPHL Parameter VCC TA = +25°C (V) CL = 50 pF TA = −40°C to +85°C CL = 50 pF (Note 7) Min Typ Max Min Max Propagation Delay 3.3 1.5 7.0 11.5 1.5 13.0 S to Zn 5.0 1.5 5.5 9.0 1.5 10.0 Propagation Delay 3.3 1.5 6.5 11.0 1.5 12.0 S to Zn 5.0 1.5 5.0 8.5 1.0 9.5 Propagation Delay 3.3 1.5 7.0 11.5 1.5 13.0 E to Zn 5.0 1.5 5.5 9.0 1.5 10.0 Propagation Delay 3.3 1.5 6.5 11.0 1.5 12.0 E to Zn 5.0 1.5 5.5 9.0 1.0 9.5 Propagation Delay 3.3 1.5 5.0 8.5 1.0 9.0 In to Zn 5.0 1.5 4.0 6.5 1.0 7.0 Propagation Delay 3.3 1.5 5.0 8.0 1.0 9.0 In to Zn 5.0 1.5 4.0 6.5 1.0 7.0 Note 7: Voltage Range 3.3 is 3.3V ± 0.3V Voltage Range 5.0 is 5.0V ± 0.5V www.fairchildsemi.com 4 Units ns ns ns ns ns ns Symbol tPLH Parameter Propagation Delay S to Zn tPHL Propagation Delay S to Zn tPLH Propagation Delay E to Zn tPHL Propagation Delay E to Zn tPLH Propagation Delay In to Zn tPHL Propagation Delay In to Zn VCC TA = +25°C (V) CL = 50 pF TA = −40°C to +85°C CL = 50 pF Units (Note 8) Min Typ Max Min Max 5.0 2.0 5.5 9.0 1.5 10.0 ns 5.0 2.0 5.5 9.5 2.0 10.5 ns 5.0 1.5 6.0 10.0 1.5 11.5 ns 5.0 1.5 5.0 8.5 1.0 9.0 ns 5.0 1.5 4.0 7.0 1.0 8.5 ns 5.0 1.5 4.5 7.5 1.0 8.5 ns Note 8: Voltage Range 5.0 is 5.0V ± 0.5V Capacitance Typ Units CIN Symbol Input Capacitance Parameter 4.5 pF V CC = OPEN CPD Power Dissipation Capacitance 50.0 pF V CC = 5.0V 5 Conditions www.fairchildsemi.com 74AC157 • 74ACT157 AC Electrical Characteristics for ACT 74AC157 • 74ACT157 Physical Dimensions inches (millimeters) unless otherwise noted 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150” Narrow Body Package Number M16A www.fairchildsemi.com 6 74AC157 • 74ACT157 Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide Package Number M16D 7 www.fairchildsemi.com 74AC157 • 74ACT157 Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 16- Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide Package Number MTC16 www.fairchildsemi.com 8 74AC157 • 74ACT157 Quad 2-Input Multiplexer Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide Package Number N16E Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. www.fairchildsemi.com 9 www.fairchildsemi.com