® ISO 9001 Registered Process C1004 CMOS 1.0µm 5 Volt Digital Electrical Characteristics N-Channel Transistor Threshold Voltage Body Factor Conduction Factor Effective Channel Length Width Encroachment Punch Through Voltage Poly Field Threshold Symbol VTN γN βN LeffN ∆WN BVDSSN VTFP(N) Minimum 0.55 P-Channel Transistor Threshold Voltage Body Factor Conduction Factor Effective Channel Length Width Encroachment Punch Through Voltage Poly Field Threshold Voltage Symbol VTP γP βP LeffP ∆WP BVDSSP VTFP(P) Minimum –0.85 Diffusion & Thin Films Well (field) Sheet Resistance N+ Sheet Resistance N+ Junction Depth P+ Sheet Resistance P+ Junction Depth Gate Oxide Thickness Field Oxide Thickness Poly Sheet Resistance Metal-1 Sheet Resistance Metal-2 Sheet Resistance Passivation Thickness Symbol ρN-well(f) ρN+ xjN+ ρP+ xjP+ TGOX TFIELD ρPOLY ρM1 ρM2 TPASS Minimum 0.8 20 Capacitance Gate Oxide Metal-1 to Poly1 Metal-1 to SIlicon Metal-2 to Metal-1 Symbol Cox CM1P CMIS CMM Minimum 1.52 © IMP, Inc. 74 0.60 Typical 0.75 0.60 87 0.75 0.8 7 10 24 0.83 T=25oC Unless otherwise noted Maximum Unit Comments 0.95 V 100x1.0µm V1/2 100x1.0µm 100 µA/V2 100x100µm 0.90 µm 100x1.0µm µm Per side V V Typical –1.0 0.4 28 0.98 0.85 Maximum –1.15 Typical 1.0 35 0.45 80 0.5 20 700 22 50 30 200+900 Maximum 1.22 50 Typical 1.64 0.046 0.028 0.038 Maximum 1.82 32 1.13 –7 –10 60 15 100 30 Unit V V1/2 µA/V2 µm µm V V Comments 100x1.0µm 100x1.0µm 100x100µm 100x1.0µm Per side Unit KΩ/o Ω/o µm Ω/o µm nm nm Ω/o mΩ/o mΩ/o nm Comments n-well Unit fF/µm2 fF/µm2 fF/µm2 fF/µm2 oxide+nit. Comments 17 Process C1004 Physical Characteristics Starting Material Starting Mat. Resistivity Typ. Operating Voltage Well Type Metal Layers Poly Layers Contact Size Via Size Metal-1 Width/Space Metal-2 Width/Space Gate Poly Width/Space P <100> 7-8.5 Ω-cm 5V N-well 2 1 1.2x1.2µm 1.2x1.2µm 1.4 / 1.2µm 2.0 / 1.4µm 1.0 / 1.4µm N+/P+ Width/Space N+ To P+ Space Contact To Poly Space Contact Overlap Of Diffusion Contact Overlap Of Poly Metal-1 Overlap Of Contact Metal-1 Overlap Of Via Metal-2 Overlap Of Via Minimum Pad Opening Minimum Pad-to-Pad Spacing Minimum Pad Pitch 2.0 / 1.2µm 7.0µm 0.8µm 0.7µm 0.7µm 0.7µm 0.7µm 0.7µm 65x65µm 5.0µm 80.0µm Metal 2 SIO2 Metal 1 LTO LTO p+ substrate VGS = 5.0V VGS = 4.0V 21.0 VGS = 3.0V 14.0 VGS = 2.0V VGS = 1.0V 0 1.0 2.0 3.0 4.0 –12.0 VGS = –4.0V –9.0 –6.0 0 5.0 Drain Voltage (V) VDS N-ch Transistor IV Characteristics of a 20/1.2 device 18 VGS = –5.0V VGS = –3.0V –3.0 7.0 0 Source –15.0 Drain Current (mA) IDS Drain Current (mA) IDS 28.0 C1004-4-98 p ID vs VD, W/L = 20/1.2 ID vs VD, W/L = 20/1.2 35.0 Channel stop p–epi p+ p– substrate contact Sidewall spacer LDD Poly gate n+ Drain N-well p Contact N-well contact n+ Drain p+ Poly gate p+ Source n+ Field Oxide VGS = –2.0V 0 –1.0 –2.0 –3.0 –4.0 –5.0 Drain Voltage (V) VDS P-ch Transistor IV Characteristics of a 20/1.2 device