® ISO 9001 Registered Process C1210 CMOS 1.2µm Zero Threshold Devices Electrical Characteristics N-Channel Transistor Threshold Voltage Body Factor Conduction Factor Effective Channel Length Width Encroachment Punch Through Voltage Poly Field Threshold Voltage Symbol VTN γN βN LeffN ∆WN BVDSSN VTFP(N) Minimum 0.55 Zero Vt N-Channel Transis. Threshold Voltage Body Factor Conduction Factor Saturation Current Symbol VTZLN γZLN βZLN IDSATZN Minimum 0.00 P-Channel Transistor Threshold Voltage Body Factor Conduction Factor Effective Channel Length Width Encroachment Punch Through Voltage Poly Field Threshold Voltage Symbol VTP γP βP LeffP ∆WP BVDSSP VTFP(P) Minimum –0.7 Zero Vt P-Channel Transis. Threshold Voltage Body Factor Conduction Factor Saturation Current Symbol VTZLP γZLP βZLP IDSATZP Minimum –0.3 © IMP, Inc. 64 0.8 Typical 0.75 0.34 75 1.0 0.6 9 10 75 28 21 0.9 T=25oC Unless otherwise noted Maximum Unit Comments 0.95 V 100x1.2µm V1/2 100x1.2µm 86 µA/V2 100x100µm 1.2 µm 100x1.2µm µm Per side V V Typical 0.15 0.348 90 34 Maximum 0.30 Typical –0.9 0.38 25 1.1 0.8 Maximum –1.1 Typical –0.1 0.36 26 –15 Maximum 0.1 105 40 29 1.3 –9.0 –10.0 21 –11 31 –19 Unit V V1/2 µA/V2 mA Comments 100x100µm 100x100µm 100x100µm 100x1.5µm Unit V V1/2 µA/V2 µm µm V V Comments 100x1.2µm 100x1.2µm 100x100µm 100x1.2µm Per side Unit V V1/2 µA/V2 mA Comments 100x100µm 100x100µm 100x100µm 100x1.5µm 47 Process C1210 Electrical Characteristics Diffusion & Thin Films Well (field) Sheet Resistance N+ Sheet Resistance N+ Junction Depth P+ Sheet Resistance P+ Junction Depth Gate Oxide Thickness Field Oxide Thickness Gate Poly Sheet Resistance Bottom Poly Sheet Res. Metal-1 Sheet Resistance Metal-2 Sheet Resistance Passivation Thickness Symbol ρN-well(f) ρN+ xjN+ ρP+ xjP+ TGOX TFIELD ρPOLY2 ρPOLY1 ρM1 ρM2 TPASS Minimum 0.6 20 Capacitance Gate Oxide Metal-1 to Poly-1 Metal-1 to Silicon Metal-2 to Metal-1 Poly-1 to Poly-2 Symbol COX CM1P CM1S CMM CP1P2 Minimum 1.28 48 C1210-4-98 50 15 0.69 Typical 1.0 35 0.35 75 0.35 24 800 22 35 50 30 200+900 Maximum 1.3 50 Typical 1.38 0.057 Maximum 1.58 0.035 0.86 100 30 1.03 Unit KΩ/o Ω/o µm Ω/o µm nm nm Ω/o Ω/o mΩ/o mΩ/o nm Unit fF/µm2 fF/µm2 fF/µm2 fF/µm2 fF/µm2 Comments n-well oxide+nit. Comments Process C1210 Physical Characteristics Starting Material Starting Mat. Resistivity Typ. Operating Voltage Well Type Metal Layers Poly Layers Contact Size Via Size Metal-1 Width/Space Metal-2 Width/Space Gate Poly Width/Space EPI P <100> 7 - 8.5 Ω-cm 5V N-well 2 2 1.5x1.5µm 1.5x1.5µm 2.5 / 1.5µm 2.5 / 1.5µm 1.5 / 2.0µm N+/P+ Width/Space N+ To P+ Space Contact To Poly Space Contact Overlap Of Diffusion Contact Overlap Of Poly Metal-1 Overlap Of Contact Metal-1 Overlap Of Via Metal-2 Overlap Of Via Minimum Pad Opening Minimum Pad-to-Pad Spacing Minimum Pad Pitch 2.5/ 2.0µm 9.0µm 1.5µm 1.0µm 1.0µm 1.0µm 1.0µm 1.0µm 65x65µm 5.0µm 80.0µm Special Feature of C1210 Process: This process offers zero threshold n- and p-channel transistors in addition to normal threshold transistors of CMOS 1.2µm technology. SIO2 LTO LTO Contact Poly gate Channel stop Source substrate p Bottom poly Field Oxide p+ p– substrate contact p–epi p+ Sidewall spacer LDD Poly gate p Drain N-well n+ Contact n+ Drain N-well contact Source p+ Poly gate p+ Sidewall spacer Metal 1 n+ Metal 1 VIA Metal 2 Cross-Sectional view of the LVMOS process ID vs VD, W/L = 20/1.2 ID vs VD, W/L = 20/1.2 VGS = 4.0V 5.5 VGS = –5.0V -3.0 0.55 mA /div Drain Current ID (mA) Drain Current ID (mA) VGS = –4.0V VGS = 3.0V VGS = 2.0V VGS = –3.0V 0.3 mA /div VGS = –2.0V VGS = 1.0V VGS = –1.0V .00 VGS = 0V 0 1 2 3 4 Drain Voltage (v) VDS 5 n-ch Transistor IV characteristics of a 20/1.2 device © IMP, Inc. .00 VGS = 0.0V 0 –1 –2 –3 –4 Drain Voltage (v) VDS –5 p-ch Transistor IV characteristics of a 20/1.2 device 49 50 C1210-4-98