NEC UPA2717GR

DATA SHEET
MOS FIELD EFFECT TRANSISTOR
µ PA2717GR
SWITCHING
P-CHANNEL POWER MOS FET
DESCRIPTION
PACKAGE DRAWING (Unit: mm)
The µ PA2717GR is P-Channel MOS Field Effect Transistor
designed for power management applications of notebook
computers and Li-ion battery protection circuit.
8
5
1, 2, 3
: Source
4
: Gate
5, 6, 7, 8 : Drain
FEATURES
• Low on-state resistance
RDS(on)1 = 5.5 mΩ MAX. (VGS = –10 V, ID = –7.5 A)
RDS(on)2 = 8.9 mΩ MAX. (VGS = –4.5 V, ID = –7.5 A)
• Low Ciss: Ciss = 3550 pF TYP.
• Built-in gate protection diode
• Small and surface mount package (Power SOP8)
4.4
5.37 MAX.
0.15
0.05 MIN.
PACKAGE
µ PA2717GR
6.0 ±0.3
4
0.8
+0.10
–0.05
1.8 MAX.
ORDERING INFORMATION
PART NUMBER
1.44
1
0.5 ±0.2
0.10
1.27 0.78 MAX.
0.40
+0.10
–0.05
0.12 M
Power SOP8
ABSOLUTE MAXIMUM RATINGS (TA = 25°C, All terminals are connected.)
Drain to Source Voltage (VGS = 0 V)
VDSS
–30
V
Gate to Source Voltage (VDS = 0 V)
VGSS
m20
V
Drain Current (DC)
ID(DC)
m15
A
ID(pulse)
m150
A
Drain Current (pulse)
Note1
Total Power Dissipation
Note2
PT1
2
W
Total Power Dissipation
Note3
PT2
2
W
Channel Temperature
Tch
150
°C
Storage Temperature
Tstg
–55 to + 150
°C
Single Avalanche Current
Note4
IAS
–15
A
Single Avalanche Energy
Note4
EAS
22.5
mJ
Notes 1.
2.
3.
4.
EQUIVALENT CIRCUIT
Drain
Body
Diode
Gate
Gate
Protection
Diode
Source
PW ≤ 10 µs, Duty Cycle ≤ 1%
Mounted on ceramic substrate of 1200 mm2 x 2.2 mm
Mounted on glass epoxy board of 1 inch x 1 inch x 0.8 mm, PW = 10 sec
Starting Tch = 25°C, VDD = –15 V, RG = 25 Ω, L = 100 µH, VGS = –20 → 0 V
Remark The diode connected between the gate and source of the transistor serves as a protector against ESD. When
this device actually used, an additional protection circuit is externally required if a voltage exceeding the rated
voltage may be applied to this device.
The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all products and/or types are available in every country. Please check with an NEC Electronics
sales representative for availability and additional information.
Document No. G16950EJ1V0DS00 (1st edition)
Date Published July 2004 NS CP(K)
Printed in Japan
2004
µ PA2717GR
ELECTRICAL CHARACTERISTICS (TA = 25°C, All terminals are connected.)
CHARACTERISTICS
SYMBOL
TEST CONDITIONS
MIN.
TYP.
MAX.
UNIT
Zero Gate Voltage Drain Current
IDSS
VDS = –30 V, VGS = 0 V
–1
µA
Gate Leakage Current
IGSS
VGS = m20 V, VDS = 0 V
m10
µA
–2.5
V
VGS(off)
VDS = –10 V, ID = –1 mA
–1.0
| yfs |
VDS = –10 V, ID = –7.5 A
13
RDS(on)1
VGS = –10 V, ID = –7.5 A
4.7
5.5
mΩ
RDS(on)2
VGS = –4.5 V, ID = –7.5 A
6.1
8.9
mΩ
RDS(on)3
VGS = –4.0 V, ID = –7.5 A
6.9
10.4
mΩ
Gate Cut-off Voltage
Forward Transfer Admittance
Note
Drain to Source On-state Resistance
Note
S
Input Capacitance
Ciss
VDS = –10 V
3550
pF
Output Capacitance
Coss
VGS = 0 V
1260
pF
Reverse Transfer Capacitance
Crss
f = 1 MHz
600
pF
td(on)
VDD = –15 V, ID = –7.5 A
17
ns
VGS = –10 V
32
ns
RG = 10 Ω
920
ns
510
ns
Turn-on Delay Time
Rise Time
tr
Turn-off Delay Time
td(off)
Fall Time
tf
Total Gate Charge
QG
VDD = –24 V
130
nC
Gate to Source Charge
QGS
VGS = –10 V
11
nC
QGD
ID = –15 A
36
nC
Gate to Drain Charge
Body Diode Forward Voltage
Note
VF(S-D)
IF = 15 A, VGS = 0 V
0.82
V
Reverse Recovery Time
trr
IF = 15 A, VGS = 0 V
500
ns
Reverse Recovery Charge
Qrr
di/dt = 50 A/µs
1320
nC
Note Pulsed
TEST CIRCUIT 1 AVALANCHE CAPABILITY
TEST CIRCUIT 2 SWITCHING TIME
D.U.T.
RG = 25 Ω
D.U.T.
L
RL
50 Ω
PG.
VGS = −20 → 0 V
VDD
RG
PG.
VGS(−)
VGS
Wave Form
0
VGS
10%
90%
VDD
VDS(−)
−
IAS
BVDSS
VDS
ID
VGS(−)
0
VDS
Wave Form
τ
VDD
Starting Tch
τ = 1 µs
Duty Cycle ≤ 1%
TEST CIRCUIT 3 GATE CHARGE
D.U.T.
PG.
2
IG = −2 mA
RL
50 Ω
VDD
Data Sheet G16950EJ1V0DS
VDS
90%
90%
10% 10%
0
td(on)
tr td(off)
ton
tf
toff
µ PA2717GR
TYPICAL CHARACTERISTICS (TA = 25°C)
TOTAL POWER DISSIPATION vs.
AMBIENT TEMPERATURE
2.8
120
PT - Total Power Dissipation - W
dT - Percentage of Rated Power - %
DERATING FACTOR OF FORWARD BIAS
SAFE OPERATING AREA
100
80
60
40
20
Mounted on ceramic substrate of
1200 mm2 x 2.2 mm
2.4
2
1.6
1.2
0.8
0.4
0
0
0
25
50
75
100
125
150
175
0
25
TA - Ambient Temperature - °C
50
75
100
125
150
175
TA - Ambient Temperature - °C
FORWARD BIAS SAFE OPERATING AREA
- 1000
PW = 100 µs
RDS(on) Limited
(at VGS = 10 V)
ID(DC)
- 10
-1
- 0.1
1 ms
DC
Power Dissipation Limited
10 ms
100 ms
TA = 25°C
Single pulse
Mounted on ceramic substrate of
2
1200 mm x 2.2 mm
- 0.01
- 0.01
- 0.1
-1
- 10
- 100
VDS - Drain to Source Voltage - V
TRANSIENT THERMAL RESISTANCE vs. PULSE WIDTH
1000
rth(t) - Transient Thermal Resistance - °C/W
ID - Drain Current - A
ID(pulse)
- 100
TA = 25°C, Single pulse
Rth(ch-A)1: Mounted on ceramic substrate of 1200 mm2 x 2.2 mm
Rth(ch-A)2: Mounted on glass epoxy board of 1 inch x 1 inch x 0.8 mm
Rth(ch-A)2
100
Rth(ch-A)1
10
1
0.1
100 µ
1m
10 m
100 m
1
PW - Pulse Width - s
Data Sheet G16950EJ1V0DS
10
100
1000
3
µ PA2717GR
DRAIN CURRENT vs.
DRAIN TO SOURCE VOLTAGE
FORWARD TRANSFER CHARACTERISTICS
- 150
- 1000
Pulsed
VGS = −10 V
−4.5 V
−4.0 V
- 100
ID - Drain Current - A
ID - Drain Current - A
- 125
- 75
- 50
VDS = −10 V
Pulsed
- 100
TA = 150°C
75°C
25°C
−40°C
- 10
-1
- 0.1
- 25
0
- 0.01
0
- 0.2
- 0.4
- 0.6
- 0.8
-1
0
VDS - Drain to Source Voltage - V
RDS(on) - Drain to Source On-state Resistance - mΩ
| yfs | - Forward Transfer Admittance - S
- 1.5
-1
- 0.5
50
100
150
100
-5
TA = 150°C
75°C
25°C
−40°C
10
1
VDS = −10 V
Pulsed
0.1
- 0.1
-1
- 10
- 100
ID - Drain Current - A
DRAIN TO SOURCE ON-STATE RESISTANCE vs.
DRAIN CURRENT
DRAIN TO SOURCE ON-STATE RESISTANCE vs.
GATE TO SOURCE VOLTAGE
20
Pulsed
VGS = −4 V
15
10
−4.5 V
5
−10 V
0
-1
- 10
- 100
- 1000
20
Pulsed
ID = −7.5 A
15
10
5
0
ID - Drain Current - A
4
-4
Tch - Channel Temperature - °C
RDS(on) - Drain to Source On-state Resistance - mΩ
VGS(off) - Gate Cut-off Voltage - V
VDS = −10 V
ID = −1 mA
0
-3
FORWARD TRANSFER ADMITTANCE vs.
DRAIN CURRENT
- 2.5
0
- 50
-2
VGS - Gate to Source Voltage - V
GATE CUT-OFF VOLTAGE vs.
CHANNEL TEMPERATURE
-2
-1
0
-5
- 10
- 15
VGS - Gate to Source Voltage - V
Data Sheet G16950EJ1V0DS
- 20
DRAIN TO SOURCE ON-STATE RESISTANCE vs.
CHANNEL TEMPERATURE
10000
ID = − 7.5 A
Pulsed
V GS = −4.0 V
−4.5 V
− 10 V
10
5
0
- 50
0
50
100
Ciss
1000
Coss
Crss
100
VGS = 0 V
f = 1 MHz
10
- 0.1
150
SWITCHING CHARACTERISTICS
1000
td(off)
tf
100
tr
td(on)
10
1
-0.1
VDS - Drain to Source Voltage - V
- 30
VDD = −15 V
VGS = −10 V
RG = 10 Ω
- 15
ID =15 A
VDD = −6 V
−15 V
−24 V
- 20
- 10
VGS
- 10
-5
VDS
0
-1
- 100
DYNAMIC INPUT/OUTPUT CHARACTERISTICS
10000
td(on), tr, td(off), tf - Switching Time - ns
- 10
VDS - Drain to Source Voltage - V
Tch - Channel Temperature - °C
-10
-100
0
50
100
ID - Drain Current - A
QG - Gate Charge - nC
SOURCE TO DRAIN DIODE FORWARD VOLTAGE
REVERSE RECOVERY TIME vs.
DIODE FORWARD CURRENT
1000
0
150
1000
trr - Reverse Recovery Time - ns
Pulsed
IF - Diode Forward Current - A
-1
VGS - Gate to Source Voltage - V
15
CAPACITANCE vs. DRAIN TO SOURCE VOLTAGE
Ciss, Coss, Crss - Capacitance - pF
RDS(on) - Drain to Source On-state Resistance - mΩ
µ PA2717GR
100
VGS = −10 V
10
0V
1
0.1
0.01
100
VGS = 0 V
di/dt = 50 A/µs
10
0
0.2
0.4
0.6
0.8
1
1.2
1.4
0.1
VF(S-D) - Source to Drain Voltage - V
1
10
100
IF - Diode Forward Current - A
Data Sheet G16950EJ1V0DS
5
µ PA2717GR
SINGLE AVALANCHE CURRENT vs.
INDUCTIVE LOAD
SINGLE AVALANCHE ENERGY
DERATING FACTOR
100
IAS = −15 A
- 10
EAS = 22.5 mJ
-1
VDD = −15 V
VGS = −20 → 0 V
RG = 25 Ω
Starting Tch = 25°C
- 0.1
0.01
VDD = −15 V
RG = 25 Ω
VGS = −20 → 0 V
IAS ≤ −15 A
80
60
40
20
0
0.1
1
L - Inductive Load - mH
6
Energy Derating Factor - %
IAS - Single Avalanche Current - A
- 100
10
25
50
75
100
125
150
Starting Tch - Starting Channel Temperature - °C
Data Sheet G16950EJ1V0DS
µ PA2717GR
• The information in this document is current as of July, 2004. The information is subject to change
without notice. For actual design-in, refer to the latest publications of NEC Electronics data sheets or
data books, etc., for the most up-to-date specifications of NEC Electronics products. Not all
products and/or types are available in every country. Please check with an NEC Electronics sales
representative for availability and additional information.
• No part of this document may be copied or reproduced in any form or by any means without the prior
written consent of NEC Electronics. NEC Electronics assumes no responsibility for any errors that may
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M8E 02. 11-1