LH531000B-S CMOS 1M (128K × 8) 3 V-Drive MROM FEATURES DESCRIPTION • 131,072 words × 8 bit organization The LH531000B-S is a mask-programmable ROM organized as 131,072 × 8 bits. It is fabricated using silicon-gate CMOS process technology. • Access time: 500 ns (MAX.) • Power consumption: Operating: 64.8 mW (MAX.) Standby: 108 µW (MAX.) • Mask-programmable control pin: Pin 20 = CE/OE/OE • Static operation • Three-state outputs • Low power supply: 2.6 V to 3.6 V • Package: 28-pin, 450-mil SOP PIN CONNECTIONS 28-PIN SOP TOP VIEW A15 1 28 VCC A12 2 27 A14 A7 3 26 A13 A6 4 25 A8 A5 5 24 A9 A4 6 23 A11 A3 7 22 A16 A2 8 21 A10 A1 9 20 CE/OE/OE A0 10 19 D7 D0 11 18 D6 D1 12 17 D5 D2 13 16 D4 GND 14 15 D3 531000BS-1 Figure 1. Pin Connections for DIP Package 1 LH531000B-S CMOS 1M MROM A16 22 A15 1 A14 27 A13 26 A10 21 A9 24 A8 25 A7 3 A6 4 A5 5 MEMORY MATRIX (131,072 x 8) ADDRESS DECODER ADDRESS BUFFER A12 2 A11 23 A4 6 A3 7 A2 8 COLUMN SELECTOR A1 9 A0 10 SENSE AMPLIFIER CE BUFFER TIMING GENERATOR CE/OE/OE 20 OE BUFFER OUTPUT BUFFER 28 14 VCC GND 11 D0 12 D1 13 D2 15 D3 16 D4 17 D5 18 D6 19 D7 531000BS-2 Figure 2. LH531000B-S Block Diagram PIN DESCRIPTION SIGNAL A0 – A16 D0 – D7 CE/OE/OE PIN NAME NOTE Address input 1 PIN NAME VCC Power supply (2.6 V to 3.6 V) GND Ground Data output Chip Enable input or Output Enable input NOTE: 1. Active level of CE/OE/OE is mask-programmable. 2 SIGNAL NOTE CMOS 1M MROM LH531000B-S TRUTH TABLE CE OE/OE MODE SUPPLY CURRENT H – High-Z Standby L – Output Operating – L/H High-Z – H/L Output Operating ABSOLUTE MAXIMUM RATINGS PARAMETER SYMBOL RATING UNIT Supply voltage VCC –0.3 to +7.0 V Input voltage VIN –0.3 to VCC + 0.3 V Output voltage VOUT –0.3 to VCC + 0.3 V Operating temperature Topr 0 to +70 °C Storage temperature Tstg – 65 to +150 °C RECOMMENDED OPERATING CONDITIONS (TA = 0°C to +70°C) PARAMETER SYMBOL MIN. VCC 2.6 Supply voltage TYP. MAX. UNIT 3.6 V DC CHARACTERISTICS (VCC = 2.6 V to 3.6 V, TA = 0°C to +70°C) PARAMETER SYMBOL CONDITIONS MIN. TYP. MAX. UNIT Input ‘Low’ voltage VIL –0.3 0.4 V Input ‘High’ voltage V IH 0.8 × VCC VCC + 0.3 V 0.4 V NOTE Output ‘Low’ voltage VOL I OL = 400 µA Output ‘High’ voltage VOH I OH = –100 µA Input leakage current | ILI | V IN = 0 V to VCC 10 µA Output leakage current | ILO | V OUT = 0 V to VCC 10 µA 1 2 0.8 × VCC V Operating current ICC t RC = 500 ns 18 mA Standby current ISB CE = VCC – 0.2 V 30 µA Input capacitance CIN f = 1 MHz T A = 25°C 10 pF 10 pF Output capacitance COUT NOTE: 1. CE/OE = VIH, OE = VIL 2. Outputs open AC CHARACTERISTICS (VCC = 2.6 V to 3.6 V, TA = 0°C to +70°C) PARAMETER SYMBOL MIN. 500 MAX. UNIT Read cycle time tRC Address access time tAA 500 ns Chip enable access time tACE 500 ns Output enable delay time tOE 200 ns Output hold time tOH CE to output in High-Z tCHZ OE to output in High-Z tOHZ NOTE ns 10 ns 150 ns 1 ns NOTE: 1. This is the time required for the output to become high-impedance. 3 LH531000B-S CMOS 1M MROM AC TEST CONDITIONS PARAMETER RATING Input voltage amplitude Input rise/fall time 0.4 V to (0.8 × VCC) V 10 ns Input/output reference level Output load condition 1.5 V 1TTL + 100 pF CAUTION To stabilize the power supply, it is recommended that a high-frequency bypass capacitor be connected between the VCC pin and the GND pin. tRC A0 - A16 tAA (NOTE) CE tACE tCHZ (NOTE) OE OE tOHZ tOE (NOTE) D0 - D 7 tOH DATA VALID NOTE: The output data becomes valid when the last intervals, tAA, tACE, or tOE, have concluded. Figure 3. Timing Diagram 4 531000BS-3 CMOS 1M MROM LH531000B-S PACKAGE DIAGRAM 28SOP (SOP028-P-0450) 0.50 [0.020] 0.30 [0.012] 1.27 [0.050] TYP. 1.70 [0.067] 28 15 8.80 [0.346] 8.40 [0.331] 1 12.40 [0.488] 11.60 [0.457] 10.60 [0.417] 14 1.70 [0.067] 0.20 [0.008] 0.10 [0.004] 18.20 [0.717] 17.80 [0.701] 0.15 [0.006] 1.025 [0.040] 2.40 [0.094] 2.00 [0.079] 0.20 [0.008] 0.00 [0.000] 1.025 [0.040] DIMENSIONS IN MM [INCHES] MAXIMUM LIMIT MINIMUM LIMIT 28SOP 28-pin, 450-mil SOP ORDERING INFORMATION LH531000B Device Type N Package -S Low-Voltage Operation 28-pin, 450-mil SOP (SOP028-P-0450) CMOS 1M (128K x 8) Mask-Programmable ROM Example: LH531000BN-S (CMOS 1M (128K x 8) Mask-Programmable ROM, Low-Voltage Operation, 28-pin, 450-mil SOP) 531000BS-4 5