4 Mbit ROM + 1 Mbit / 256 Kbit SRAM ROM/RAM Combo SST30VR041 / SST30VR043 Preliminary Specifications SST30VR041/0434 Mb Mask ROM (x8) + 1 Mb / 256 Kbit SRAM (x8) Combo FEATURES: • ROM + SRAM ROM/RAM Combo – SST30VR041: 512K x8 ROM + 128K x8 SRAM – SST30VR043: 512K x8 ROM + 32K x8 SRAM • ROM/RAM combo on a monolithic chip • Equivalent ComboMemory (Flash + SRAM): SST31LF041A for code development and pre-production • Wide Operating Voltage Range: 2.7-3.3V • Chip Access Time – SST30VR041 70 ns and 150 ns – SST30VR043 150 ns • Low Power Dissipation: – Standby: 1.0 µW (Typical) – Operating: 3.0 mW (Typical) • Fully Static Operation – No clock or refresh required • Three state Outputs • Packages Available – 32-pin TSOP (8mm x14mm) PRODUCT DESCRIPTION The SST30VR041/043 are ROM/RAM combo chips consisting of 4 Mbit Read Only Memory organized as 512 KBytes and a Static Random Access Memory organized as either 128 or 32 KBytes. Output Enable Input (OE#) is pin-shared with RAMCS# (RAM Enable Input) signal in order to maintain the standard 32-pin TSOP package. The device is fabricated using SST’s advanced CMOS low power process technology. The SST30VR041/043 have an output enable input for precise control of the data outputs. It also has two (2) separate chip enable inputs for selection of either RAM or ROM and for minimizing current drain during power-down mode. The SST30VR041/043 is particularly well suited for use in low voltage (2.7-3.3V) supplies such as pagers, organizers and other handheld applications. FUNCTIONAL BLOCK DIAGRAM WE# OE# WE# Address Buffer RAM DQ7-DQ0 ROMCS# OE# ROM AMS-A0 Note: AMS = Most Significant Address ©2001 Silicon Storage Technology, Inc. S71134-02-000 4/01 381 1 Data Buffer OE#/RAMCS# Control Circuit RAMCS# ROMCS# 381 ILL B1.2 The SST logo and SuperFlash are registered trademarks of Silicon Storage Technology, Inc. ComboMemory is a trademark of Silicon Storage Technology, Inc. These specifications are subject to change without notice. 4 Mbit ROM + 1 Mbit / 256 Kbit SRAM ROM/RAM Combo SST30VR041 / SST30VR043 Preliminary Specifications A11 A9 A8 A13 A14 A17 WE# VDD A18 A16 A15 A12 A7 A6 A5 A4 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Standard Pinout Top View Die Up OE#/RAMCS# A10 ROMCS# DQ7 DQ6 DQ5 DQ4 DQ3 VSS DQ2 DQ1 DQ0 A0 A1 A2 A3 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 381 ILL F01.0 FIGURE 1: PIN ASSIGNMENTS FOR 32-PIN TSOP TABLE 1: PIN DESCRIPTION Symbol Pin Name AMS1-A0 Address Inputs, for ROM: AMS = A18, for RAM: AMS =A16 for SST30VR041 A14 for SST30VR043 WE# Write Enable Input OE#/RAMCS# Output Enable/RAM Enable Input ROMCS# ROM Enable Input DQ7-DQ0 Data Input/Output VDD Power Supply VSS Ground T1.2 381 1. AMS = Most significant address ©2001 Silicon Storage Technology, Inc. S71134-02-000 4/01 2 381 4 Mbit ROM + 1 Mbit / 256 Kbit SRAM ROM/RAM Combo SST30VR041 / SST30VR043 Preliminary Specifications Absolute Maximum Stress Ratings (Applied conditions greater than those listed under “Absolute Maximum Stress Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these conditions or conditions greater than those defined in the operational sections of this data sheet is not implied. Exposure to absolute maximum stress rating conditions may affect device reliability.) Operating Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -20°C to +85°C Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65°C to +150°C Voltage on Any Pin Relative to VSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to VDD + 0.5V Voltage on VDD Supply Relative to VSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 4.0V Power Dissipation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.0W Soldering Temperature (10 Seconds Lead Only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C OPERATING RANGE Range Commercial Extended AC CONDITIONS OF Ambient Temp VDD 0°C to +70°C 2.7-3.3V -20°C to +85°C 2.7-3.3V TEST Input Pulse Level . . . . . . . . . . . . . . . . . . . . 0-VDD Input & Output Timing Reference Levels . . . VDD/2 Input Rise/Fall Time . . . . . . . . . . . . . . . . . . . 5 ns Output Load . . . . . . . . . . . . . . . . . . . . . . . . . CL = 30 pF for 70 ns Output Load . . . . . . . . . . . . . . . . . . . . . . . . . CL = 100 pF for 150 ns TABLE 2: RECOMMENDED DC OPERATING CONDITIONS Symbol Parameter Min Max Units VDD Supply Voltage 2.7 3.3 V VSS Ground 0 0 V VIH Input High Voltage 2.4 VDD + 0.5 V VIL Input Low Voltage -0.3 0.3 V T2.0 381 TABLE 3: DC OPERATING CHARACTERISTICS VDD = 3.0±0.3V Symbol Parameter Min Max Units Test Conditions mA ROMCS# = VIL, RAMCS# = VIH, VIN = VIH or VIL, II/O = Opens IDD1 ROM Operating Supply Current 4.0+1.1(f)1 IDD2 RAM Operating Supply Current 2.5+1(f)1 mA ROMCS# = VIH, RAMCS# = VIL, II/O = Opens ISB Standby VDD Current 10 µA ROMCS# ≥ VDD-0.2V, RAMCS# ≥ VDD-0.2V VIN ≥ VDD-0.2V or VIN ≤ 0.2V ILI Input Leakage Current -1 1 µA VIN = VSS to VDD ILO Output Leakage Current -1 1 µA ROMCS# = RAMCS# = VIH or OE# = VIH or WE# = VIL, VI/O = VSS to VDD VOL Output Low Voltage VOH Output High Voltage 0.4 2.2 V IOL = 1.0 mA V IOH = -0.5 mA T3.4 381 1. f = Frequency of operation (MHz) = 1/cycle time ©2001 Silicon Storage Technology, Inc. S71134-02-000 4/01 3 381 4 Mbit ROM + 1 Mbit / 256 Kbit SRAM ROM/RAM Combo SST30VR041 / SST30VR043 Preliminary Specifications TABLE 4: CAPACITANCE (Ta = 25°C, f=1 Mhz) Parameter Description Test Condition Maximum CI/O1 I/O Pin Capacitance VI/O = 0V 8 pF Input Capacitance VIN = 0V 6 pF CIN 1 T4.1 381 1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter. VIHT INPUT VIT REFERENCE POINTS VOT OUTPUT VILT 381 ILL F07.0 AC test inputs are driven at VIHT (0.9 VDD) for a logic “1” and VILT (0.1 VDD) for a logic “0”. Measurement reference points for inputs and outputs are VIT (0.5 VDD) and VOT (0.5 VDD). Input rise and fall times (10% ↔ 90%) are <5 ns. Note: VIT - VINPUT Test VOT - VOUTPUT Test VIHT - VINPUT HIGH Test VILT - VINPUT LOW Test FIGURE 2: AC INPUT/OUTPUT REFERENCE WAVEFORMS TO TESTER TO DUT CL 381 ILL F08.0 FIGURE 3: A TEST LOAD EXAMPLE ©2001 Silicon Storage Technology, Inc. S71134-02-000 4/01 4 381 4 Mbit ROM + 1 Mbit / 256 Kbit SRAM ROM/RAM Combo SST30VR041 / SST30VR043 Preliminary Specifications AC CHARACTERISTICS I. ROM Operation TABLE 5: READ CYCLE TIMING PARAMETERS VDD = 3.0V±0.3 SST30VR041-70 Min Max SST30VR041/043-150 Symbol Parameter Max Units TRC Read Cycle Time TAA Address Access Time 70 150 ns TCO TOE Chip Select to Output 70 150 ns Output Enable to Valid Output 35 70 ns TLZ Chip Select to Low-Z Output 0 0 ns TOLZ Output Enable to Low-Z Output 0 0 ns THZ Chip Disable to High-Z Output 25 30 ns TOHZ Output Disable to High-Z Output 25 30 ns TOH Output Hold from Address Change 70 Min 150 10 ns 15 ns T5.2 381 TRC Address TAA TOH Data Out Previous Data Valid Data Valid 381 ILL F02.0 FIGURE 4: ROM READ CYCLE TIMING DIAGRAM (ADDRESS CONTROLLED) (ROMCS# = OE# = VIL) ©2001 Silicon Storage Technology, Inc. S71134-02-000 4/01 5 381 4 Mbit ROM + 1 Mbit / 256 Kbit SRAM ROM/RAM Combo SST30VR041 / SST30VR043 Preliminary Specifications TRC Address THZ(1,2) TAA TCO ROMCS# TLZ(2) TOHZ(1) TOE OE# TOLZ TOH High-Z Data Valid Data Out 381 ILL F03.0 Notes: 1. THZ and TOHZ are defined as the time at which the outputs achieve the open circuit condition and are referenced to the VOH or VOL. 2. At any given temperature and voltage condition THZ(max) is less than TLZ(min) both for a given device and from device to device. FIGURE 5: ROM READ CYCLE TIMING DIAGRAM (ROMCS# & OE# CONTROLLED) II. SRAM Operation (ROMCS# = VIH) TABLE 6: READ CYCLE TIMING PARAMETERS VDD = 3.0V±0.3 SST30VR041-70 Min Max SST30VR041/043-150 Symbol Parameter TRC Read Cycle Time TAA Address Access Time 70 150 ns TCO Chip Select to Output 70 150 ns TLZ Chip Select to Low-Z Output THZ Chip Disable to High-Z Output 30 ns TOH Output Hold from Address Change 70 Min Max 150 0 ns 0 25 10 Units ns 15 ns T6.2 381 TABLE 7: WRITE CYCLE TIMING PARAMETERS VDD = 3.0V±0.3 SST30VR041-70 Min Max SST30VR041/043-150 Symbol Parameter TWC Write Cycle Time 70 Min 150 Max ns TCW Chip Select to End-of-Write 60 120 ns TAW Address Valid to End-of-Write 60 120 ns TAS Address Set-up Time 0 0 ns TWP Write Pulse Width 60 120 ns TWR Write Recovery Time 0 TWHZ Write to Output High-Z TDW Data to Write Time Overlap 30 60 ns TDH Data Hold from Write Time 0 0 ns TOW End Write to Output Low-Z 0 10 0 30 Units ns 60 ns ns T7.2 381 ©2001 Silicon Storage Technology, Inc. S71134-02-000 4/01 6 381 4 Mbit ROM + 1 Mbit / 256 Kbit SRAM ROM/RAM Combo SST30VR041 / SST30VR043 Preliminary Specifications TRC Address TAA TOH Data Out Previous Data Valid Data Valid 381 ILL F04.0 FIGURE 6: SRAM READ CYCLE TIMING DIAGRAM (ADDRESS CONTROLLED) (OE#/RAMCS# = VIL, WE# = VIH) TRC Address THZ(1,2) TAA TCO OE#/RAMCS# TLZ(2) TOH High-Z Data Valid Data Out Notes: 1. THZ and TOHZ are defined as the time at which the outputs achieve the open circuit condition and are referenced to the VOH or VOL. 2. At any given temperature and voltage condition THZ(max) is less than TLZ(min) both for a given device and from device to device. 3. WE# is high for Read cycle. 381 ILL F05.0 FIGURE 7: SRAM READ CYCLE TIMING DIAGRAM (OE#/RAMCS# CONTROLLED) ©2001 Silicon Storage Technology, Inc. S71134-02-000 4/01 7 381 4 Mbit ROM + 1 Mbit / 256 Kbit SRAM ROM/RAM Combo SST30VR041 / SST30VR043 Preliminary Specifications TWC Address TWR(4) TAW TCW(2) OE#/RAMCS# TAS(3) TWP(1) TOH WE# TDH TDW High-Z Data Valid Data In TOW TWHZ(5) (7) High-Z (6) Data Out (8) 381 ILL F06.0 Notes: 1. A write occurs during the overlap (TWP) of a low RAMCS# and low WE#. A write begins at the latest transition among RAMCS# going low and WE# going low: A write end at the earliest transition among RAMCS# going high and WE# going high, TWP is measured from the beginning of write to the end of write. 2. TCW is measured from the later of RAMCS# going low to the end of write. 3. TAS is measured from the address valid to the beginning of write. 4. TWR is measured from the end of write to the address change. 5. If RAMCS#, WE# are in the read mode during this period, the I/O pins are in the outputs Low-Z state. Inputs of opposite phase of the output must not be applied because bus contention can occur. 6. If RAMCS# goes low simultaneously with WE# going low or after WE# going low, the outputs remain high impedance state. 7. DOUT is the same phase of the latest written data in this write cycle. 8. DOUT is the read data of new address 9. ROMCS# = VIH FIGURE 8: SRAM WRITE CYCLE TIMING DIAGRAM TABLE 8: FUNCTIONAL DESCRIPTION/TRUTH TABLE OE#/RAMCS#1 (Pin 32) WE# DQ7-DQ0 H H X Z Standby L OE# (H) X Z Output Floating Address Inputs ROMCS# X2 AMS3-A0 AMS3-A0 L OE# (L) X DOUT ROM Read Only AMS4-A0 are valid H RAMCS# (L) H DOUT RAM Read H RAMCS# (L) L DIN RAM Write Only AMS4-A0 are valid T8.3 381 1. 2. 3. 4. OE# & RAMCS# are pin-shared X means Don’t Care. For ROM: AMS = A18 for SST30VR041 and SST30VR043 For RAM: AMS = A16 for SST30VR041, A18-A17 must be fixed to “L” or “H” AMS = A14 for SST30VR043, A18-A15 must be fixed to “L” or “H” ©2001 Silicon Storage Technology, Inc. S71134-02-000 4/01 8 381 4 Mbit ROM + 1 Mbit / 256 Kbit SRAM ROM/RAM Combo SST30VR041 / SST30VR043 Preliminary Specifications Device Speed SST30VR0xx - XXX Suffix1 - X Suffix2 - XX - RXXXX C-Spec Number Package Modifier H = 32 leads Numeric = Die modifier Package Type W = TSOP (8mm x 14mm) U = Die only Temperature Range C = Commercial = 0°C to +70°C E = Extended = -20°C to +85°C Read Access Speed 70 = 70 ns 150 = 150 ns Device Density 041 = 4 Mbit ROM + 1 Mbit SRAM 043 = 4 Mbit ROM + 256 Kbit SRAM Voltage Range V = 2.7-3.3V Device Family 30 = ROM/RAM Combo SST30VR041 Valid combinations SST30VR041-70-C-WH SST30VR041-150-C-WH SST30VR041-70-C-U1 SST30VR041-150-C-U1 SST30VR041-70-E-WH SST30VR041-150-E-WH SST30VR043 Valid combinations SST30VR043-150-C-WH SST30VR043-150-C-U1 SST30VR043-150-E-WH Example: Valid combinations are those products in mass production or will be in mass production. Consult your SST sales representative to confirm availability of valid combinations and to determine availability of new combinations. ©2001 Silicon Storage Technology, Inc. S71134-02-000 4/01 9 381 4 Mbit ROM + 1 Mbit / 256 Kbit SRAM ROM/RAM Combo SST30VR041 / SST30VR043 Preliminary Specifications PACKAGING DIAGRAMS 1.05 0.95 Pin # 1 Identifier .50 BSC .270 .170 8.10 7.90 0.15 0.05 12.50 12.30 0.70 0.50 14.20 13.80 32.TSOP-WH-ILL.4 Note: 1. Complies with JEDEC publication 95 MO-142 BA dimensions, although some dimensions may be more stringent. 2. All linear dimensions are in millimeters (min/max). 3. Coplanarity: 0.1 (±.05) mm. 4. Maximum allowable mold flash is 0.15mm at the package ends, and 0.25mm between leads. 32-PIN THIN SMALL OUTLINE PACKAGE (TSOP) 8MM SST PACKAGE CODE: WH X 14MM Silicon Storage Technology, Inc. • 1171 Sonora Court • Sunnyvale, CA 94086 • Telephone 408-735-9110 • Fax 408-735-9036 www.SuperFlash.com or www.ssti.com ©2001 Silicon Storage Technology, Inc. S71134-02-000 4/01 10 381