ETC AM79M574-JC

Am79M574
Metering Subscriber Line Interface Circuit
DISTINCTIVE CHARACTERISTICS
Programmable constant-resistance feed
Programmable loop-detect threshold
Ground-key detect
Performs polarity reversal
Line-feed characteristics independent of
battery variations
Test relay driver optional
Supports 2.2 Vrms metering (12 and 16 kHz)
On-chip switching regulator for low-power
dissipation
Two-wire impedance set by single external
impedance
Tip Open state for ground-start lines
On-hook transmission
BLOCK DIAGRAM
A(TIP)
Ring Relay Driver
RINGOUT
Test Relay Driver
TESTOUT
Ground-Key
Detector
HPA
Input Decoder
and Control
Two-Wire
Interface
C1
C2
C3
C4
E1
E0
DET
HPB
VTX
RSN
Signal Transmission
Off-Hook Detector
B(RING)
DA
DB
VREG
L
VBAT
RD
RDC
Power-Feed
Controller
Ring-Trip Detector
Switching Regulator
BGND
CHS
QBAT
CHCLK
VCC
VEE
AGND
16857C-001
Notes:
1. Am79M574—E0 and E1 inputs; ring and test relay drivers sourced internally to BGND.
2. Current gain (K1) = 1000.
Publication# 080135 Rev: E Amendment: /0
Issue Date: October 1999
ORDERING INFORMATION
Standard Products
Legerity standard products are available in several packages and operating ranges. The order number (Valid Combination) is
formed by a combination of the elements below.
Am79M574
J
C
TEMPERATURE RANGE
C = Commercial (0°C to 70°C)*
PACKAGE TYPE
J = 32-Pin Plastic Leaded Chip Carrier (PL 032)
PERFORMANCE GRADE
Blank = Standard Specification
–1 = Performance Grading
–2 = Performance Grading
DEVICE NAME/DESCRIPTION
Am79M574
Subscriber Line Interface Circuit
Valid Combinations
Valid Combinations
Am79M574
–1
–2
JC
Valid Combinations list configurations planned to
be supported in volume for this device. Consult
the local Legerity sales office to confirm availability of specific valid combinations, to check on
newly released combinations, and to obtain additional data on Legerity’s standard military grade
products.
Note:
* Functionality of the device from 0°C to +70°C is guaranteed by production testing. Performance from –40°C to +85°C is
guaranteed by characterization and periodic sampling of production units.
2
Am79M574 Data Sheet
RINGOUT
VCC
VREG
BGND
B(RING)
A(TIP)
DB
4
3
2
1
32
31
30
CONNECTION DIAGRAM
Top View
26
HPB
QBAT
9
25
HPA
CHS
10
24
VTX
CHCLK
11
23
VEE
C4
12
22
RSN
E1
13
21
AGND
20
8
DGND
VBAT
19
RD
RDC
27
18
7
C1
L
17
DA
C3
28
16
6
C2
TESTOUT
15
TP
DET
29
14
5
E0
TP
Notes:
1. Pin 1 is marked for orientation.
2. TP is a thermal conduction pin tied to substrate (QBAT).
3. NC = No connect
SLIC Products
3
PIN DESCRIPTIONS
Pin Names
4
Type
Description
AGND
Gnd
Analog (quiet) ground
A(TIP)
Output
Output of A(TIP) power amplifier
BGND
Gnd
Battery (power) ground
B(RING)
Output
Output of B(RING) power amplifier
C3–C1
Input
Decoder. TTL compatible. C3 is MSB and C1 is LSB.
C4
Input
Test relay driver command. TTL compatible. A logic Low enables the driver.
CHCLK
Input
Chopper clock. Input to switching regulator (TTL compatible). Frequency = 256 kHz (Nominal).
CHS
Input
Chopper Stabilization. Connection for external stabilization components.
DA
Input
Ring-trip negative. Negative input to ring-trip comparator.
DB
Input
Ring-trip positive. Positive input to ring-trip comparator.
DET
Output
Detector. When enabled, a logic Low indicates that the selected detector is tripped. Logic inputs
C3–C1, E1, and E0 select the detector. Open-collector with a built-in 15 kΩ pull-up resistor.
DGND
Gnd
Digital ground
E0
Input
Read Enable. A logic High enables DET. A logic Low disables DET.
E1
Input
Ground enable. When E0 is High, E1 = High connects the ground-key detector to DET, and
E1 = Low connects the off-hook or ring-trip detector to DET.
HPA
Capacitor
High-pass filter capacitor. A(TIP) side of high-pass filter capacitor.
HPB
Capacitor
High-pass filter capacitor. B(RING) side of high-pass filter capacitor.
L
Output
Switching Regulator Power Transistor. Connection point for filter inductor and anode of catch
diode. Has up to 60 V of pulse waveform and must be isolated from sensitive circuits. Keep the
diode connections short because of the high currents and high di/dt.
QBAT
Battery
Quiet Battery. Filtered battery supply for the signal processing circuits.
RD
Resistor
Detector resistor. Threshold modification and filter point for the off-hook detector.
RDC
Resistor
DC feed resistor. Connection point for the DC feed resistance programming network, which
also connects to the Receiver Summing Node (RSN). VRDC is negative for normal polarity and
positive for reverse polarity.
RINGOUT
Output
Ring relay driver. Sourcing from BGND with internal diode to QBAT.
RSN
Input
Receive Summing Node. The metallic current (AC and DC) between A(TIP) and B(RING) =
1000 x the current into this pin. The networks that program receive gain, two-wire
impedance, and feed resistance all connect to this node. This node is extremely sensitive.
Route the 256 kHz chopper clock and switch lines away from the RSN node.
TESTOUT
Output
Test relay driver. Sourcing from BGND with internal diode to QBAT.
TP
Thermal
Thermal pin. Connection for heat dissipation. Internally connected to substrate (QBAT). Leave
as open circuit or connected to QBAT. In both cases, the TP pins can connect to an area of
copper on the board to enhance heat dissipation.
VBAT
Battery
Battery supply. Connected to office battery supply through an external protection diode.
VCC
Power
+5 V power supply
VEE
Power
–5 V power supply
VREG
Input
Regulated Voltage. Provides negative power supply for power amplifiers, connection point for
inductor, filter capacitor, and chopper stabilization.
VTX
Output
Transmit Audio.This output is 0.510 times the A(TIP) and B(RING) metallic voltage. The other
end of the two-wire input impedance programming network connects here.
Am79M574 Data Sheet
ABSOLUTE MAXIMUM RATINGS
OPERATING RANGES
Storage temperature . . . . . . . . . . . . –55°C to +150°C
Commercial (C) Devices
VCC with respect to AGND/DGND . . .–0.4 V to +7.0 V
Ambient temperature . . . . . . . . . . . . . . .0°C to +70°C
VEE with respect to AGND/DGND . . .+0.4 V to –7.0 V
VCC . . . . . . . . . . . . . . . . . . . . . . . . . . 4.75 V to 5.25 V
VBAT with respect to AGND/DGND . . . +0.4 V to –70 V
VEE . . . . . . . . . . . . . . . . . . . . . . . . –4.75 V to –5.25 V
Note: Rise time of VBAT (dv/dt) must be limited to 27 V/µs
or less when QBAT bypass = 0.33 µF.
VBAT . . . . . . . . . . . . . . . . . . . . . . . . . . . –40 V to –58 V
BGND with respect to
AGND/DGND. . . . . . . . . . . . . . . .+1.0 V to –3.0 V
A(TIP) or B(RING) to BGND:
Continuous . . . . . . . . . . . . . . . . . –70 V to +1.0 V
10 ms (f = 0.1 Hz) . . . . . . . . . . . . –70 V to +5.0 V
1 µs (f = 0.1 Hz). . . . . . . . . . . . . . . –90 V to +10 V
250 ns (f = 0.1 Hz) . . . . . . . . . . . .–120 V to +15 V
Current from A(TIP) or B(RING) . . . . . . . . . . . .±150 mA
Voltage on RINGOUT. . . . .BGND to 70 V above QBAT
Voltage on TESTOUT. . . . .BGND to 70 V above QBAT
AGND/DGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 V
BGND with respect to
AGND/DGND . . . . . . . . . . . –100 mV to +100 mV
Load resistance on VTX to ground . . . . . . . 10 kΩ min
Operating Ranges define those limits between which the
functionality of the device is guaranteed.
* Functionality of the device from 0°C to +70°C is guaranteed
by production testing. Performance from –40°C to +85°C is
guaranteed by characterization and periodic sampling of
production units.
Current through relay drivers . . . . . . . . . . . . . . 60 mA
Voltage on ring-trip inputs
(DA and DB) . . . . . . . . . . . . . . . . . . . . VBAT to 0 V
Current into ring-trip inputs . . . . . . . . . . . . . . . . .±10 mA
Peak current into regulator
switch (L pin) . . . . . . . . . . . . . . . . . . . . . . 150 mA
Switcher transient peak off
voltage on L pin . . . . . . . . . . . . . . . . . . . . . +1.0 V
C4–C1, E0, E1, CHCLK to
AGND/DGND. . . . . . . . . . . .–0.4 V to VCC + 0.4 V
Maximum power dissipation, (see note). . . .TA = 70°C
In 32-pin PLCC package . . . . . . . . . . . . . . 1.74 W
Note: Thermal limiting circuitry on chip will shut down the
circuit at a junction temperature of about 165°C. The device should never be exposed to this temperature. Operation above 145°C junction temperature may degrade
device reliability. See the SLIC Packaging Considerations
for more information.
Stresses above those listed under Absolute Maximum Ratings
may cause permanent device failure. Functionality at or above
these limits is not implied. Exposure to Absolute Maximum
Ratings for extended periods may affect device reliability.
SLIC Products
5
ELECTRICAL CHARACTERISTICS
Description
Test Conditions (See Note 1)
Min
Analog (VTX) output impedance
Analog (VTX) output offset
Max
0°C to +70°C
–40°C to +85°C
–1
–35
–30
–40
–35
Analog (RSN) input impedance 300 Hz to 3.4 kHz
Longitudinal impedance at A or B
–3.1
–6.0
Note
+35
+30
+40
+35
mV
—
—
4
4
20
35
Ω
4
—
+3.1
+6.0
Vpk
—
2
dB
4, 14
dB
—
—
4
—
1
4-wire
2-wire
Unit
Ω
3
–1*
Overload level
Z2WIN = 600 Ω to 900 Ω
Typ
Transmission Performance, 2-Wire Impedance
2-wire return loss
(See Test Circuit D)
300 Hz to 500 Hz
500 Hz to 2500 Hz
2500 Hz to 3400 Hz
26
26
20
Longitudinal Balance (2-Wire and 4-Wire, See Test Circuit C)
RL = 600 Ω, longitudinal to
metallic L-T, L-4 (normalized to
unity gain)
300 Hz to 3400 Hz
–1*
48
52
Longitudinal to metallic L-T, L-4
200 Hz to 1 kHz
normal polarity
0°C to +70°C
normal polarity –40°C to +85°C
reverse polarity
–2*
–2
–2
63
58
54
1 kHz to 3.4 kHz
normal polarity
0°C to +70°C
normal polarity –40°C to +85°C
reverse polarity
–2*
–2
–2
58
54
54
Longitudinal signal
generation 4-L
300 Hz to 800 Hz
300 Hz to 800 Hz
–1*
40
42
Longitudinal current capability
per wire
Active state
OHT state
—
—
4
—
25
18
mArms
4
Insertion Loss (2- to 4-Wire and 4- to 2-Wire, See Test Circuits A and B)
Gain accuracy 2- to 4-wire
2- to 4-wire
2- to 4-wire
2- to 4-wire
0 dBm, 1 kHz,
0°C to +70°C
0 dBm, 1 kHz, –40°C to +85°C
0 dBm, 1 kHz,
0°C to +70°C
0 dBm, 1 kHz, –40°C to +85°C
4- to 2-wire
4- to 2-wire
4- to 2-wire
4- to 2-wire
0 dBm, 1 kHz,
0°C to +70°C
0 dBm, 1 kHz, –40°C to +85°C
0 dBm, 1 kHz,
0°C to +70°C
0 dBm, 1 kHz, –40°C to +85°C
Variation with frequency
Gain tracking
–1*
–1
5.75
5.65
5.75
5.70
–1*
–1
–0.15
–0.20
–0.1
–0.15
5.85
5.85
5.85
5.85
6.00
6.05
5.95
6.00
—
4
—
4
+0.15
+0.20
+0.1
+0.15
—
4
—
4
300 Hz to 3400 Hz
Relative to 1 kHz
0°C to +70°C
–40°C to +85°C
–0.1
–0.15
+0.1
+0.15
—
—
—
4
+7 dBm to –55 dBm, ref 0 dBm
0°C to +70°C
–40°C to +85°C
–0.1
–0.15
+0.1
+0.15
—
4
4
Notes:
* P.G. = Performance Grade
–2 grade performance parameters are equivalent to –1 performance parameters except where indicated.
6
dB
Am79M574 Data Sheet
ELECTRICAL CHARACTERISTICS (continued)
Description
Test Conditions (See Note 1)
Min
Typ
Max
–6.00
–6.05
–5.95
–6.00
–5.85
–5.85
–5.85
–5.85
–5.75
–5.65
–5.75
–5.70
Unit
Note
Balance Return Signal (4- to 4-Wire, See Test Circuit B)
Gain accuracy
Variation with frequency
Gain tracking
Group delay
0 dBm, 1 kHz,
0°C to +70°C
0 dBm, 1 kHz, –40°C to +85°C
0 dBm, 1 kHz,
0°C to +70°C
0 dBm, 1 kHz, –40°C to +85°C
–1*
–1
3
3, 4
3
3, 4
300 Hz to 3400 Hz
Relative to 1 kHz
0°C to +70°C
–40°C to +85°C
–0.1
–0.15
+0.1
+0.15
—
—
3, 4
3, 4
+7 dBm to –55 dBm, ref 0 dBm
0°C to +70°C
–40°C to +85°C
–0.1
–0.15
+0.1
+0.15
—
4
4
dB
f = 1 kHz
µs
5.3
4, 15
Total Harmonic Distortion (2- to 4-Wire or 4- to 2-Wire, See Test Circuits A and B)
Total harmonic distortion
0 dBm, 300 Hz to 3.4 kHz
+9 dBm, 300 Hz to 3.4 kHz
–64
–55
–50
–40
dB
Total harmonic distortion
with metering
–35
4, 11
Idle Channel Noise
C-message weighted noise
2-wire, 0°C to +70°C
2-wire, 0°C to +70°C
2-wire, –40°C to +85°C
–1*
+7
+7
+7
+15
+12
+15
4-wire, 0°C to +70°C
4-wire, 0°C to +70°C
4-wire, –40°C to +85°C
–1*
+7
+7
+7
+15
+12
+15
2-wire, 0°C to +70°C
2-wire, 0°C to +70°C
2-wire, –40°C to +85°C
–1*
–83
–83
–83
–75
–78
–75
–1*
–83
–83
–83
–75
–78
–75
dBrnC
Psophometric weighted noise
4
7
7
4, 7
dBmp
4-wire, 0°C to +70°C
4-wire, 0°C to +70°C
4-wire, –40°C to +85°C
7
7
4, 7
Single Frequency Out-of-Band Noise (See Test Circuit E)
Metallic
4 kHz to 9 kHz
9 kHz to 1 MHz
256 kHz and harmonics
–76
–76
–57
Longitudinal
1 kHz to 15 kHz
Above 15 kHz
256 kHz and harmonics
–70
–85
–57
4, 5, 9
4, 5, 9
4, 5
dBm
4, 5, 9
4, 5, 9
4, 5
Line Characteristics (See Figure 1) BAT = –48 V, RL = 600 Ω and 900 Ω, RFEED = 800 Ω
Apparent battery voltage
Active state
47
Loop-current accuracy
Active state
–7.5
Loop current—Tip Open state
RL = 600 Ω
50
53
V
+7.5
1.0
Loop current—Open Circuit state RL = 0 Ω
1.0
Loop-current limit accuracy
OHT state
Active state
Fault current limit, ILLIM
(IAX + IBX)
A and B shorted to GND
–20
SLIC Products
%
+20
130
10
mA
7
ELECTRICAL CHARACTERISTICS (continued)
Description
Test Conditions (See Note 1)
Min
Typ
Max
–1*
35
35
120
80
–1*
135
135
250
200
–1*
200
200
400
300
Unit
Note
Power Dissipation BAT = –48 V, Normal Polarity
On-hook Open Circuit state
On-hook OHT state
On-hook Active state
Off-hook OHT state
RL = 600 Ω
500
750
Off-hook Active state
RL = 600 Ω
650
1000
VCC On-hook supply current
Open Circuit state
OHT state
Active state
3.0
6.0
7.5
4.5
10.0
12.0
VEE On-hook supply current
Open Circuit state
OHT state
Active state
1.0
2.2
2.7
2.3
3.5
6.0
Open Circuit state
OHT state
Active state
0.4
3.0
4.0
1.0
5.0
6.0
mW
Supply Currents
VBAT On-hook supply current
mA
Power Supply Rejection Ratio (VRIPPLE = 50 mVrms)
VCC
50 Hz to 3400 Hz
–1*
25
30
45
45
–1*
22
25
35
35
–1*
20
25
40
40
–1*
10
10
25
25
–1*
27
30
45
45
–1*
20
25
40
40
6, 7
3.4 kHz to 50 kHz
VEE
50 Hz to 3400 Hz
dB
3.4 kHz to 50 kHz
VBAT
50 Hz to 3400 Hz
6, 7
6, 7
3.4 kHz to 50 kHz
Off-Hook Detector
Current threshold accuracy
IDET = 365/RD Nominal
–20
+20
%
10.0
kΩ
Ground-Key Detector Thresholds, Active State, BAT = –48 V (See Test Circuit F)
Ground-key resistance threshold B(RING) to GND
Ground-key current threshold
2.0
B(RING) to GND
Midpoint to GND
5.0
9
9
mA
–5
–0.05
µA
–50
0
8
Ring-Trip Detector Input
Bias current
Offset voltage
8
Source resistance 0 to 2 MΩ
Am79M574 Data Sheet
+50
mV
13
ELECTRICAL CHARACTERISTICS (continued)
Description
Test Conditions (See Note 1)
Min
Typ
Max
Unit
Note
Logic Inputs (C4–C1, E0, E1, and CHCLK)
Input High voltage
2.0
V
Input Low voltage
0.8
Input High current
All inputs except E1
–75
40
Input High current
Input E1
–75
45
Input Low current
–0.4
µA
mA
Logic Output (DET)
Output Low voltage
IOUT = 0.8 mA
Output High voltage
IOUT = –0.1 mA
0.4
V
2.4
Relay Driver Outputs (RINGOUT, TESTOUT)
On voltage
50 mA source
BGND –2 BGND –0.95
Off leakage
0.5
Clamp voltage
50 mA sink
QBAT –2
V
100
µA
V
RELAY DRIVER SCHEMATICS
BGND
BGND
TESTOUT
RINGOUT
QBAT
QBAT
16857C-002
SLIC Products
9
SWITCHING CHARACTERISTICS
Symbol
Parameter
Test Conditions
E1 Low to DET High (E0 = 1)
Temperature
Range
Min
Typ
Max
0°C to +70°C
–40°C to +85°C
3.8
4.0
0°C to +70°C
–40°C to +85°C
1.1
1.6
0°C to +70°C
–40°C to +85°C
1.1
1.6
Unit
Note
µs
4
tgkde
E1 Low to DET Low (E0 = 1)
Ground-Key Detect state
RL open, RG connected
(See Figure H)
tgkdd
E0 High to DET Low (E1 = 0)
tgkd0
E0 Low to DET High (E1 = 0)
0°C to +70°C
–40°C to +85°C
3.8
4.0
E1 High to DET Low (E0 = 1)
0°C to +70°C
–40°C to +85°C
1.2
1.7
0°C to +70°C
–40°C to +85°C
3.8
4.0
0°C to +70°C
–40°C to +85°C
1.1
1.6
0°C to +70°C
–40°C to +85°C
3.8
4.0
tshde
E1 High to DET High (E0 = 1)
tshdd
E0 High to DET Low (E1 = 1)
tshd0
E0 Low to DET High (E1 = 1)
Switchhook Detect state
RL = 600 Ω, RG open
(See Figure G)
SWITCHING WAVEFORMS
E1 to DET
E1
DET
tgkde
tshde
tgkde
tshde
E0 to DET
E1
E0
DET
tshdd
tshd0
Note:
All delays measured at 1.4 V level.
10
tgkdd
tgkd0
16857C-003
Am79M574 Data Sheet
Notes:
1. Unless otherwise noted, test conditions are BAT = –48 V, VCC = +5 V, VEE = –5 V, RL = 600 Ω, CHP = 0.22 µF,
RDC1 = RDC2 = 20 kΩ, CDC = 0.1 µF, Rd = 51.1 kΩ, no fuse resistors, two-wire AC output impedance, programming impedance
(ZT) = 306 kΩ resistive, receive input summing impedance (ZRX) = 300 kΩ resistive. (See Table 2 for
component formulas.)
2. Overload level is defined when THD = 1%.
3. Balance return signal is the signal generated at VTX by VRX. This specification assumes that the two-wire AC load impedance
matches the impedance programmed by ZT.
4. Not tested in production. This parameter is guaranteed by characterization or correlation to other tests.
5. These tests are performed with a longitudinal impedance of 90 Ω and metallic impedance of 300 Ω for frequencies below
12 kHz and 135 Ω for frequencies greater than 12 kHz. These tests are extremely sensitive to circuit board layout.
6. This parameter is tested at 1 kHz in production. Performance at other frequencies is guaranteed by characterization.
7. When the SLIC is in the Anti-sat 2 operating region, this parameter is degraded. The exact degradation depends on system
design. The Anti-sat 2 region occurs at high loop resistances whenVBAT–VAX – VBX is less than approximately 17V.
8. "Midpoint" is defined as the connection point between two 300 Ω series resistors connected between A(TIP) and B(RING).
9. Fundamental and harmonics from 256 kHz switch-regulator chopper are not included.
10. Loop-current limit which depends upon the programmed apparent open circuit voltage and the feed resistance is calculated
as follows:
In OHT state:
V apparent
-------------------R FEED
I LIMIT = 0.5
In Active state:
I LIMIT = 0.8
V apparent
-------------------R FEED
11. Total harmonic distortion with metering as specified with a metering signal of 2.2 Vrms at the two-wire output, and a transmit
signal of +3 dBm or receive signal of –4 dBm. The transmit or receive signals are single-frequency inputs, and the distortion
is measured as the highest in-band harmonic at the two-wire or the four-wire output relative to the input signal.
12. Noise with metering is measured by applying a 2.2 Vrms metering signal (measured at the two-wire output) and measuring
the psophometric noise at the two-wire and four-wire outputs over a 200 ms time interval.
13. Tested with 0 Ω source impedance. 2 MΩ is specified for system design purposes only.
14. Assumes the following ZT network:
RSN
VTX
153 kΩ
153 kΩ
56 pF
15. Group delay can be considerably reduced by using a ZT network such as that shown in Note 14. The network reduces the
group delay to less than 2 µs. The effect of group delay on linecard performance may be compensated for by using the
QSLAC™ or DSLAC™ devices.
Table 1. SLIC Decoding
DET Output
State
C3 C2 C1
Two-Wire Status
E0 = 1*
E1 = 0
E0 = 1*
E1 = 1
0
0
0
0
Open Circuit
Ring trip
Ring trip
1
0
0
1
Ringing
Ring trip
Ring trip
2
0
1
0
Active
Loop detector
Ground key
3
0
1
1
On-hook TX (OHT)
Loop detector
Ground key
4
1
0
0
Tip Open
Loop detector
—
5
1
0
1
Reserved
Loop detector
—
6
1
1
0
Active Polarity Reversal
Loop detector
Ground key
7
1
1
1
OHT Polarity Reversal
Loop detector
Ground key
Note:
* Logic Low on E0 disables the DET output into the open-collector state.
SLIC Products
11
Table 2.
User-Programmable Components
Z T = 510 ( Z 2WIN – 2R F )
ZT is connected between the VTX and RSN pins. The fuse
resistors are RF, and Z2WIN is the desired 2-wire AC input
impedance. When computing ZT, the internal current amplifier
pole and any external stray capacitance between VTX and
RSN must be taken into account.
ZL
1000 • ZT
- • ------------------------------------------------Z RX = ---------G 42L Z T + 510 ( Z L + 2R F )
ZRX is connected from VRX to the RSN pin, ZT is defined
above, and G42L is the desired receive gain.
R DCI + R DC2 = 50 ( R FEED – 2R F )
RDC1, RDC2, and CDC form the network connected to the
RDC pin. RDC1 and RDC2 are approximately equal.
R DC1 + R DC2
C DC = 1.5 ms • ------------------------------R DC1 • R DC2
365
0.5 ms
R D = ---------, C D = ----------------IT
RD
RD and CD form the network connected from RD to –5 V and
IT is the threshold current between on-hook and off-hook.
V MG
K1 ( ω ) ZL • ZT
- • -----------------------------------------------------------------------Z M = -------------V M2W Z T + 0.51 • K 1 ( ω ) ( 2R F + Z L )
ZM is connected from VMG (metering source) to the RSN pin,
VM2W is the desired magnitude of the metering signal at the
2-wire output (usually 2.2 Vrms) and K1 ( ω ) is defined below.
1000
K 1 ( ω ) = --------------------------------------------------------------------------------------------------------------–9
1 + jω ( 11.5 • 10 + CX ⁄ 2 ) ( 36 + Z L + 2R F )
where: CX = The values of the identical capacitors
from A and B to GND
ω = 2 π • metering frequency
12
Am79M574 Data Sheet
DC FEED CHARACTERISTICS
6
3
5
4
2
1
7
Active state
VBAT = 47.3 V
RDC = 40 kΩ
OHT state
Notes:
R DC
1. Constant-resistance region: V
AB = 50 – I L ----------
50
2. Anti-sat–1 turn-on:
V AB = 28.48 V
3. Anti-sat–2 turn-on:
V AB = 0.992 V BAT – 13.8
4. Open Circuit voltage:
V AB = 0.44 V BAT + 15.89,
V BAT < 52.2 V (Anti-sat –2)
V AB = 38.85 V,
V BAT ≥ 52.2 V (Anti-sat –1)
5. Anti-sat –1 region:
R DC
V AB = 38.85 – IL ------------101.3
6. Anti-sat –2 region:
R DC
V AB = 0.44 V BAT + 15.89 – IL ------------173.9
7. Current limit:
1992
I L = -----------R DC
a. VA–VB (VAB) Voltage vs. Loop Current (Typical)
SLIC Products
13
DC FEED CHARACTERISTICS (continued)
VBAT = 47.3 V
RDC = 40 kΩ
b. Loop Current vs. Load Resistance (Typical)
A
a
IL
RL
RSN
SLIC
RDC1
b
RDC2
B
RDC
Feed resistance programmed by RDC1 and RDC2
c. Feed Programming
Figure 1.
14
CDC
DC Feed Characteristics
Am79M574 Data Sheet
16857C-004
TEST CIRCUITS
RL
2
A(TIP)
VTX
A(TIP)
SLIC
AGND
VAB
VL
RT
RT
SLIC
VAB
RL
2
VTX
RTMG
VMG
AGND
RL
RRX
B(RING)
RRX
RSN
B(RING)
RSN
VRX
IL4-2 = –20 log (VAB / VRX)
IL2-4 = –20 log (VTX / VAB)
BRS = 20 log (VTX / VRX)
B. Four- to Two-Wire Insertion Loss and Balance Return Signal
A. Two- to Four-Wire Insertion Loss
RL
2
A(TIP)
1/ωC << RL
VTX
S1 Closed, S2 Open
L-T Long. Bal. = –20 log (VAB / VL)
RT
SLIC
L-4 Long. Bal. = –20 log (VTX / GTX • VL)
C
S1
AGND
VL
S2 Closed, S1 Open:
VL
S2
B(RING)
RRX
4-L Long. Sig. Gen. = –20 log (VL / VRX)
RSN
RL
2
VRX
C. Longitudinal Balance
ZD
A(TIP)
VTX
R
RT
VM
VS
Note:
ZD is the desired impedance (i.e., the characteristic impedance of the line).
SLIC
R
RL = 20 log (2 VM / VS)
B(RING) RSN
ZIN
RRX
D. Two-Wire Return Loss Test Circuit
SLIC Products
15
TEST CIRCUITS (continued)
RL
68 Ω
A(TIP)
C
A(TIP)
1/ωC << 90 Ω
SM
56 Ω
RL
IDC
B(RING)
SLIC
68 Ω
RG
C
SE
B(RING)
Current Feed and Ground Key
F. Ground-Key Detection
E. Single-Frequency Noise
VCC
6.2 kΩ
A(TIP)
A(TIP)
B(RING)
15 pF
RL = 600 Ω
E0
RG = 2 kΩ
B(RING)
E1
H. Loop-Detector Switching
G. Ground-Key Switching
16
DET
Am79M574 Data Sheet
PHYSICAL DIMENSION
PL032
.447
.453
.485
.495
.009
.015
.585
.595
.042
.056
.125
.140
Pin 1 I.D.
.080
.095
.547
.553
SEATING
PLANE
.400
REF.
.490
.530
.013
.021
.050 REF.
.026
.032
TOP VIEW
SIDE VIEW
16-038FPO-5
PL 032
DA79
6-28-94 ae
REVISION SUMMARY
Revision B to Revision C
•
Minor changes were made to the data sheet style and format to conform to Legerity standards.
•
In the Pin Description table, inserted/changed TP pin description to: “Thermal pin. Connection for heat
dissipation. Internally connected to substrate (QBAT). Leave as open circuit or connected to QBAT. In both
cases, the TP pins can connect to an area of copper on the board to enhance heat dissipation.”
Revision C to Revision D
•
Minor changes were made to the data sheet style and format to conform to Legerity standards.
Revision D to Revision E
•
The physical dimension (PL032) was added to the Physical Dimension section.
•
Deleted the Ceramic DIP and Plastic DIP part (Am79570) and references to it.
•
Updated the Pin Description table to correct inconsistencies.
SLIC Products
17
Legerity provides silicon solutions that enhance the performance, speeds time-to-market, and lowers the system
cost of our customers' products. By combining process, design, systems architecture, and a complete set of
software and hardware support tools with unparalleled factory and worldwide field applications support, Legerity
ensures its customers enjoy a smoother design experience. It is this commitment to our customers that places
Legerity in a class by itself.
The contents of this document are provided in connection with Legerity, Inc. products. Legerity makes no representations or warranties with respect to the accuracy or completeness of the contents of this publication and reserves the right to make changes to specifications and product
descriptions at any time without notice. No license, whether express, implied, arising by estoppel or otherwise, to any intellectual property rights
is granted by this publication. Except as set forth in Legerity's Standard Terms and Conditions of Sale, Legerity assumes no liability whatsoever,
and disclaims any express or implied warranty, relating to its products including, but not limited to, the implied warranty of merchantability, fitness
for a particular purpose, or infringement of any intellectual property right.
Legerity's products are not designed, intended, authorized or warranted for use as components in systems intended for surgical implant into the
body, or in other applications intended to support or sustain life, or in any other application in which the failure of Legerity's product could create
a situation where personal injury, death, or severe property or environmental damage may occur. Legerity reserves the right to discontinue or
make changes to its products at any time without notice.
© 1999 Legerity, Inc.
All rights reserved.
Trademarks
Legerity, the Legerity logo and combinations thereof, DSLAC and QSLAC are trademarks of Legerity, Inc.
Other product names used in this publication are for identification purposes only and may be trademarks of their respective companies.
P.O. Box 18200
Austin, Texas 78760-8200
Telephone: (512) 228-5400
Fax: (512) 228-5510
North America Toll Free: (800) 432-4009
To contact the Legerity Sales Office nearest you,
or to download or order product literature, visit
our website at www.legerity.com.
To order literature in North America, call:
(800) 572-4859
or email:
[email protected]
To order literature in Europe or Asia, call:
44-0-1179-341607
or email:
Europe — [email protected]
Asia — [email protected]