SN54ALS323, SN74ALS323 8-BIT UNIVERSAL SHIFT/STORAGE REGISTERS WITH SYNCHRONOUS CLEAR AND 3-STATE OUTPUTS SDAS267A – DECEMBER 1982 – REVISED DECEMBER 1994 • • • • • description These 8-bit universal shift /storage registers feature multiplexed input/output (I/O) ports to achieve full 8-bit data handling in a 20-pin package. Two function-select (S0, S1) inputs and two output-enable (OE1, OE2) inputs can be used to choose the modes of operation listed in the function table. S0 OE1 OE2 G/QG E/QE C/QC A/QA QA′ CLR GND 1 20 2 19 3 18 4 17 5 16 6 15 7 14 8 13 9 12 10 11 VCC S1 SL QH′ H/QH F/QF D/QD B/QB CLK SR SN54ALS323 . . . FK PACKAGE (TOP VIEW) G/QG E/QE C/QC A/QA QA′ S1 • SN54ALS323 . . . J PACKAGE SN74ALS323 . . . DW OR N PACKAGE (TOP VIEW) OE2 OE1 S0 VCC • Multiplexed I/O Ports Provide Improved Bit Density Four Modes of Operation: – Hold (Store) – Shift Right – Shift Left – Load Data Operate With Outputs Enabled or at High Impedance 3-State Outputs Drive Bus Lines Directly Can Be Cascaded for n-Bit Word Lengths Synchronous Clear Applications: – Stacked or Push-Down Registers – Buffer Storage – Accumulator Registers Package Options Include Plastic Small-Outline (DW) Packages, Ceramic Chip Carriers (FK), and Standard Plastic (N) and Ceramic (J) 300-mil DIPs 4 3 2 1 20 19 18 5 17 6 16 7 15 8 14 9 10 11 12 13 SL QH′ H/QH F/QF D/QD CLR GND SR CLK B/Q B • Synchronous parallel loading is accomplished by taking both S0 and S1 high. This places the 3-state outputs in the high-impedance state and permits data applied on the I/O ports to be clocked into the register. Reading out of the register can be accomplished while the outputs are enabled in any mode. Clearing occurs synchronously when the clear (CLR) input is low. Taking either OE1 or OE2 high disables the outputs but has no effect on clearing, shifting, or storing data. The SN54ALS323 is characterized for operation over the full military temperature range of – 55°C to 125°C. The SN74ALS323 is characterized for operation from 0°C to 70°C. Copyright 1994, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 SN54ALS323, SN74ALS323 8-BIT UNIVERSAL SHIFT/STORAGE REGISTERS WITH SYNCHRONOUS CLEAR AND 3-STATE OUTPUTS SDAS267A – DECEMBER 1982 – REVISED DECEMBER 1994 FUNCTION TABLE INPUTS MODE I/O PORTS CLR S1 S0 OE1† OE2† CLK SL SR A/QA B/QB C/QC D/QD Clear L L L X L H L X H L L X L L X ↑ ↑ ↑ X X X X X X L L X L L X L L X Hold H H L X L X L L L L X L X X X X QA0 QA0 QB0 QB0 Shift Right H H L L H H L L L L ↑ ↑ X X H L H L Shift Left H H H H L L L L L L ↑ ↑ H L X X Load H H H X X ↑ X X OUTPUTS F/QF L L X G/QG H/QH QA′ QH′ L L X E/QE L L X L L X L L X L L L L L L QC0 QC0 QD0 QD0 QE0 QE0 QF0 QF0 QG0 QG0 QH0 QH0 QA0 QA0 QH0 QH0 QAn QAn QBn QBn QCn QCn QDn QDn QEn QEn QFn QFn QGn QGn H L QGn QGn QBn QBn QCn QCn QDn QDn QEn QEn QFn QFn QGn QGn QHn QHn H L QBn QBn H L a b c d e f g h a h NOTE: a . . . h = the level of the steady-state input at inputs A through H, respectively. This data is loaded into the flip-flops while the flip-flop outputs are isolated from the I/O terminals. † When one or both output-enable inputs are high, the eight I/O terminals are disabled to the high-impedance state; however, sequential operation or clearing of the register is not affected. logic symbol‡ CLR OE1 9 2 SRG8 4R & 3 3EN13 OE2 S0 S1 CLK SR 1 19 0 1 M 0 3 12 C4/1→/2← 11 7 A /QA B/QB D/QD E/QE F/QF G/QG H/QH SL Z5 3, 4D 6, 13 C/QC Z6 6 14 5 15 4 16 18 3, 4D 12, 13 Z12 17 QH′ 2, 4D ‡ This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12. 2 QA′ 3,4D 5, 13 13 8 1,4D POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SN54ALS323, SN74ALS323 8-BIT UNIVERSAL SHIFT/STORAGE REGISTERS WITH SYNCHRONOUS CLEAR AND 3-STATE OUTPUTS SDAS267A – DECEMBER 1982 – REVISED DECEMBER 1994 logic diagram (positive logic) CLR S0 S1 SR (shift right serial input) CLK 9 1 19 18 11 Six Identical Channels Not Shown† 12 1D 1D C1 QA′ OE1 OE2 SL (shift left serial input) C1 17 8 QH′ 2 3 7 16 A/QA H/QH † I/O ports not shown: B/QB (13), C/QC (6), D/QD (14), E/QE (5), F/QF (15), and G/QG (4). absolute maximum ratings over operating free-air temperature range (unless otherwise noted)‡ Supply voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V Input voltage, VI: All inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V I/O ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5 V Operating free-air temperature range, TA: SN54ALS323 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 55°C to 125°C SN74ALS323 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 65°C to 150°C ‡ Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3 SN54ALS323, SN74ALS323 8-BIT UNIVERSAL SHIFT/STORAGE REGISTERS WITH SYNCHRONOUS CLEAR AND 3-STATE OUTPUTS SDAS267A – DECEMBER 1982 – REVISED DECEMBER 1994 recommended operating conditions SN54ALS323 VCC VIH Supply voltage VIL Low-level input voltage High-level input voltage IOH High level output current High-level IOL Low level output current Low-level TA Operating free-air temperature SN74ALS323 MIN NOM MAX MIN NOM MAX 4.5 5 5.5 4.5 5 5.5 2 2 QA′ or QH′ QA thru QH 0.7 0.8 – 0.4 – 0.4 –1 – 2.6 4 8 QA thru QH 12 24 125 V V QA′ or QH′ – 55 UNIT 0 70 V mA mA °C electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER VIK VOH Any output VCC = 4.5 V, VCC = 4.5 V to 5.5 V, II = – 18 mA IOH = – 0.4 mA QA thru QH VCC = 4 4.5 5V IOH = – 1 mA IOH = – 2.6 mA QA′ or QH′ VCC = 4 4.5 5V IOL = 4 mA IOL = 8 mA 0.25 0.4 5V VCC = 4 4.5 IOL = 12 mA IOL = 24 mA 0.25 0.4 VCC = 5 5.5 5V VI = 5.5 V VI = 7 V VCC = 5.5 V, VI = 2.7 V VOL QA thru QH II A thru H Any others IIH‡ IIL‡ IOS§ ICC SN54ALS323 MIN TYP† MAX TEST CONDITIONS S0, S1, SR, SL Any others QA′ or QH′ QA thru QH VCC = 5 5.5 5V V, VI = 0 0.4 4V VCC = 5 5.5 5V V, VO = 2 2.25 25 V VCC = 5.5 V SN74ALS323 MIN TYP† MAX – 1.5 VCC – 2 2.4 – 1.5 UNIT V VCC – 2 V 3.3 2.4 3.2 0.25 0.4 0.35 0.5 0.25 0.4 0.35 0.5 0.1 0.1 0.1 0.1 20 20 – 0.2 – 0.2 – 0.1 – 0.1 – 15 –70 – 15 –70 – 20 –112 – 30 –112 Outputs high 15 28 15 28 Outputs low 22 38 22 38 Outputs disabled 23 40 23 40 V mA µA mA mA mA † All typical values are at VCC = 5 V, TA = 25°C. ‡ For I/O ports (QA thru QH), the parameters IIH and IIL include the off-state output current. § The output conditions have been chosen to produce a current that closely approximates one half of the true short-circuit output current, IOS. 4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SN54ALS323, SN74ALS323 8-BIT UNIVERSAL SHIFT/STORAGE REGISTERS WITH SYNCHRONOUS CLEAR AND 3-STATE OUTPUTS SDAS267A – DECEMBER 1982 – REVISED DECEMBER 1994 timing requirements over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) SN54ALS323 fclock tw tsu Clock frequency (at 50% duty cycle) Pulse duration ↑ Setup time before CLK↑ th Hold time after CLK↑ MAX 0 17 SN74ALS323 MIN MAX 0 17 CLK high or low 22 16.5 S0 or S1 25 20 High 18 16 Low 15 6 CLR active 25 20 CLR 18 16 S0 or S1 0 0 Serial or parallel data 0 0 Serial or parallel data Inactive-state setup time before CLK↑† MIN UNIT MHz ns ns ns † Inactive-state setup time is also referred to as recovery time. switching characteristics (see Figure 1) PARAMETER FROM (INPUT) TO (OUTPUT) VCC = 4.5 V to 5.5 V, CL = 50 pF, R1 = 500 Ω, R2 = 500 Ω, TA = MIN to MAX‡ SN54ALS323 MIN fmax tPLH tPHL tPLH tPHL tPZH tPZL tPZH tPZL tPHZ tPLZ tPHZ SN74ALS323 MAX 17 CLK QA thru QH CLK QA′′ or QH′′ OE1 OE2 OE1, QA thru QH S0 S1 S0, QA thru QH OE1 OE2 OE1, QA thru QH • DALLAS, TEXAS 75265 MIN MAX 17 MHz 2 19 4 13 4 25 7 19 2 21 5 15 4 25 8 18 5 22 6 16 6 27 8 22 5 27 7 17 6 27 8 22 1 15 1 8 4 38 5 15 1 12 8 25 1 16 S0 S1 S0, QA thru QH tPLZ 4 34 ‡ For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions. POST OFFICE BOX 655303 UNIT ns ns ns ns ns ns 5 SN54ALS323, SN74ALS323 8-BIT UNIVERSAL SHIFT/STORAGE REGISTERS WITH SYNCHRONOUS CLEAR AND 3-STATE OUTPUTS SDAS267A – DECEMBER 1982 – REVISED DECEMBER 1994 PARAMETER MEASUREMENT INFORMATION SERIES 54ALS/74ALS AND 54AS/74AS DEVICES 7V RL = R1 = R2 VCC S1 RL R1 Test Point From Output Under Test CL (see Note A) From Output Under Test RL Test Point From Output Under Test CL (see Note A) CL (see Note A) LOAD CIRCUIT FOR BI-STATE TOTEM-POLE OUTPUTS LOAD CIRCUIT FOR OPEN-COLLECTOR OUTPUTS 3.5 V Timing Input Test Point LOAD CIRCUIT FOR 3-STATE OUTPUTS 3.5 V High-Level Pulse 1.3 V R2 1.3 V 1.3 V 0.3 V 0.3 V Data Input tw th tsu 3.5 V 1.3 V 3.5 V Low-Level Pulse 1.3 V 0.3 V 1.3 V 0.3 V VOLTAGE WAVEFORMS SETUP AND HOLD TIMES VOLTAGE WAVEFORMS PULSE DURATIONS 3.5 V Output Control (low-level enabling) 1.3 V 1.3 V 0.3 V tPZL Waveform 1 S1 Closed (see Note B) tPLZ [3.5 V 1.3 V tPHZ tPZH Waveform 2 S1 Open (see Note B) 1.3 V VOL 0.3 V VOH 1.3 V 0.3 V [0 V 3.5 V 1.3 V Input 1.3 V 0.3 V tPHL tPLH VOH In-Phase Output 1.3 V 1.3 V VOL tPLH tPHL VOH Out-of-Phase Output (see Note C) 1.3 V 1.3 V VOL VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES, 3-STATE OUTPUTS NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. When measuring propagation delay items of 3-state outputs, switch S1 is open. D. All input pulses have the following characteristics: PRR ≤ 1 MHz, tr = tf = 2 ns, duty cycle = 50%. E. The outputs are measured one at a time with one transition per measurement. Figure 1. Load Circuits and Voltage Waveforms 6 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 IMPORTANT NOTICE Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. 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