ISL9H1260EG3, ISL9H1260EP3, ISL9H1260ES3 Data Sheet [ /Title (ISL9 H1260 EG3, ISL9H 1260E P3, ISL9H 1260E S3) /Subjec t (600V, SMPS II LGC Series NChann el IGBT with AntiParalle l Stealth TM Diode) /Autho r () /Keyw ords (Intersi l Corpor ation, semico nducto r, 600V, January 2001 600V, SMPS II LGC Series N-Channel IGBT with Anti-Parallel StealthTM Diode The ISL9H1260EG3, ISL9H1260EP3 and ISL9H1260ES3 are Low Gate Charge (LGC) SMPS II IGBTs combining the fast switching speed of the SMPS IGBTs with lower gate charge and avalanche capability (UIS). These LGC devices shorten delay times, and reduce the power requirement of the gate drive. These devices are ideally suited for high voltage switched mode power supply applications where low conduction loss, fast switching times and UIS capability are essential. SMPS II LGC devices have been specially designed for: • Power Factor Correction (PFC) Circuits • Full Bridge Topologies • Half Bridge Topologies • Push-Pull Circuits • Uninterruptible Power Supplies • Zero Voltage and Zero Current Switching Circuits File Number 5018 Features • >100kHz Operation at 390V, 12A • 200kHz Operation at 390V, 9A • 600V Switching SOA Capability • Typical Fall Time . . . . . . . . . . . . . . . . . . . .72ns at TJ = 125oC • Low Gate Charge . . . . . . . . . . . . . . . . .23nC at VGE = 15V • UIS Rated . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .150mJ • Low Conduction Loss Symbol C G Formerly Developmental Type TA49336. E Ordering Information PART NUMBER PACKAGE BRAND ISL9H1260EG3 TO-247 G1260EG3 ISL9H1260EP3 TO-220AB G1260EP3 ISL9H1260ES3 TO-263AB G1260ES3 NOTE: When ordering, use the entire part number. Add the suffix T to obtain the TO-263AB variant in tape and reel, e.g., ISL9H1260ES3T. Packaging JEDEC STYLE TO-247 JEDEC TO-220AB E E C C G COLLECTOR G COLLECTOR (FLANGE) (FLANGE) JEDEC TO-263AB G E COLLECTOR (FLANGE) INTERSIL CORPORATION IGBT PRODUCT IS COVERED BY ONE OR MORE OF THE FOLLOWING U.S. PATENTS 4,364,073 4,598,461 4,682,195 4,803,533 4,888,627 4,417,385 4,605,948 4,684,413 4,809,045 4,890,143 ©2001 Fairchild Semiconductor Corporation 4,430,792 4,620,211 4,694,313 4,809,047 4,901,127 4,443,931 4,631,564 4,717,679 4,810,665 4,904,609 4,466,176 4,639,754 4,743,952 4,823,176 4,933,740 4,516,143 4,639,762 4,783,690 4,837,606 4,963,951 4,532,534 4,641,162 4,794,432 4,860,080 4,969,027 4,587,713 4,644,637 4,801,986 4,883,767 ISL9H1260EG3, ISL9H1260EP3, ISL9H1260ES3 Rev. A ISL9H1260EG3, ISL9H1260EP3, ISL9H1260ES3 Absolute Maximum Ratings TC = 25oC, Unless Otherwise Specified ALL TYPES 600 UNITS V 50 20 A A Collector Current Pulsed (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ICM Gate to Emitter Voltage Continuous. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VGES Gate to Emitter Voltage Pulsed . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VGEM Switching Safe Operating Area at TJ = 150oC, Figure 2 . . . . . . . . . . . . . . . . . . . . . . . . SSOA Single Pulse Avalanche Energy at TC = 25oC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . EAS 108 ±20 ±30 60A at 600V 150mJ at 12A A V V Power Dissipation Total at TC = 25oC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PD Power Dissipation Derating TC > 25oC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Operating and Storage Junction Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . TJ, TSTG Maximum Lead Temperature for Soldering Leads at 0.063in (1.6mm) from Case for 10s. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TL Package Body for 10s, See Tech Brief 334 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TPKG 167 1.33 -55 to 150 W W/oC oC 300 260 oC oC Collector to Emitter Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .BVCES Collector Current Continuous At TC = 25oC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IC25 At TC = 110oC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IC110 CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTE: 1. Pulse width limited by maximum junction temperature. Electrical Specifications TJ = 25oC, Unless Otherwise Specified PARAMETER Collector to Emitter Breakdown Voltage Collector to Emitter Leakage Current Collector to Emitter Saturation Voltage Gate to Emitter Threshold Voltage SYMBOL BVCES ICES VCE(SAT) VGE(TH) TEST CONDITIONS MIN TYP MAX UNITS 600 - - V TJ = 25oC - - 100 µA TJ = 125oC - - 2 mA TJ = 25oC - 1.95 2.7 V TJ = 125oC - 1.7 2.0 V 4.5 6.5 7.0 V - - ±250 nA IC = 250µA, VGE = 0V VCE = 600V IC =12A, VGE = 15V IC = 250µA, VCE = 600V Gate to Emitter Leakage Current IGES VGE = ±20V Switching SOA SSOA TJ = 150oC, RG = 10Ω, VGE = 15V L = 100µH, VCE = 600V 60 - - A EAS ICE = 12A, L = 2.1mH, VDD = 50V 150 - - mJ - 9.0 - V VGE = 15V - 23 30 nC VGE = 20V - 28 36 nC - 16 - ns - 14 - ns - 42 - ns - 18 - ns Pulsed Avalanche Energy Gate to Emitter Plateau Voltage On-State Gate Charge Current Turn-On Delay Time Current Rise Time Current Turn-Off Delay Time Current Fall Time VGEP Qg(ON) td(ON)I trI td(OFF)I tfI IC = 12A, VCE = 300V IC = 12A, VCE = 300V IGBT and Diode at TJ = 25oC ICE = 12A VCE = 390V VGE = 15V RG = 10Ω L = 200µH Test Circuit - Figure 26 Turn-On Energy (Note 2) EON1 - 55 - µJ Turn-On Energy (Note 2) EON2 - 170 - µJ Turn-Off Energy (Note 3) EOFF - 100 - µJ ©2001 Fairchild Semiconductor Corporation ISL9H1260EG3, ISL9H1260EP3, ISL9H1260ES3 Rev. A ISL9H1260EG3, ISL9H1260EP3, ISL9H1260ES3 Electrical Specifications TJ = 25oC, Unless Otherwise Specified (Continued) PARAMETER SYMBOL Current Turn-On Delay Time td(ON)I Current Rise Time trI Current Turn-Off Delay Time td(OFF)I Current Fall Time tfI TEST CONDITIONS IGBT and Diode at TJ = 125oC ICE = 12A VCE = 390V VGE = 15V RG = 10Ω L = 200µH Test Circuit - Figure 26 MIN TYP MAX UNITS - 22 - ns - 15 - ns - 80 100 ns - 72 90 ns Turn-On Energy (Note 2) EON1 - 55 - µJ Turn-On Energy (Note 2) EON2 - 230 280 µJ Turn-Off Energy (Note 3) EOFF - 225 300 µJ Diode Forward Voltage VEC IEC = 12A - 2.1 2.5 V IEC = 1A, dIEC/dt = 200A/µs, VCE = 30V - 25 30 ns IEC = 12A, dIEC/dt = 200A/µs, VCE = 30V - 35 40 ns IGBT - - 0.75 oC/W Diode - - 2.0 oC/W Diode Reverse Recovery trr Thermal Resistance Junction To Case RθJC NOTES: 2. Values for two Turn-On loss conditions are shown for the convenience of the circuit designer. E ON1 is the turn-on loss of the IGBT only. EON2 is the turn-on loss when a typical diode is used in the test circuit and the diode is at the same T J as the IGBT. The diode type is specified in Figure 26. 3. Turn-Off Energy Loss (EOFF) is defined as the integral of the instantaneous power loss starting at the trailing edge of the input pulse and ending at the point where the collector current equals zero (ICE = 0A). All devices were tested per JEDEC Standard No. 24-1 Method for Measurement of Power Device Turn-Off Switching Loss. This test method produces the true total Turn-Off Energy Loss. Unless Otherwise Specified ICE , DC COLLECTOR CURRENT (A) 50 VGE = 15V TJ = 150oC 40 30 20 10 0 25 50 75 100 125 TC , CASE TEMPERATURE (oC) FIGURE 1. DC COLLECTOR CURRENT vs CASE TEMPERATURE ©2001 Fairchild Semiconductor Corporation 150 ICE, COLLECTOR TO EMITTER CURRENT (A) Typical Performance Curves 70 TJ = 150oC, RG = 10Ω, VGE = 15V 60 50 40 30 20 10 0 0 100 200 300 400 500 600 700 VCE, COLLECTOR TO EMITTER VOLTAGE (V) FIGURE 2. MINIMUM SWITCHING SAFE OPERATING AREA ISL9H1260EG3, ISL9H1260EP3, ISL9H1260ES3 Rev. A ISL9H1260EG3, ISL9H1260EP3, ISL9H1260ES3 Typical Performance Curves TC 75oC VGE = 15V VGE = 12V 100 fMAX1 = 0.05 / (td(OFF)I + td(ON)I) fMAX2 = (PD - PC) / (EON2 + EOFF) PC = CONDUCTION DISSIPATION (DUTY FACTOR = 50%) RØJC = 0.75oC/W, SEE NOTES TJ = 125oC, RG = 10Ω, L = 200µH, V CE = 390V 10 1 5 20 10 30 140 24 VCE = 390V, RG = 10Ω, TJ = 125oC 120 20 ISC 100 16 80 12 tSC 60 8 40 4 10 ICE, COLLECTOR TO EMITTER CURRENT (A) 14 12 10 8 6 TJ = 25oC TJ = 150oC 4 TJ = 125oC 2 0 0 1.5 1.0 0.5 2.0 2.5 DUTY CYCLE < 0.5%, VGE = 15V PULSE DURATION = 250µs 16 14 12 TJ = 150oC 10 TJ = 25oC 8 6 4 TJ = 125oC 2 0 0 EOFF , TURN-OFF ENERGY LOSS (µJ) EON2 , TURN-ON ENERGY LOSS (µJ) 275 RG = 10Ω, VCE = 390V TJ = 125oC, VGE = 12V, VGE = 15V 300 250 200 150 100 TJ = 25oC, VGE = 12V, VGE = 15V 0 2 4 6 8 10 12 ICE , COLLECTOR TO EMITTER CURRENT (A) FIGURE 7. TURN-ON ENERGY LOSS vs COLLECTOR TO EMITTER CURRENT ©2001 Fairchild Semiconductor Corporation 1.5 1.0 2.0 2.5 FIGURE 6. COLLECTOR TO EMITTER ON-STATE VOLTAGE 400 0 0.5 VCE, COLLECTOR TO EMITTER VOLTAGE (V) FIGURE 5. COLLECTOR TO EMITTER ON-STATE VOLTAGE 50 15 18 VCE, COLLECTOR TO EMITTER VOLTAGE (V) 350 14 FIGURE 4. SHORT CIRCUIT WITHSTAND TIME ICE, COLLECTOR TO EMITTER CURRENT (A) ICE, COLLECTOR TO EMITTER CURRENT (A) DUTY CYCLE < 0.5%, VGE = 12V PULSE DURATION = 250µs 16 13 12 VGE , GATE TO EMITTER VOLTAGE (V) FIGURE 3. OPERATING FREQUENCY vs COLLECTOR TO EMITTER CURRENT 18 11 ISC, PEAK SHORT CIRCUIT CURRENT (A) fMAX, OPERATING FREQUENCY (kHz) 1000 tSC , SHORT CIRCUIT WITHSTAND TIME (µs) Unless Otherwise Specified (Continued) 14 RG = 10Ω, VCE = 390V 250 225 200 175 TJ = 125oC, VGE = 12V OR 15V 150 125 100 75 50 25 TJ = 25oC, VGE = 12V OR 15V 0 0 2 4 6 8 10 12 14 ICE , COLLECTOR TO EMITTER CURRENT (A) FIGURE 8. TURN-OFF ENERGY LOSS vs COLLECTOR TO EMITTER CURRENT ISL9H1260EG3, ISL9H1260EP3, ISL9H1260ES3 Rev. A ISL9H1260EG3, ISL9H1260EP3, ISL9H1260ES3 Typical Performance Curves Unless Otherwise Specified (Continued) 35 RG = 10Ω, VCE = 390V 22 RG = 10Ω, VCE = 390V 30 TJ = 25oC, VGE = 12V trI , RISE TIME (ns) td(ON)I, TURN-ON DELAY TIME (ns) 24 20 TJ = 125oC, VGE = 12V 18 16 TJ = 25oC, VGE = 15V 14 TJ = 125oC, VGE = 15V 25 20 15 10 12 5 10 0 0 2 4 6 8 10 12 14 TJ = 25oC OR TJ = 125oC, VGE = 12V TJ = 25oC OR TJ = 125oC, VGE = 15V 0 2 ICE , COLLECTOR TO EMITTER CURRENT (A) 70 VGE = 12V, TJ = 125oC 60 VGE = 15V, TJ = 25oC 40 70 14 TJ = 125oC, VGE = 12V OR 15V 60 50 40 TJ = 25oC, VGE = 12V OR 15V 20 VGE = 12V, TJ = 25oC 0 2 4 6 8 10 12 10 14 2 4 ICE , COLLECTOR TO EMITTER CURRENT (A) TJ = -55oC 100 TJ = 125oC 75 50 25 VGE, GATE TO EMITTER VOLTAGE (V) 16 DUTY CYCLE < 0.5%, VCE = 10V PULSE DURATION = 250µs TJ = 25oC 125 8 10 12 14 16 18 20 22 24 FIGURE 12. FALL TIME vs COLLECTOR TO EMITTER CURRENT 175 150 6 ICE , COLLECTOR TO EMITTER CURRENT (A) FIGURE 11. TURN-OFF DELAY TIME vs COLLECTOR TO EMITTER CURRENT ICE, COLLECTOR TO EMITTER CURRENT (A) 12 RG = 10Ω, VCE = 390V 30 30 20 10 80 tfI , FALL TIME (ns) td(OFF)I , TURN-OFF DELAY TIME (ns) 90 VGE = 15V, TJ = 125oC 50 8 FIGURE 10. TURN-ON RISE TIME vs COLLECTOR TO EMITTER CURRENT 90 80 6 ICE , COLLECTOR TO EMITTER CURRENT (A) FIGURE 9. TURN-ON DELAY TIME vs COLLECTOR TO EMITTER CURRENT RG = 10Ω, VCE = 390V 4 IG(REF) = 1mA, RL = 25Ω, TJ = 25oC 14 VCE = 600V 12 10 8 VCE = 400V VCE = 200V 6 4 2 0 0 6 7 8 9 10 11 12 13 14 VGE, GATE TO EMITTER VOLTAGE (V) FIGURE 13. TRANSFER CHARACTERISTIC ©2001 Fairchild Semiconductor Corporation 15 16 0 2 4 6 8 10 12 14 16 18 20 22 24 QG , GATE CHARGE (nC) FIGURE 14. GATE CHARGE WAVEFORMS ISL9H1260EG3, ISL9H1260EP3, ISL9H1260ES3 Rev. A ISL9H1260EG3, ISL9H1260EP3, ISL9H1260ES3 1.4 Unless Otherwise Specified (Continued) RG = 10Ω, VCE = 390V 1.2 ETOTAL = EON2 + EOFF 1.0 ICE = 24A 0.8 0.6 0.4 ICE = 12A ICE = 6A 0.2 0 25 50 75 125 100 150 ETOTAL, TOTAL SWITCHING ENERGY LOSS (mJ) ETOTAL, TOTAL SWITCHING ENERGY LOSS (mJ) Typical Performance Curves 10 TJ = 125oC, VCE = 390V, VGE = 15V ETOTAL = EON2 + EOFF ICE = 24A 1 ICE = 12A ICE = 6A 0.1 3 10 TC , CASE TEMPERATURE (oC) FREQUENCY = 1MHz C, CAPACITANCE (pF) 1200 1000 CIES 800 600 COES 400 200 0 CRES 0 20 40 60 80 100 FIGURE 16. TOTAL SWITCHING LOSS vs GATE RESISTANCE VCE, COLLECTOR TO EMITTER VOLTAGE (V) FIGURE 15. TOTAL SWITCHING LOSS vs CASE TEMPERATURE 1400 2.4 DUTY CYCLE < 0.5%, VGE = 15V PULSE DURATION = 250µs, TJ = 25oC 2.3 2.2 ICE = 18A 2.1 2.0 ICE = 12A 1.9 ICE = 6A 1.8 10 VCE, COLLECTOR TO EMITTER VOLTAGE (V) trr , REVERSE RECOVERY TIMES (ns) IEC , FORWARD CURRENT (A) 16 125oC 25oC 12 8 4 0.5 1.0 1.5 2.0 2.5 VEC , FORWARD VOLTAGE (V) FIGURE 19. DIODE FORWARD CURRENT vs FORWARD VOLTAGE DROP ©2001 Fairchild Semiconductor Corporation 14 200 DUTY CYCLE < 0.5%, PULSE DURATION = 250µs 0 13 12 15 16 FIGURE 18. COLLECTOR TO EMITTER ON-STATE VOLTAGE vs GATE TO EMITTER VOLTAGE 20 0 11 VGE, GATE TO EMITTER VOLTAGE (V) FIGURE 17. CAPACITANCE vs COLLECTOR TO EMITTER VOLTAGE 24 1000 100 RG, GATE RESISTANCE (Ω) 3.0 125oC trr dIEC/dt = 200A/µs, VCE = 390V 175 150 125oC tb 125 25oC trr 100 75 25oC tb 50 125oC ta 25 25oC ta 0 2 4 6 8 10 12 IEC , FORWARD CURRENT (A) FIGURE 20. REVERSE RECOVERY TIMES vs DIODE FORWARD CURRENT ISL9H1260EG3, ISL9H1260EP3, ISL9H1260ES3 Rev. A ISL9H1260EG3, ISL9H1260EP3, ISL9H1260ES3 Unless Otherwise Specified (Continued) Qrr , REVERSE RECOVERY CHARGE (nC) Typical Performance Curves trr , REVERSE RECOVERY TIMES (ns) 175 IEC = 12A, VCE = 390V 150 125oC tb 125 100 25oC tb 75 50 125oC ta 25 0 200 25oC ta 300 400 600 500 700 800 900 1000 700 VCE = 390V 500 400 125oC, IEC = 6A 300 25oC, IEC = 12A 200 25oC, IEC = 6A 100 0 200 dIEC/dt, RATE OF CHANGE OF CURRENT (A/µs) IRRM, MAX REVERSE RECOVERY CURRENT (A) S, REVERSE RECOVERY SOFTNESS FACTOR VCE = 390V, TJ = 125˚C 6.0 IEC = 12A 5.5 5.0 4.5 IEC = 6A 3.5 3.0 200 300 400 500 600 700 800 900 1000 10 500 600 700 VCE = 390V, TJ = 125˚C 800 1000 900 IEC = 12A 9 8 IEC = 6A 7 6 5 4 3 200 300 dIF /dt, CURRENT RATE OF CHANGE (A/µs) 400 500 600 700 800 900 1000 dIF /dt, CURRENT RATE OF CHANGE (A/µs) FIGURE 23. REVERSE RECOVERY SOFTNESS FACTOR vs RATE OF CHANGE OF CURRENT ZθJC , NORMALIZED THERMAL RESPONSE 400 FIGURE 22. STORED CHARGE vs RATE OF CHANGE OF CURRENT 6.5 4.0 300 dIEC/dt, RATE OF CHANGE OF CURRENT (A/µs) FIGURE 21. REVERSE RECOVERY TIMES vs RATE OF CHANGE OF CURRENT 7.0 125oC, IEC = 12A 600 FIGURE 24. MAXIMUM REVERSE RECOVERY CURRENT vs RATE OF CHANGE OF CURRENT 100 0.5 0.2 10-1 t1 0.1 PD 0.05 t2 0.02 DUTY FACTOR, D = t1 / t2 PEAK TJ = (PD X ZθJC X RθJC) + TC 0.01 SINGLE PULSE 10-2 10-5 10-4 10-3 10-2 10-1 100 101 t1 , RECTANGULAR PULSE DURATION (s) FIGURE 25. IGBT NORMALIZED TRANSIENT THERMAL RESPONSE, JUNCTION TO CASE ©2001 Fairchild Semiconductor Corporation ISL9H1260EG3, ISL9H1260EP3, ISL9H1260ES3 Rev. A ISL9H1260EG3, ISL9H1260EP3, ISL9H1260ES3 Test Circuit and Waveforms ISL9H1260EP3 90% 10% VGE EON2 EOFF L = 200µH VCE RG = 10Ω 90% ICE + ISL9H1260EP3 - VDD = 390V FIGURE 26. INDUCTIVE SWITCHING TEST CIRCUIT 10% td(OFF)I tfI trI td(ON)I FIGURE 27. SWITCHING TEST WAVEFORMS Handling Precautions for IGBTs Operating Frequency Information Insulated Gate Bipolar Transistors are susceptible to gate-insulation damage by the electrostatic discharge of energy through the devices. When handling these devices, care should be exercised to assure that the static charge built in the handler’s body capacitance is not discharged through the device. With proper handling and application procedures, however, IGBTs are currently being extensively used in production by numerous equipment manufacturers in military, industrial and consumer applications, with virtually no damage problems due to electrostatic discharge. IGBTs can be handled safely if the following basic precautions are taken: Operating frequency information for a typical device (Figure 3) is presented as a guide for estimating device performance for a specific application. Other typical frequency vs collector current (ICE) plots are possible using the information shown for a typical unit in Figures 5, 6, 7, 8, 9 and 11. The operating frequency plot (Figure 3) of a typical device shows fMAX1 or fMAX2; whichever is smaller at each point. The information is based on measurements of a typical device and is bounded by the maximum rated junction temperature. 1. Prior to assembly into a circuit, all leads should be kept shorted together either by the use of metal shorting springs or by the insertion into conductive material such as “ECCOSORBD LD26” or equivalent. 2. When devices are removed by hand from their carriers, the hand being used should be grounded by any suitable means - for example, with a metallic wristband. 3. Tips of soldering irons should be grounded. 4. Devices should never be inserted into or removed from circuits with power on. 5. Gate Voltage Rating - Never exceed the gate-voltage rating of VGEM. Exceeding the rated VGE can result in permanent damage to the oxide layer in the gate region. 6. Gate Termination - The gates of these devices are essentially capacitors. Circuits that leave the gate open-circuited or floating should be avoided. These conditions can result in turn-on of the device due to voltage buildup on the input capacitor due to leakage currents or pickup. fMAX1 is defined by fMAX1 = 0.05/(td(OFF)I+ td(ON)I). Deadtime (the denominator) has been arbitrarily held to 10% of the on-state time for a 50% duty factor. Other definitions are possible. td(OFF)I and td(ON)I are defined in Figure 27. Device turn-off delay can establish an additional frequency limiting condition for an application other than TJM. fMAX2 is defined by fMAX2 = (PD - PC)/(EOFF + EON2). The allowable dissipation (PD) is defined by PD = (TJM - TC)/RθJC. The sum of device switching and conduction losses must not exceed PD . A 50% duty factor was used (Figure 3) and the conduction losses (PC) are approximated by PC = (VCE x ICE)/2. EON2 and EOFF are defined in the switching waveforms shown in Figure 27. EON2 is the integral of the instantaneous power loss (ICE x VCE) during turn-on and EOFF is the integral of the instantaneous power loss (ICE x VCE) during turn-off. All tail losses are included in the calculation for EOFF; i.e., the collector current equals zero (ICE = 0). 7. Gate Protection - These devices do not have an internal monolithic Zener diode from gate to emitter. If gate protection is required an external Zener is recommended. ©2001 Fairchild Semiconductor Corporation ISL9H1260EG3, ISL9H1260EP3, ISL9H1260ES3 Rev. A ISL9H1260EG3, ISL9H1260EP3, ISL9H1260ES3 TO-247 3 LEAD JEDEC STYLE TO-247 PLASTIC PACKAGE A E ØS Q ØR D L1 b1 b2 L c b 2 1 3 3 e e1 J1 INCHES TERM. 4 ØP MILLIMETERS SYMBOL MIN MAX MIN MAX A 0.180 0.190 4.58 4.82 NOTES - b 0.046 0.051 1.17 1.29 2, 3 b1 0.060 0.070 1.53 1.77 1, 2 b2 0.095 0.105 2.42 2.66 1, 2 c 0.020 0.026 0.51 0.66 1, 2, 3 D 0.800 0.820 20.32 20.82 - E 0.605 0.625 15.37 15.87 - e 0.219 TYP 5.56 TYP 4 e1 0.438 BSC 11.12 BSC 4 J1 0.090 0.105 2.29 2.66 1 L 0.620 0.640 15.75 16.25 - BACK VIEW L1 0.145 0.155 3.69 3.93 1 ØP 0.138 0.144 3.51 3.65 - Q 0.210 0.220 5.34 5.58 - ØR 0.195 0.205 4.96 5.20 - ØS 0.260 0.270 6.61 6.85 - 2 5 NOTES: 1. Lead dimension and finish uncontrolled in L1. 2. Lead dimension (without solder). 3. Add typically 0.002 inches (0.05mm) for solder coating. 4. Position of lead to be measured 0.250 inches (6.35mm) from bottom of dimension D. 5. Position of lead to be measured 0.100 inches (2.54mm) from bottom of dimension D. 6. Controlling dimension: Inch. 7. Revision 1 dated 1-93. ©2001 Fairchild Semiconductor Corporation ISL9H1260EG3, ISL9H1260EP3, ISL9H1260ES3 Rev. A ISL9H1260EG3, ISL9H1260EP3, ISL9H1260ES3 TO-263AB SURFACE MOUNT JEDEC TO-263AB PLASTIC PACKAGE E A A1 H1 TERM. 4 D SYMBOL A A1 b b1 b2 c D L2 L1 L 1 b b1 e c J1 e1 0.450 (11.43) TERM. 4 L3 b2 3 E e e1 H1 J1 L L1 3 0.350 (8.89) 0.700 (17.78) 0.150 (3.81) 1 0.080 TYP (2.03) 0.062 TYP (1.58) MINIMUM PAD SIZE RECOMMENDED FOR SURFACE-MOUNTED APPLICATIONS 1.5mm DIA. HOLE INCHES MIN MAX 0.170 0.180 0.048 0.052 0.030 0.034 0.045 0.310 0.018 0.405 0.055 0.022 0.425 0.395 0.405 0.100 TYP 0.200 BSC 0.045 0.055 0.095 0.105 0.175 0.195 MILLIMETERS MIN MAX 4.32 4.57 1.22 1.32 0.77 0.86 1.15 7.88 0.46 10.29 NOTES 4, 5 4, 5 1.39 0.55 10.79 4, 5 2 4, 5 - 10.04 10.28 2.54 TYP 5.08 BSC 1.15 1.39 2.42 2.66 4.45 4.95 7 7 - 0.090 0.110 2.29 2.79 4, 6 0.050 0.070 1.27 1.77 3 L2 L3 0.315 8.01 2 NOTES: 1. These dimensions are within allowable dimensions of Rev. C of JEDEC TO-263AB outline dated 2-92. 2. L3 and b2 dimensions established a minimum mounting surface for terminal 4. 3. Solder finish uncontrolled in this area. 4. Dimension (without solder). 5. Add typically 0.002 inches (0.05mm) for solder plating. 6. L1 is the terminal length for soldering. 7. Position of lead to be measured 0.120 inches (3.05mm) from bottom of dimension D. 8. Controlling dimension: Inch. 9. Revision 10 dated 5-99. 4.0mm USER DIRECTION OF FEED 2.0mm TO-263AB 1.75mm C L 24mm TAPE AND REEL 24mm 16mm COVER TAPE 40mm MIN. ACCESS HOLE 30.4mm 13mm 330mm 100mm GENERAL INFORMATION 1. 800 PIECES PER REEL. 2. ORDER IN MULTIPLES OF FULL REELS ONLY. 3. MEETS EIA-481 REVISION "A" SPECIFICATIONS. ©2001 Fairchild Semiconductor Corporation 24.4mm ISL9H1260EG3, ISL9H1260EP3, ISL9H1260ES3 Rev. A ISL9H1260EG3, ISL9H1260EP3, ISL9H1260ES3 TO-220AB 3 LEAD JEDEC TO-220AB PLASTIC PACKAGE A INCHES E ØP A1 Q H1 TERM. 4 D 45o E1 D1 L1 b1 L b c 60o 1 2 3 e e1 J1 MILLIMETERS SYMBOL MIN MAX MIN MAX NOTES A 0.170 0.180 4.32 4.57 - A1 0.048 0.052 1.22 1.32 3, 4 b 0.030 0.034 0.77 0.86 b1 0.045 0.055 1.15 1.39 2, 3 c 0.014 0.019 0.36 0.48 2, 3, 4 14.99 15.49 - D 0.590 0.610 D1 - 0.160 E 0.395 0.410 E1 - 0.030 10.04 - 4.06 - 10.41 - 0.76 - e 0.100 TYP 2.54 TYP 5 e1 0.200 BSC 5.08 BSC 5 H1 0.235 0.255 5.97 6.47 - J1 0.100 0.110 L 0.530 0.550 2.54 2.79 6 13.47 13.97 L1 0.130 0.150 3.31 - 3.81 2 ØP 0.149 0.153 3.79 3.88 - Q 0.102 0.112 2.60 2.84 - NOTES: 1. These dimensions are within allowable dimensions of Rev. J of JEDEC TO-220AB outline dated 3-24-87. 2. Lead dimension and finish uncontrolled in L1. 3. Lead dimension (without solder). 4. Add typically 0.002 inches (0.05mm) for solder coating. 5. Position of lead to be measured 0.250 inches (6.35mm) from bottom of dimension D. 6. Position of lead to be measured 0.100 inches (2.54mm) from bottom of dimension D. 7. Controlling dimension: Inch. 8. Revision 2 dated 7-97. ©2001 Fairchild Semiconductor Corporation ISL9H1260EG3, ISL9H1260EP3, ISL9H1260ES3 Rev. A TRADEMARKS The following are registered and unregistered trademarks Fairchild Semiconductor owns or is authorized to use and is not intended to be an exhaustive list of all such trademarks. ACEx™ Bottomless™ CoolFET™ CROSSVOLT™ DenseTrench™ DOME™ EcoSPARK™ E2CMOSTM EnSignaTM FACT™ FACT Quiet Series™ FAST FASTr™ GlobalOptoisolator™ GTO™ HiSeC™ ISOPLANAR™ LittleFET™ MicroFET™ MICROWIRE™ OPTOLOGIC™ OPTOPLANAR™ PACMAN™ POP™ PowerTrench QFET™ QS™ QT Optoelectronics™ Quiet Series™ SILENT SWITCHER SMART START™ Star* Power™ Stealth™ SuperSOT™-3 SuperSOT™-6 SuperSOT™-8 SyncFET™ TinyLogic™ UHC™ UltraFET VCX™ DISCLAIMER FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS. LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or 2. A critical component is any component of a life support device or system whose failure to perform can systems which, (a) are intended for surgical implant into be reasonably expected to cause the failure of the life the body, or (b) support or sustain life, or (c) whose support device or system, or to affect its safety or failure to perform when properly used in accordance with instructions for use provided in the labeling, can be effectiveness. reasonably expected to result in significant injury to the user. PRODUCT STATUS DEFINITIONS Definition of Terms Datasheet Identification Product Status Definition Advance Information Formative or In Design This datasheet contains the design specifications for product development. Specifications may change in any manner without notice. Preliminary First Production This datasheet contains preliminary data, and supplementary data will be published at a later date. Fairchild Semiconductor reserves the right to make changes at any time without notice in order to improve design. No Identification Needed Full Production This datasheet contains final specifications. Fairchild Semiconductor reserves the right to make changes at any time without notice in order to improve design. Obsolete Not In Production This datasheet contains specifications on a product that has been discontinued by Fairchild semiconductor. The datasheet is printed for reference information only. Rev. H1