Am7949 Subscriber Line Interface Circuit DISTINCTIVE CHARACTERISTICS n Ideal for Fiber-In-The-Loop (FITL) applications n Low standby power n –21 V to –58 V battery operation n On-chip battery switching and feed selection n On-hook transmission n Two-wire impedance set by single external n n n n n n n impedance Programmable constant-current feed Current gain = 200 Programmable loop-detect threshold Ground-key detector Tip Open state for ground-start lines Polarity reversal option On-chip ring relay driver and relay snubber circuit BLOCK DIAGRAM Ring Relay Driver A(TIP) RINGOUT C1 C2 HPA Input Decoder and Control C3 Ground-Key Detector Two-Wire Interface E1 DET HPB VTX Signal Transmission RSN Off-Hook Detector B(RING) RD Power-Feed Controller DA RDC CAS Ring-Trip Detector DB TESTIN VBAT2 BSW Test Relay Driver Switch Driver TESTOUT VBAT1 B2EN AS VCC VEE BGND AGND/DGND Publication# 080143 Rev: D Amendment: /0 Issue Date: October 1999 ORDERING INFORMATION Standard Products Legerity standard products are available in several packages and operating ranges. The order number (Valid Combination) is formed by a combination of the elements below. Am7949 –1 C J TEMPERATURE RANGE C = Commercial (0°C to 70°C)* PACKAGE TYPE J = 32-pin Plastic Leaded Chip Carrier (PL 032) PERFORMANCE GRADE OPTION –1 = 52 dB Long. Bal., Polarity Reversal –2 = 63 dB Long. Bal., Polarity Reversal –3 = 52 dB Long. Bal., No Polarity Reversal –4 = 63 dB Long. Bal., No Polarity Reversal DEVICE NUMBER/DESCRIPTION Am7949 Subscriber Line Interface Circuit Valid Combinations Valid Combinations Am7949 –1 –2 –3 –4 JC Valid Combinations list configurations planned to be supported in volume for this device. Consult the local Legerity sales office to confirm availability of specific valid combinations, to check on newly released combinations, and to obtain additional data on Legerity’s standard military–grade products. Note: * Functionality of the device from 0°C to +70°C is guaranteed by production testing. Performance from –40°C to +85°C is guaranteed by characterization and periodic sampling of production units. 2 Am7949 Data Sheet CONNECTION DIAGRAMS Top View VCC VBAT2 BGND B(RING) A(TIP) 4 3 2 1 32 31 30 DB NC 32-Pin PLCC 29 TP RINGOUT 6 28 DA BSW 7 27 RD NC 8 26 HPB VBAT1 9 25 HPA B2EN 10 24 VTX C2 11 23 VEE E1 12 22 RSN 21 AGND/DGND RDC 17 18 19 20 CAS 16 C1 DET 13 14 15 C3 TESTOUT TESTIN 5 AS TP Notes: 1. Pin 1 is marked for orientation. 2. TP is a thermal conduction pin tied to substrate. 3. NC = No Connect SLIC Products 3 PIN DESCRIPTIONS 4 Pin Names Type Description AGND/DGND Gnd Analog and Digital ground. AS Input Anti-saturation state select. Logic Low enables battery independent feed. Logic High enables battery tracking anti-sat. TTL compatible. A(TIP) Output B2EN Input VBAT2 Enable. Logic Low enables low power operation from VBAT2. Logic High enables operation from VBAT1. TTL compatible. BGND Gnd Battery (power) ground. B(RING) Output BSW Battery Switch C3–C1 Input CAS Capacitor DA Input Ring-Trip Negative; negative input to ring-trip comparator. DB Input Ring-Trip Positive; positive input to ring-trip comparator. DET Output Switchhook detector; a logic Low indicates that selected condition is detected. The detect condition is selected by the logic inputs (C3–C1 and E1). The output is open-collector with a built-in 15 kΩ pull-up resistor. E1 Input Ground-Key enable. A logic High selects the off-hook detector. A logic Low selects the ground key. TTL compatible. HPA Capacitor High-pass filter capacitor; A(TIP) side of high-pass filter capacitor. HPB Capacitor High-pass filter capacitor; B(RING) side of high-pass filter capacitor. NC ___ RD Resistor Detect resistor. Detector threshold set and filter pin. RDC Resistor DC feed resistor. Connection point for the DC feed current programming network, which also connects to the receiver summing node (RSN). The sign of VRDC is negative for normal polarity and positive for reverse polarity. RINGOUT Output RSN Input Receive summing node; the metallic current (both AC and DC) between A(TIP) and B(RING) is equal to 200 times the current into this pin. The networks that program receive gain, two-wire impedance, and feed resistance all connect to this node. TESTIN Input Test relay driver input. TESTOUT Output TP Thermal Thermal pin. Connection for heat dissipation. Internally connected to substrate (VBAT). Leave as open circuit or connected to VBAT. In both cases, the TP pins can connect to an area of copper on the board to enhance heat dissipation. VBAT1 Battery Battery supply and connection to substrate. VBAT2 Battery Power supply to output amplifiers. Connect externally to BSW. Connect to off-hook battery through a diode. VCC Power +5 V power supply. VEE Power –5 V power supply. VTX Output Transmit audio; this output is a unity gain version of the A(TIP) and B(RING) metallic voltage. VTX also sources the two-wire input impedance programming network. Output of A(TIP) power amplifier. Output of B(RING) power amplifier. Battery Switch. Collector of battery switch. Decoder. SLIC control pins. C3 is MSB and C1 is LSB. TTL compatible. Anti-saturation capacitor; pin for capacitor to filter reference voltage when operating in anti-saturation region. Pin not internally connected. Ring relay driver; open-collector driver with emitter internally connected to BGND. Open collector driver with emitter internally connected to AGND. Am7949 Data Sheet ABSOLUTE MAXIMUM RATINGS OPERATING RANGES Storage temperature . . . . . . . . . . . . –55°C to +150°C Commercial (C) Devices VCC with respect to AGND/DGND . . . –0.4 V to +7.0 V Ambient temperature . . . . . . . . . . . . . . 0°C to +70°C* VEE with respect to AGND/DGND . . . +0.4 V to –7.0 V VCC . . . . . . . . . . . . . . . . . . . . . . . . . . .4.75 V to 5.25 V VBAT2 with respect to VBAT1 . . . . . . . . . .VBAT1 to GND VEE . . . . . . . . . . . . . . . . . . . . . . . . .–4.75 V to –5.25 V VBAT1 with respect to AGND/DGND: Continuous . . . . . . . . . . . . . . . . . . +0.4 V to –70 V 10 ms . . . . . . . . . . . . . . . . . . . . . . +0.4 V to –75 V VBAT1 . . . . . . . . . . . . . . . . . . . . . . . . –40.5 V to –58 V BGND with respect to AGND/DGND . . . . +3 V to –3 V A(TIP) or B(RING) to BGND: Continuous . . . . . . . . . . . . . . . . . . . . –70 V to +1 V 10 ms (f = 0.1 Hz) . . . . . . . . . . . . . . . –70 V to +5 V 1 µs (f = 0.1 Hz) . . . . . . . . . . . . . . . . –80 V to +8 V 250 ns (f = 0.1 Hz) . . . . . . . . . . . . . –90 V to +12 V Current from A(TIP) or B(RING) . . . . . . . . . . . . ±150 mA RINGOUT current . . . . . . . . . . . . . . . . . . . . . . .50 mA RINGOUT voltage . . . . . . . . . . . . . . . . BGND to +7 V VBAT2 . . . . . . . . . . . . . . . . . . . . . . . . . –21 V to VBAT1 AGND/DGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 V BGND with respect to AGND/DGND. . . . . . . . . . . . –100 mV to +100 mV Load resistance on VTX to ground . . . . . . . 10 kΩ min Operating Ranges define those limits between which device functionality is guaranteed. * Functionality of the device from 0°C to +70°C is guaranteed by production testing. Performance from –40°C to +85°C is guaranteed by characterization and periodic sampling of production units. RINGOUT transient . . . . . . . . . . . . . . BGND to +10 V DA and DB inputs Voltage on ring-trip inputs . . . . . . . . . . .VBAT to 0 V Current into ring-trip inputs . . . . . . . . . . . . . . ±10 mA C3–C1, E1, AS, B2EN Input voltage . . . . . . . . . . . . .–0.4 V to VCC + 0.4 V Maximum power dissipation, continuous, TA = 85°C, No heat sink (See note): In 32-pin PLCC package. . . . . . . . . . . . . . . . 1.4 W Thermal Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . θJA In 32-pin PLCC package. . . . . . . . . . . . 43°C/W typ Note: Thermal limiting circuitry on chip will shut down the circuit at a junction temperature of about 165°C. The device should never be exposed to this temperature. Operation above 145°C junction temperature may degrade device reliability. See the SLIC Packaging Considerations for more information. Stresses above those listed under Absolute Maximum Ratings may cause permanent device failure. Functionality at or above these limits is not implied. Exposure to Absolute Maximum Ratings for extended periods may affect device reliability. SLIC Products 5 ELECTRICAL CHARACTERISTICS Description Test Conditions (See Note 1) Min Typ Max Unit Note 3 20 dB 1, 4, 7 Ω 4 +35 +40 mV — 4 20 Ω 4 Vpk 2a Vrms 2b dB 5 — Transmission Performance 2-wire return loss 200 Hz to 3.4 kHz (Test Circuit D) 26 ZVTX, Analog output impedance VVTX, Analog output offset voltage 0°C to +70°C –40°C to +85°C –35 –40 ZRSN, Analog input impedance 1 Overload level, 2-wire and 4-wire Active state 2.5 Overload level On-hook, RL = 600 Ω 0.88 THD (Total Harmonic Distortion) +3 dBm, BAT2 = –24 V THD, on-hook 0 dBm, RL = 600 Ω, BAT1 = –57.5 V –64 –50 –35.5 Longitudinal Performance (See Test Circuit D) Longitudinal to metallic L-T, L-4 200 Hz to 1 kHz normal polarity 0°C to +70°C normal polarity –40°C to +85°C reverse polarity –1, –3* –2, –4 –2, –4 –2, –4 52 63 58 54 1 kHz to 3.4 kHz normal polarity 0°C to +70°C normal polarity –40°C to +85°C reverse polarity –1, –3* –2, –4 –2, –4 –2, –4 52 58 54 54 Longitudinal signal generation 4-L 200 Hz to 800 Hz normal polarity 42 Longitudinal current per pin (A or B) Active or OHT state 12 Longitudinal impedance at A or B 0 to 100 Hz — — 4 — dB 18 — — 4 — mArms 35 Ω/pin Idle Channel Noise C-message weighted noise RL = 300 Ω DC RL = 300 Ω DC 0°C to +70°C –40°C to +85°C +7 +10 +12 dBrnC — 4 Psophometric weighted noise RL = 300 Ω DC RL = 300 Ω DC 0°C to +70°C –40°C to +85°C –83 –80 –78 dBmp — 4 0 0 +0.15 +0.20 Insertion Loss and Balance Return Signal (2- to 4-Wire, 4- to 2-Wire, and 4- to 4-Wire, See Test Circuits A and B) Gain accuracy over temperature 0 dBm, 1 kHz 0°C to +70°C –40°C to +85°C –0.15 –0.20 Gain accuracy over frequency 300 to 3400 Hz relative to 1 kHz 0°C to +70°C –40°C to +85°C –0.10 –0.15 +0.10 +0.15 Gain tracking +3 dBm to –55 dBm 0°C to +70°C relative to 0 dBm –40°C to +85°C –0.10 –0.15 +0.10 +0.15 –0.5 +0.5 Gain accuracy, OHT state Group delay 0 dBm, 1 kHz 3 Note: *P.G. = Performance Grade 6 Am7949 Data Sheet — 4 dB — 4 — 4 4 µs 1, 4, 7 ELECTRICAL CHARACTERISTICS (continued) Description Test Conditions (See Note 1) Min Typ Max 0.915IL IL 1.085IL 20 21.7 0.7IL IL Unit Note Line Characteristics IL, Loop current accuracy IL in constant-current region IL, Long loops, Active or OHT state RLDC = 600 Ω IL, Accuracy, Standby state V BAT – 3 V I L = --------------------------------RL + 1800 RL = 600 Ω ILLIM 1.3IL TA = 25°C mA 15 Active, A and B to GND OHT, A and B to GND 17.4 50 50 80 4 IL, Loop current, Open Circuit state RL = 0 100 IA, pin A leakage, Tip Open state RL = 0 100 IB, pin B current, Tip Open state B to GND B to VBAT1 + 6 V VA, Active, ground-start signaling A to –48 V = 7 kΩ, B to GND = 100 Ω –7.5 VAB, Open Circuit voltage VBAT1 = –51.6 V 42.8 30 30 µA mA –5 4 V Power Supply Rejection Ratio (VRIPPLE = 100 mVrms), Active Normal State VCC VEE VBAT 50 Hz to 3400 Hz 50 Hz to 3400 Hz 50 Hz to 3400 Hz 33 29 30 40 35 50 Effective internal resistance CAS pin to GND 85 170 255 35 70 dB 5 kΩ 4 Power Dissipation On-hook, Open Circuit state AS & B2EN = logic high On-hook, Standby state AS & B2EN = logic high 45 85 On-hook, OHT state AS & B2EN = logic high 120 220 On-hook, Active state AS & B2EN = logic high 160 230 Off-hook, Standby state AS & B2EN = logic low, RL = 600 Ω 860 1100 Off-hook, OHT state AS & B2EN = logic low, RL = 300 Ω 500 700 Off-hook, Active state AS & B2EN = logic low, RL = 300 Ω 500 700 ICC, On-hook VCC supply current Open Circuit state OHT state Standby state Active state, BAT1 = –50 V 2.0 5.3 2.3 5.5 3.0 7.5 3.5 8.0 IEE, On-hook VEE supply current Open Circuit state OHT state Standby state Active state, BAT1 = –50 V 0.82 2.0 1.1 2.0 2.0 3.5 2.0 4.0 IBAT, On-hook VBAT supply current Open Circuit state OHT state Standby state Active state, BAT1 = –50 V 0.45 2.2 0.8 2.8 1.0 4.0 2.0 4.0 mW Supply Currents, Battery = –58 V SLIC Products mA 7 ELECTRICAL CHARACTERISTICS (continued) Description Test Conditions (See Note 1) Min Typ Max Unit Note 1.0 mVrms 4 RFI Rejection RFI rejection 100 kHz to 30 MHz (See Figure E) Logic Inputs (C3–C1, E1, AS, and B2EN) VIH, Input High voltage C3–C1, E1, AS, B2EN TESTIN, IIH = 300 µA 2.0 4.5 V VIL, Input Low voltage 0.8 IIH, Input High current C3–C1, AS, B2EN –75 40 Input High current Input E1 –75 45 IIL, Input Low current C1, C2, C3, E1, AS B2EN –400 –600 µA Logic Output (DET) VOL, Output Low voltage IOUT = 0.8 mA, 15 kΩ to VCC VOH, Output High voltage IOUT = –0.1 mA, 15 kΩ to VCC 0.40 V 2.4 Ring-Trip Detector Input (DA, DB) Bias current Offset voltage Source resistance = 2 MΩ –500 –50 –50 0 +50 mV nA 2 5 10 kΩ Ground-Key Detector Thresholds Ground-key resistive threshold B to GND Ground-key current threshold B to GND 9 mA Loop Detector IT, Loop-detect threshold RD = 35.4 kΩ, IT = 375/RD 9.6 10.6 11.6 mA Relay Driver Output (RINGOUT/TESTOUT) VOL, On voltage, (RINGOUT) IOL = 30 mA +0.25 +0.4 VOL, On voltage, (TESTOUT) IOL = 30 mA, VTESTINmin = 4.0 V +0.6 +1.0 IOH, Off leakage VOH = +5 V Zener breakover IZ = 100 µA Zener On voltage IZ = 30 mA 6 V 100 µA V V 7.2 10 RELAY DRIVER SCHEMATICS TESTOUT RINGOUT AGND BGND 8 Am7949 Data Sheet 6 SWITCHING CHARACTERISTICS Symbol Parameter Test Conditions E1 Low to DET High (E0 = 1) tgkde E1 Low to DET Low (E0 = 1) Ground-Key Detect state RL open, RG connected (See Figure H) E1 High to DET Low (E0 = 1) tshde Temperature Ranges Min Typ Max 0°C to +70°C –40°C to +85°C 3.8 4.0 0°C to +70°C –40°C to +85°C 1.1 1.6 0°C to +70°C –40°C to +85°C 1.2 1.7 0°C to +70°C –40°C to +85°C 3.8 4.0 Unit Note µs 4 Switchhook Detect state E1 High to DET High (E0 = 1) SWITCHING WAVEFORMS E1 to DET E1 DET tgkde tshde tgkde tshde Notes: 1. Unless otherwise noted, test conditions are BAT1 = –52 V, BAT2 = –24 V, VCC = +5 V, VEE = –5 V, RL = 600 Ω, RDC1 = RDC2 = 10 kΩ, RD = 35.4 kΩ, no fuse resistors, CHP = 0.33 µF, CDC = 0.33 µF, CCAS = 0.33 µF, D1 = 1N400x, two-wire AC input impedance is a 600 Ω resistance synthesized by the programming network shown below. VTX RT1 = 60 kΩ CT1 = 150 pF RT2 = 60 kΩ RSN RRX = 60 kΩ ~ VRX 2. a. Overload level is defined when THD = 1%. b. Overload level is defined when THD = 1.5% 3. Balance return signal is the signal generated at VTX by VRX. This specification assumes the two-wire AC load impedance matches the programmed impedance. 4. Not tested in production. This parameter is guaranteed by characterization or correlation to other tests. 5. This parameter is tested at 1 kHz in production. Performance at other frequencies is guaranteed by characterization. 6. Tested with 0 Ω source impedance. 2 MΩ is specified for system design only. 7. Group delay can be greatly reduced by using a ZT network such as that shown in Note 1 above. The network reduces the group delay to less than 2 µs. The effect of group delay on the linecard performance may also be compensated for by synthesizing complex impedance with the QSLAC™ or DSLAC™ device. SLIC Products 9 Table 1. SLIC Decoding (DET) Output State C3 C2 C1 2-Wire Status E1 = 1 E1 = 0 Battery Selection 0 0 0 0 Open Circuit Ring trip Ring trip 1 0 0 1 Ringing Ring trip Ring trip 2 0 1 0 Active Loop detector Ground key 3 0 1 1 On-hook TX (OHT) Loop detector Ground key 4 1 0 0 Tip Open Loop detector Ground key B2EN = 1** 5 1 0 1 Standby Loop detector Ground key VBAT1 6* 1 1 0 Active Polarity Reversal Loop detector Ground key 7* 1 1 1 OHT Polarity Reversal Loop detector Ground key B2EN B2EN Notes: * Only –1 performance grade devices support polarity reversal. ** For correct ground-start operation using Tip Open, VBAT1 on-hook battery must be used. Table 2. Battery Switching Decoding AS B2EN Operation Status 0 0 Battery independent anti-sat, off-hook battery 1 0 Battery dependent anti-sat, off-hook battery 1 1 Battery dependent anti-sat, on-hook battery Note: BSW and VBAT2 are connected together externally. Table 3. User-Programmable Components ZT = 200 ( Z 2WIN – 2RF ) ZT is connected between the VTX and RSN pins. The fuse resistors are RF, and Z2WIN is the desired 2-wire AC input impedance. When computing ZT, the internal current amplifier pole and any external stray capacitance between VTX and RSN must be taken into account. ZL 200 • ZT Z RX = ------------ • -------------------------------------------------G 42L ZT + 200 ( ZL + 2RF ) ZRX is connected from VRX to RSN. ZT is defined above, and G42L is the desired receive gain. 500 R DC1 + R DC2 = -------------I LOOP RDC1, RDC2, and CDC form the network connected to the RDC pin. RDC1 and RDC2 are approximately equal. ILOOP is the desired loop current in the constant-current region. R DC1 + R DC2 C DC = 1.5 ms • -------------------------------R DC1 • R DC2 375 R D = --------- , IT 0.5 ms CD = -----------------RD 1 C CAS = ---------------------------5 3.4 • 10 π f c 10 RD and CD form the network connected from RD to –5 V and IT is the threshold current between on-hook and off-hook. CCAS is the regulator filter capacitor and fc is the desired filter cut-off frequency. Am7949 Data Sheet DC FEED CHARACTERISTICS 5 VBAT = 51.3 V VBAT = 47.3 V 3 2 7 3 4 2 6 1 RDC = 20 kΩ Notes: 1. Constant-current region: 500 I L = --------R DC V AB = 12.5 V, Low-Battery Anti-sat 2. Anti-sat turn-on point: 500 V AB = 1.01 V BAT – 7.51 – --------- , High-Battery Anti-sat, V BAT < 50.1 V 60 500 V AB = 0.338 V BAT + 26.0 – --------- , High-Battery Anti-sat, V BAT > 50.1 V 60 V AB = 16.7 V, Low-Battery Anti-sat 3. Open Circuit voltage: V AB = 1.01 V BAT – 7.51 , High-Battery Anti-sat, V BAT < 50.1 V V AB = 0.338 V BAT + 26.0 , High-Battery Anti-sat, V BAT > 50.1 V 4. Anti-sat region, Low battery state: R DC V AB = 16.7 – I L --------120 5. Anti-sat region, High battery state: R DC - , V BAT < 50.1 V V AB = 1.01 V BAT – 7.51 – I L --------60 R DC - , V BAT > 50.1 V V AB = 0.338 V BAT + 26.0 – I L --------60 6. Loop resistance at transition between High and Low battery states. 7. DC feed characteristic through High/Low battery transitions, High/Low battery states controlled by on/off-hook states. a. VA–VB (VAB) Voltage vs. Loop Current (Typical) SLIC Products 11 30 Loop Current (mA) 25 20 15 10 5 0 1000 2000 RDC = 20 kΩ VBAT: High = 51.3 V Low = 24 V 3000 Load Resistance 4000 5000 6000 (Ω ) b. Loop Current vs. Load Resistance (Typical) A a RL SLIC IL RSN RDC1 b RDC2 B RDC Feed current programmed by RDC1 and RDC2 c. Feed Programming Figure 1. DC Feed Characteristics 12 Am7949 Data Sheet CDC TEST CIRCUITS A(TIP) VTX VTX A(TIP) RL 2 SLIC VAB VL AGND RL 2 SLIC RT VAB RL RT AGND RRX RSN RRX B(RING) B(RING) RSN VRX IL2-4 = 20 log (VTX / VAB) IL4-2 = 20 log (VAB / VRX) BRS = 20 log (VTX / VRX) B. Four- to Two-Wire Insertion Loss and Balance Return Signal A. Two- to Four-Wire Insertion Loss 1 ωC << RL S1 A(TIP) A(TIP) VTX RL C 2 VL VL ZD VTX SLIC VAB AGND RL 2 RSN B(RING) AGND VM VS S2 RT1 R RT RRX VRX R SLIC ZIN CT1 RT2 RSN B(RING) S2 Open, S1 Closed L-T Long. Bal. = 20 log (VAB / VL) L-4 Long. Bal. = 20 log (VTX / VL) RRX S2 Closed, S1 Open 4-L Long. Sig. Gen. = 20 log (VL / VRX) Note: ZD is the desired impedance (e.g., the characteristic impedance of the line). RL = –20 log (2 VM / VS) D. Two-Wire Return Loss Test Circuit C. Longitudinal Balance SLIC Products 13 TEST CIRCUITS (continued) VCC 6.2 kΩ A(TIP) A(TIP) DET B(RING) 15 pF RL = 600 Ω RG B(RING) RG: 2 kΩ at VBAT = –48 V E1 E. Loop-Detector Switching F. Ground-Key Switching C1 L1 200 Ω RF1 50 Ω A(TIP) CAX 33 nF RF2 50 Ω 200 Ω B(RING) HF GEN 50 Ω L2 C2 CBX 33 nF VTX SLIC under test 1.5 Vrms 80% Amplitude Modulated 100 kHz to 30 MHz G. RFI Test Circuit 14 Am7949 Data Sheet TEST CIRCUITS (continued) –5 V +5 V VCC VEE DA RD DB RD 2.2 nF VTX VTX A(TIP) A(TIP) HPA CHP RT RSN VRX HPB B(RING) B(RING) 2.2 nF RRX RDC1 RDC2 RDC CDC RINGOUT AGND/ DGND BGND AS B2EN D1 VBAT1 BAT1 = –52 V E1 DET 0.1 µF VBAT2 BAT2 = –24 V 0.1 µF D2 C3 C2 C1 CAS BATTERY GROUND BSW CCAS ANALOG GROUND DIGITAL GROUND H. Am7949 Test Circuit SLIC Products 15 PHYSICAL DIMENSIONS PL032 .447 .453 .485 .495 .009 .015 .585 .595 .042 .056 .125 .140 Pin 1 I.D. .080 .095 .547 .553 SEATING PLANE .400 REF. .490 .530 .013 .021 .050 REF. .026 .032 TOP VIEW SIDE VIEW 16-038FPO-5 PL 032 DA79 6-28-94 ae REVISION SUMMARY Revision A to Revision B • Minor changes were made to the data sheet style and format to conform to Legerity standards. • Electrical Characteristics—Under Longitudinal Performance, the specifications for Longitudinal to Metallic moved from the Typ column to the Min column. • Electrical Characteristics—Under Line Characteristics (the last row) in the Test Conditions column, V BAT1 = 50 V changed to V BAT1 = 51.6 V. • SLIC Decoding Table—Added B2EN reference to the Battery Selection column and its corresponding note to the notes section. • DC Feed Characteristics—Added new equations and revised existing ones. Revision B to Revision C • Minor changes were made to the data sheet style and format to conform to Legerity standards. • In Pin Description table, inserted/changed TP pin description to: “Thermal pin. Connection for heat dissipation. Internally connected to substrate (VBAT). Leave as open circuit or connected to VBAT. In both cases, the TP pins can connect to an area of copper on the board to enhance heat dissipation.” Revision C to Revision D • The physical dimensions (PL032) were added to the Physical Dimensions section. • Deleted the Ceramic DIP and Plastic DIP packages and references to them. • Updated the Pin Description table to correct inconsistencies. 16 Am7949 Data Sheet Notes: www.legerity.com SLIC Products 17 Legerity provides silicon solutions that enhance the performance, speeds time-to-market, and lowers the system cost of our customers' products. By combining process, design, systems architecture, and a complete set of software and hardware support tools with unparalleled factory and worldwide field applications support, Legerity ensures its customers enjoy a smoother design experience. It is this commitment to our customers that places Legerity in a class by itself. The contents of this document are provided in connection with Legerity, Inc. products. Legerity makes no representations or warranties with respect to the accuracy or completeness of the contents of this publication and reserves the right to make changes to specifications and product descriptions at any time without notice. No license, whether express, implied, arising by estoppel or otherwise, to any intellectual property rights is granted by this publication. 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