ETC AS4C1M16E5-60JC

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• Organization: 1,048,576 words × 16 bits
• High speed
• 1024 refresh cycles, 16 ms refresh interval
- RAS-only or CAS-before-RAS refresh Read-modify-write
• TTL-compatible, three-state DQ
• JEDEC standard package and pinout
- 45/50/60 ns RAS access time
- 20/20/25 ns hyper page cycle time
- 10/12/15 ns CAS access time
- 400 mil, 42-pin SOJ
- 400 mil, 44/50-pin TSOP 2
• Low power consumption
- Active: 740 mW max (AS4C1M16E5-60)
- Standby: 5.5 mW max, CMOS DQ
• 5V power supply
• Industrial and commercial temperature available
• Extended data out
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62Vcc
DQ1
DQ2
DQ3
'4
Vcc
DQ5
DQ6
DQ7
DQ8
NC
NC
WE
RAS
NC
NC
A0
A1
A2
A3
Vcc
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
V66
DQ16
DQ15
DQ14
DQ13
V66
DQ12
DQ11
DQ10
DQ9
NC
LCAS
UCAS
OE
A9
A8
A7
A6
A5
A4
V66
V&&
DQ1
DQ2
DQ
DQ4
V&&
DQ5
DQ6
DQ7
DQ8
NC
1
2
3
4
5
6
7
8
9
10
11
50
49
48
47
46
45
44
43
42
41
40
V66
DQ16
DQ15
DQ14
DQ13
V66
DQ12
DQ11
DQ10
DQ9
NC
NC
NC
WE
RAS
NC
NC
A0
A1
A2
A3
V&&
15
16
17
18
19
20
21
22
23
24
25
36
35
34
33
32
31
30
29
28
27
26
NC
LCAS
UCAS
OE
A9
A8
A7
A6
A5
A4
V66
Pin(s)
Description
A0 to A9
Address inputs
RAS
Row address strobe
DQ1 to DQ16
Input/output
OE
Output enable
WE
Write enable
UCAS
Column address strobe, upper byte
LCAS
Column address strobe, lower byte
VCC
Power
VSS
Ground
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Symbol
-45
-50
-60
Unit
Maximum RAS access time
tRAC
45
50
60
ns
Maximum column address access time
tAA
23
25
30
ns
Maximum CAS access time
tCAC
10
12
15
ns
Maximum output enable (OE) access time
tOEA
12
13
15
ns
Minimum read or write cycle time
tRC
75
80
100
ns
Minimum hyper page mode cycle time
tHPC
20
20
25
ns
Maximum operating current
ICC1
155
145
135
mA
Maximum CMOS standby current
ICC5
2.0
2.0
2.0
mA
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The AS4C1M16E5 is a high performance 16-megabit CMOS Dynamic Random Access Memory (DRAM) organized as 1,048,576 words × 16
bits. The device is fabricated using advanced CMOS technology and innovative design techniques resulting in high speed, extremely low power
and wide operating margins at component and system levels. The Alliance 16Mb DRAM family is optimized for use as main memory in
personal and portable PCs, workstations, and multimedia and router switch applications.
The AS4C1M16E5 features hyper page mode operation where read and write operations within a single row (or page) can be executed at very
high speed by toggling column addresses within that row. Row and column addresses are alternately latched into input buffers using the falling
edge of RAS and xCAS inputs, respectively. Also, RAS is used to make the column address latch transparent, enabling application of column
addresses prior to xCAS assertion. The AS4C1M16E5 provides dual UCAS and LCAS for independent byte control of read and write access.
Extended data out (EDO), also known as 'hyper-page mode,' enables high speed operation. In contrast to 'fast-page mode' devices, data remains
active on outputs after xCAS is de-asserted high, giving system logic more time to latch the data. Use OE and WE to control output impedance
and prevent bus contention during read-modify-write and shared bus applications. Outputs also go to high impedance at the last occurrance of
RAS and xCAS going high.
Refresh on the 1024 address combinations of A0 to A9 must be performed every 16 ms using:
• RAS-only refresh: RAS is asserted while xCAS is held high. Each of the 1024 rows must be strobed. Outputs remain high impedence.
• Hidden refresh: xCAS is held low while RAS is toggled. Outputs remain low impedence with previous valid data.
• CAS-before-RAS refresh (CBR): At least one xCAS is asserted prior to RAS. Refresh address is generated internally.
Outputs are high-impedence (OE and WE are don't care).
• Normal read or write cycles refresh the row being accessed.
The AS4C1M16E5 is available in the standard 42-pin plastic SOJ and 44/50-pin TSOP 2 packages, respectively. The AS4C1M16E5 device
operates with a single power supply of 5V ± 0.5V and provides TTL compatible inputs and outputs.
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RAS
UCAS
LCAS
WE
RAS clock
generator
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
CAS clock
generator
WE clock
generator
Data
DQ
buffers
Column decoder
DQ1 to DQ16
Sense amp
OE
Row decoder
GND
Address buffers
Refresh
controller
VCC
1024 × 1024 × 16
Array
(16,777,216)
Substrate bias
generator
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Parameter
Supply voltage
Input voltage
Ambient operating temperature
Symbol
Min
Nominal
Max
Unit
VCC
4.5
5.0
5.5
V
GND
0.0
0.0
0.0
V
VIH
2.4
–
VCC
V
–0.5
–
0.8
V
0
–
70
-40
–
85
VIL
Commercial
Industrial
TA
†
°C
†V min -3.0V for pulse widths less than 5 ns.
IL
Recommended operating conditions apply throughout this document unless otherwise specified.
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Parameter
Symbol
Min
Max
Unit
Input voltage
Vin
-1.0
+7.0
V
Input voltage (DQs)
VDQ
-1.0
VCC + 0.5
V
Power supply voltage
VCC
-1.0
+7.0
V
Storage temperature (plastic)
TSTG
-65
+150
Soldering temperature × time
°C
o
TSOLDER
–
260 × 10
C × sec
Power dissipation
PD
–
1
W
Short circuit output current
Iout
–
50
mA
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Addresses
RAS
LCAS
UCAS
WE
OE
tR
tC
DQ0 to DQ15
Standby
H
H to X
H to X
X
X
X
X
High-Z
Word read
L
L
L
H
L
ROW
COL
Data out
Lower byte
read
L
L
H
H
L
ROW
COL
Lower byte,
Upper byte, Data out
Upper byte
read
L
H
L
H
L
ROW
COL
Lower byte,
Data out, Upper byte
Word
(early) write
L
L
L
L
X
ROW
COL
Data in
Lower byte
(early) write
L
L
H
L
X
ROW
COL
Lower byte, Data in,
Upper byte, High-Z
Upper byte
(early) write
L
H
L
L
X
ROW
COL
Lower byte, High-Z,
Upper byte, Data in
Read write
L
L
L
H to L
L to H
ROW
COL
Data out, Data in
1,2
1st cycle
L
H to L
H to L
H
L
ROW
COL
Data out
2
2nd cycle
L
H to L
H to L
H
L
n/a
COL
Data out
2
Any cycle
L
L to H
L to H
H
L
n/a
n/a
Data out
2
1st cycle
L
H to L
H to L
L
X
ROW
COL
Data in
1
EDO write
2nd cycle
L
H to L
H to L
L
X
n/a
COL
Data in
1
EDO
read write
1st cycle
L
H to L
H to L
H to L
L to H
ROW
COL
Data out, Data in
1,2
2nd cycle
L
H to L
H to L
H to L
L to H
n/a
COL
Data out, Data in
1,2
L
H
H
X
X
ROW
n/a
High Z
H to L
L
L
H
X
X
X
High Z
Operation
EDO read
RAS only
refresh
CBR refresh
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Parameter
Symbol Test conditions
-50
-60
Min
Max
Min
Max
Min
Max Unit Notes
Input leakage current
IIL
0V ≤ Vin ≤ VCC (max)
Pins not under test = 0V
-5
+5
-5
+5
-5
+5
µA
Output leakage
current
IOL
DOUT disabled, 0V ≤ Vout ≤ VCC
(max)
-5
+5
-5
+5
-5
+5
µA
Operating power
supply current
ICC1
RAS, UCAS, LCAS, Address cycling;
tRC=min
–
155
–
145
–
135
mA
TTL standby power
supply current
ICC2
RAS = UCAS = LCAS ≥ VIH,
all other inputs at VIH or VIL
–
2.0
–
2.0
–
2.0
mA
Average power supply
current, RAS refresh
mode or CBR
ICC3
RAS cycling, UCAS = LCAS ≥ VIH,
tRC = min of RAS low after XCAS
low.
–
145
–
135
–
125
mA
4
EDO page mode
average power supply
current
ICC4
RAS = VIL, UCAS or LCAS,
address cycling: tHPC = min
–
130
–
120
–
110
mA
4, 5
CMOS standby power
supply current
ICC5
RAS = UCAS = LCAS = VCC - 0.2V,
F=0
–
2.0
–
2.0
–
2.0
mA
VOH
IOUT = -5.0 mA
2.4
–
2.4
–
2.4
–
V
VOL
IOUT = 4.2 mA
–
0.4
–
0.4
–
0.4
V
ICC6
RAS, UCAS or LCAS cycling, tRC =
min
–
155
–
145
–
135
mA
Output voltage
CAS before RAS
refresh current
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-45
-50
-60
Symbol
Parameter
Min
Max
Min
Max
Min
Max
Unit
Notes
tRC
Random read or write cycle time
75
–
80
–
100
–
ns
tRP
RAS precharge time
30
–
30
–
40
–
ns
tRAS
RAS pulse width
45
10K
50
10K
60
10K
ns
tCAS
CAS pulse width
8
10K
8
10K
10
10K
ns
tRCD
RAS to CAS delay time
15
35
15
35
15
43
ns
9
tRAD
RAS to column address delay time
8
25
9
25
10
30
ns
10
tRSH
CAS to RAS hold time
10
–
10
–
10
–
ns
tCSH
RAS to CAS hold time
40
–
40
–
50
–
ns
tCRP
CAS to RAS precharge time
5
–
5
–
5
–
ns
tASR
Row address setup time
0
–
0
–
0
–
ns
tRAH
Row address hold time
8
–
8
–
10
–
ns
tT
Transition time (rise and fall)
1
50
1
50
1
50
ns
7,8
tREF
Refresh period
–
16
–
16
–
16
ms
6
tCP
CAS precharge time
8
–
8
–
10
–
ns
tRAL
Column address to RAS lead time
25
–
25
–
30
–
ns
tASC
Column address setup time
0
–
0
–
0
–
ns
tCAH
Column address hold time
8
–
8
–
10
–
ns
5HDGF\FOH
-45
Symbol
Parameter
tRAC
-50
-60
Min
Max
Min
Max
Min
Max
Unit
Access time from RAS
–
45
–
50
–
60
ns
9
tCAC
Access time from CAS
–
10
–
12
–
15
ns
9,16
tAA
Access time from address
–
23
–
25
–
30
ns
10,16
tRCS
Read command setup time
0
–
0
–
0
–
ns
tRCH
Read command hold time to CAS
0
–
0
–
0
–
ns
12
tRRH
Read command hold time to RAS
0
–
0
–
0
–
ns
12
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Symbol
Parameter
tWCS
-50
-60
Min
Max
Min
Max
Min
Max
Unit
Notes
Write command setup time
0
–
0
–
0
–
ns
14
tWCH
Write command hold time
10
–
10
–
10
–
ns
14
tWP
Write command pulse width
10
–
10
–
10
–
ns
tRWL
Write command to RAS lead time
10
–
10
–
10
–
ns
tCWL
Write command to CAS lead time
8
–
8
–
10
–
ns
tDS
Data-in setup time
0
–
0
–
0
–
ns
15
tDH
Data-in hold time
8
–
8
–
10
–
ns
15
5HDGPRGLI\ZULWHF\FOH
-45
-50
-60
Symbol
Parameter
Min
Max
Min
Max
Min
Max
Unit
Notes
tRWC
Read-write cycle time
105
–
113
–
135
–
ns
tRWD
RAS to WE delay time
65
–
67
–
77
–
ns
14
tCWD
CAS to WE delay time
30
–
32
–
35
–
ns
14
tAWD
Column address to WE delay time
40
–
42
–
47
–
ns
14
5HIUHVKF\FOH
-45
Symbol
Parameter
tCSR
-50
-60
Min
Max
Min
Max
Min
Max
Unit
CAS setup time (CAS-before-RAS)
5
–
5
–
5
–
ns
6
tCHR
CAS hold time (CAS-before-RAS)
8
–
8
–
10
–
ns
6
tRPC
RAS precharge to CAS hold time
0
–
0
–
0
–
ns
tCPT
CAS precharge time
(CBR counter test)
10
–
10
–
10
–
ns
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-50
-60
Symbol
Parameter
Min
Max
Min
Max
Min
Max
Unit
tCPWD
CAS precharge to WE delay time
45
–
45
–
52
–
ns
tCPA
Access time from CAS precharge
–
28
–
28
–
35
ns
tRASP
RAS pulse width
45
100K
50
100K
60
100K
ns
tDOH
Previous data hold time from CAS
5
–
5
–
5
–
ns
tREZ
Output buffer turn off delay from RAS
0
13
0
13
0
15
ns
tWEZ
Output buffer turn off delay from WE
0
13
0
13
0
15
ns
tOEZ
Output buffer turn off delay from OE
0
13
0
13
0
15
ns
tHPC
Hyper page mode cycle time
20
–
20
–
25
–
ns
tHPRWC
Hyper page mode RMW cycle
47
–
47
–
56
–
ns
tRHCP
RAS hold time from CAS
30
–
30
–
35
–
ns
Notes
16
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Symbol
Parameter
tCLZ
-50
-60
Min
Max
Min
Max
Min
Max
Unit
CAS to output in Low Z
0
–
0
–
0
–
ns
tROH
RAS hold time referenced to OE
8
–
8
–
10
–
ns
tOEA
OE access time
–
13
–
13
–
15
ns
tOED
OE to data delay
13
–
13
–
15
–
ns
tOEZ
Output buffer turnoff delay from OE
0
13
0
13
0
15
ns
tOEH
OE command hold time
10
–
10
–
10
–
ns
tOLZ
OE to output in Low Z
0
–
0
–
0
–
ns
tOFF
Output buffer turn-off time
0
13
0
13
0
15
ns
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Notes
11
11
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1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
Write cycles may be byte write cycles (either LCAS or UCAS active).
Read cycles may be byte read cycles (either LCAS or UCAS active).
One CAS must be active (either LCAS or UCAS).
ICC1, ICC3, ICC4, and ICC6 are dependent on frequency.
ICC1 and ICC4 depend on output loading. Specified values are obtained with the output open.
An initial pause of 200 µs is required after power-up followed by any 8 RAS cycles before proper device operation is achieved. In the case of an internal
refresh counter, a minimum of 8 CAS-before-RAS initialization cycles instead of 8 RAS cycles are required. 8 initialization cycles are required after extended
periods of bias without clocks (greater than 8 ms).
AC Characteristics assume tT = 2 ns. All AC parameters are measured with a load as described in AC test conditions below.
VIH (min) and VIL (max) are reference levels for measuring timing of input signals. Transition times are measured between VIH and VIL.
Operation within the tRCD (max) limit insures that tRAC (max) can be met. tRCD (max) is specified as a reference point only. If tRCD is greater than the specified tRCD (max) limit, then access time is controlled exclusively by tCAC.
Operation within the tRAD (max) limit insures that tRAC (max) can be met. tRAD (max) is specified as a reference point only. If tRAD is greater than the specified tRAD (max) limit, then access time is controlled exclusively by tAA.
Assumes three state test load (5 pF and a 380 Ω Thevenin equivalent).
Either tRCH or tRRH must be satisfied for a read cycle.
tOFF (max) defines the time at which the output achieves the open circuit condition; it is not referenced to output voltage levels. tOFF is referenced from rising edge of RAS or CAS, whichever occurs last.
tWCS, tWCH, tRWD, tCWD and tAWD are not restrictive operating parameters. They are included in the datasheet as electrical characteristics only.
If tWS ≥ tWS (min) and tWH ≥ tWH (min), the cycle is an early write cycle and data out pins will remain open circuit, high impedance, throughout the cycle.
If tRWD ≥ tRWD (min), tCWD ≥ tCWD (min) and tAWD ≥ tAWD (min), the cycle is a read-write cycle and the data out will contain data read from the selected
cell. If neither of the above conditions is satisfied, the condition of the data out at access time is indeterminate.
These parameters are referenced to CAS leading edge in early write cycles and to WE leading edge in read-write cycles.
Access time is determined by the longest of tCAA or tCAC or tCPA
tASC ≥ tCP to achieve tPC (min) and tCPA (max) values.
These parameters are sampled and not 100% tested.
These characteristics apply to AS4C1M16E5 5V devices.
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- Access times are measured with output reference levels of
VOH = 2.4V and VOL = 0.4V,
VIH = 2.4V and VIL = 0.8V
- Input rise and fall times: 2 ns
+5V
R1 = 828Ω
Dout
100 pF*
R2 = 295Ω
GND
Figure A: Equivalent output load
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tRAS
tRCD
tRSH
tRP
RAS
tCSH
tCRP
tCAH
tCAS
tASC
tRCS
UCAS
LCAS
tRAD
Address
tRAL
tRAH
tASR
Row address
Column address
tRRH
tRCH
WE
tROH
tWEZ
tROH
OE
tOEZ
tRAC
tAA
tOFF (see note 11)
tOEA
tCAC
tREZ
tCLZ
DQ
Data out
tOLZ
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tRC
tRAS
tRP
RAS
tRCD
tRSH
tCSH
tCRP
tCRP
tCAS
UCAS
tRPC
tCRP
LCAS
tRAH
tRAL
tRAD
tASC
tASR
Address
Row
tCAH
Column
tRCH
tRRH
tRCS
WE
tROH
tWEZ
OE
tOLZ
tRAC
tOEA
tREZ
tOEZ
tAA
tCAC
tCLZ
Upper DQ
tOFF
Data out
Lower DQ
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tRC
tRAS
tRP
RAS
tRCD
tRSH
tCSH
tCRP
tCRP
tCAS
LCAS
tCRP
tRPC
UCAS
tASC
tRAH
tRAL
tRAD
tASR
tCAH
Address
Row
Column
tRCH
tRRH
tRCS
WE
tROH
tWEZ
OE
Upper DQ
tRAC
tREZ
tOEA
tOLZ
tOEZ
tAA
tCAC
tOFF
tCLZ
Lower DQ
Data out
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tRC
tRAS
tRP
RAS
tCSH
tRSH
tCRP
tRCD
tCAS
UCAS,
tRAD
LCAS
tRAL
tASC
tASR
Address
tRAH
tCAH
Row address
Column address
tCWL
tRWL
tWP
tWCS
tWCH
WE
OE
tDS
DQ
Y
tDH
Data in
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tRAS
tRP
RAS
tASR
tRAD
tRAL
tRAH
Address
Row address
Column address
tCAH
tRSH
tASC
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tDS
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tRC
tRAS
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tRAL
tRAH
Row address
Column address
tCRP
tRPC
UCAS
tASC
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tCAH
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LCAS
tRWL
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tWCH
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tDS
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Y
tDH
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tRC
tRAS
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tRSH
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UCAS,
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tASR
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tRWL
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DQ
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tRC
tRAS
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Row address
Column address
tCSH
tRSH
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tCAH
tCRP
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tASC
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UCAS
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tCAH
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LCAS
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Upper DQ
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Lower DQ
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tRWC
tRAS
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Column address
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Upper input
tDS
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tRWC
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Row
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tCWL
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Upper input
Upper output
tOLZ
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tRAC
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Lower DQ
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36 35 34 33 32 31 30 29 28 27 26
50 49 48 47 46 45 44 43 42 41 40
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Min
Max
0.128 0.148
0.025
0.105 0.115
0.026 0.032
0.015 0.020
0.007 0.013
1.070 1.080
0.370 NOM
0.395 0.405
0.435 0.445
0.050 NOM
50-pin TSOP 2
Min
(mm)
TSOP 2
A
E He
15 16 17 18 19 20 21 22 23 24 25
1 2 3 4 5 6 7 8 9 10 11
d
l
A2
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A1
b
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1.2
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0.05
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0.95
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b
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0.45
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0.12
0.21
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20.85
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11.56
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RAS, UCAS, LCAS, WE, OE
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50 ns
60 ns
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AS4C1M16E5-50JI
AS4C1M16E5-60JC
AS4C1M16E5-60JI
TSOP 2, 400 mil, 44/50-pin
AS4C1M16E5-45TC
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Device number
RAS access time
Package:
Temperature range
J = 42-pin SOJ 400 mil
C=Commercial, 0°C to 70 °C
T = 44/50-pin TSOP 2 400 mil I=Industrial, -40°C to 85°C
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