SSM3J332R TOSHIBA Field-Effect Transistor Silicon P-Channel MOS Type (U-MOSVI) SSM3J332R ○Power Management Switch Applications +0.08 0.05 M A 144 mΩ (max) (@VGS = -1.8 V) 72.0 mΩ (max) (@VGS = -2.5 V) 50.0 mΩ (max) (@VGS = -4.5 V) 42.0 mΩ (max) (@VGS = -10 V) 0.42 -0.05 +0.08 0.17 -0.07 3 2.4±0.1 1.8-V drive Low ON-resistance: RDS(ON) = RDS(ON) = RDS(ON) = RDS(ON) = 1.8±0.1 • • Unit: mm 1 2 0.95 Absolute Maximum Ratings (Ta = 25°C) 0.95 2.9±0.2 Symbol Rating Drain-Source voltage VDSS -30 V Gate-Source voltage VGSS ± 12 V DC Drain current Pulse ID (Note 1) -6.0 IDP (Note 1,2) -24.0 PD (Note 3) Power dissipation A 1 t < 10s A Unit 0.8+0.08 -0.05 Characteristic 1: Gate 2: Source W 2 Channel temperature Tch 150 °C Storage temperature range Tstg −55 to 150 °C SOT-23F 3: Drain JEDEC ― Note: Using continuously under heavy loads (e.g. the application of high JEITA ― temperature/current/voltage and the significant change in TOSHIBA 2-3Z1A temperature, etc.) may cause this product to decrease in the reliability significantly even if the operating conditions (i.e. Weight: 11 mg (typ.) operating temperature/current/voltage, etc.) are within the absolute maximum ratings. Please design the appropriate reliability upon reviewing the Toshiba Semiconductor Reliability Handbook (“Handling Precautions”/“Derating Concept and Methods”) and individual reliability data (i.e. reliability test report and estimated failure rate, etc). Note 1: The channel temperature should not exceed 150°C during use. Note 2: PW ≤ 10μs,Duty ≤ 1% Note 3: Mounted on a FR4 board. (25.4 mm × 25.4 mm × 1.6 mm, Cu Pad: 645 mm2) Marking Equivalent Circuit (Top View) 3 3 KFJ 1 2 1 2 1 2010-11-11 SSM3J332R Electrical Characteristics (Ta = 25°C) Characteristic Drain-Source breakdown voltage Symbol Min Typ. Max Unit -30 ⎯ ⎯ V -22 ⎯ ⎯ V ⎯ ⎯ -1 μA V (BR) DSS ID = -10 mA, VGS = 0 V V (BR) DSX ID = -10 mA, VGS = 8 V Drain cut-off current IDSS Gate leakage current IGSS Gate threshold voltage Vth ⏐Yfs⏐ Forward transfer admittance Drain–source ON-resistance RDS (ON) Input capacitance Ciss Output capacitance Coss (Note 5) VDS = -30 V, VGS = 0 V VGS = ±10 V, VDS = 0 V VDS = -3 V, ID = -1 mA ⎯ ⎯ ±1 μA -0.5 ⎯ -1.2 V S VDS = -3 V, ID = -2.5 A (Note 4) 5.7 11.3 ⎯ ID = -5.0 A, VGS = -10 V (Note 4) ⎯ 36.0 42.0 ID = -4.0 A, VGS = -4.5 V (Note 4) ⎯ 42.5 50.0 ID = -2.5 A, VGS = -2.5 V (Note 4) ⎯ 57.5 72.0 ID = -0.5 A, VGS = -1.8 V (Note 4) ⎯ 76.5 144 ⎯ 560 ⎯ ⎯ 80 ⎯ VDS = -15 V, VGS = 0 V f = 1 MHz ⎯ 65 ⎯ Turn-on time ton VDD = -15 V, ID = -2.0 A ⎯ 15 ⎯ Turn-off time toff VGS = 0 to -4.5 V, RG = 10 Ω ⎯ 75 ⎯ ⎯ 8.2 ⎯ ⎯ 1.1 ⎯ Reverse transfer capacitance Switching time Test Conditions Crss Total Gate Charge Qg Gate-Source Charge Qgs1 Gate-Drain Charge Qgd Drain-Source forward voltage VDSF VDD = -15 V, ID = -6.0 A, VGS = -4.5 V ID = 6.0 A, VGS = 0 V (Note 4) ⎯ 2.2 ⎯ ⎯ 0.90 1.2 mΩ pF ns nC V Note4: Pulse test Note5: If a forward bias is applied between gate and source, this device enters V(BR)DSX mode. Note that the drain-source breakdown voltage is lowered in this mode. Switching Time Test Circuit (a) Test Circuit (b) VIN 0V 90% OUT 0 IN 10% −4.5 V RG −4.5V 10 μs RL (c) VOUT VDS (ON) 90% VDD VDD = -15 V RG = 10 Ω Duty ≤ 1% VIN: tr, tf < 5 ns Common Source Ta = 25°C 10% VDD tr ton tf toff Notice on Usage Let Vth be the voltage applied between gate and source that causes the drain current (ID) to be low (-1 mA for the SSM3J332R). Then, for normal switching operation, VGS(on) must be higher than Vth, and VGS(off) must be lower than Vth. This relationship can be expressed as: VGS(off) < Vth < VGS(on). Take this into consideration when using the device. Handling Precaution When handling individual devices that are not yet mounted on a circuit board, make sure that the environment is protected against electrostatic discharge. Operators should wear antistatic clothing, and containers and other objects that come into direct contact with devices should be made of antistatic materials. Thermal resistance Rth (ch-a) and power dissipation PD vary depending on board material, board area, board thickness and pad area. When using this device, please take heat dissipation into consideration 2 2010-11-11 SSM3J332R ID – VDS -10 -4.5 V VGS =-10 V ID – VGS -100 -2.5 V Common Source -1 ID Drain current Drain current -6 -4 -2 Common Source Ta = 25 °C Pulse test 0 -0.2 -0.6 -0.4 -0.8 Drain–source voltage VDS Pulse test (A) (A) ID -1.8 V 0 VDS = -3 V -10 -8 -0.1 Ta = 100 °C -0.01 -0.0001 0 -1 −25 °C 25 °C -0.001 -0.5 (V) -1.5 Gate–source voltage RDS (ON) – VGS VGS -2.0 (V) RDS (ON) – VGS 200 200 ID = -0.5 A Common Source Pulse test Drain–source ON-resistance RDS (ON) (mΩ) Drain–source ON-resistance RDS (ON) (mΩ) -1.0 150 100 25 °C Ta = 100 °C 50 ID = -2.5 A Common Source Pulse test 150 100 25 °C Ta = 100 °C 50 − 25 °C 0 0 -4 -2 -6 Gate–source voltage -10 -8 VGS − 25 °C 0 -12 0 (V) -2 -4 Drain–source ON-resistance RDS (ON) (mΩ) Drain–source ON-resistance RDS (ON) (mΩ) -1.8 V Pulse test -12 -10 VGS (V) RDS (ON) – Ta 200 Common Source Ta = 25 °C -8 Gate–source voltage RDS (ON) – ID 200 -6 150 100 -2.5 V 50 -10 V Common Source Pulse test 150 ID = -0.5 A / VGS = -1.8 V -2.5 A / -2.5 V 100 -4.0 A / -4.5 V 50 -5.0 A / -10 V -4.5 V 0 0 -2.0 -4.0 Drain current -8.0 -6.0 ID 0 −50 -10.0 0 50 Ambient temperature (A) 3 100 Ta 150 (°C) 2010-11-11 SSM3J332R Vth – Ta (S) -0.8 30 Common Source VDS = -3 V Ta = 25 °C Pulse test Forward transfer admittance Vth (V) Gate threshold voltage Common Source VDS = -3 V ID = -1 mA 100 ⎪Yfs⎪ |Yfs| – ID -1.0 -0.6 -0.4 -0.2 0 −50 50 0 100 Ambient temperature Ta 150 10 3.0 1.0 0.3 0.1 -0.01 -0.1 Drain current (°C) C – VDS 10000 -1 -10 ID -100 (A) Dynamic Input Characteristic -12 500 VGS (V) C 1000 Ciss 300 100 Coss 50 Common Source 30 Ta = 25 °C f = 1 MHz VGS = 0 V Crss -1 -10 Drain–source voltage -100 VDS -4 -2 0 (A) 10 IDR Drain reverse current tf Common Source ID = -6.0 A Ta = 25 °C 10 ton tr - -0.01 -0.1 Drain current Qg 30 (nC) Common Source VGS = 0 V Pulse test D IDR G S 1 0.1 25 °C 0.01 100 °C 1 -0.001 20 IDR – VDS t Switching time -6 100 100 10 VDD = -24 V Total Gate Charge Common Source VDD = -15 V VGS = 0 to -4.5 V Ta = 25 °C RG = 10Ω toff VDD = -15 V -8 (V) t – ID 10000 1000 -10 0 10 -0.1 (ns) Gate–source voltage (pF) 3000 Capacitance 5000 -1 ID 0.001 0 -10 0.2 −25 °C 0.4 0.6 Drain–source voltage (A) 4 0.8 VDS 1.0 1.2 (V) 2010-11-11 SSM3J332R Rth – tw PD – Ta 1000 (25.4mm × 25.4mm × 1.6mm , Cu Pad : 645 mm2) b: Mounted on FR4 board (25.4mm × 25.4mm × 1.6mm , Cu Pad : 0.72 mm2 ×3) (mW) b a 1200 a PD 100 Power dissipation Transient thermal impedance Rth (°C/W ) 1600 a: Mounted on FR4 board 10 Single pulse a. Mounted on FR4 board (25.4 mm × 25.4 mm × 1.6 mm, Cu Pad: 645 mm2) b. Mounted on FR4 board (25.4 mm × 25.4 mm × 1.6 mm, Cu Pad: 0.72 mm2×3) 1 0.001 0.01 0.1 1 Pulse width 10 tw 100 800 400 0 -40 1000 b -20 0 20 40 60 80 Ambient temperature (s) 5 100 Ta 120 140 160 (°C) 2010-11-11 SSM3J332R RESTRICTIONS ON PRODUCT USE • Toshiba Corporation, and its subsidiaries and affiliates (collectively “TOSHIBA”), reserve the right to make changes to the information in this document, and related hardware, software and systems (collectively “Product”) without notice. • This document and any information herein may not be reproduced without prior written permission from TOSHIBA. Even with TOSHIBA’s written permission, reproduction is permissible only if reproduction is without alteration/omission. • Though TOSHIBA works continually to improve Product’s quality and reliability, Product can malfunction or fail. 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