DATA SHEET MOS FIELD EFFECT TRANSISTOR 3SK254 RF AMPLIFIER FOR CATV TUNER N-CHANNEL Si DUAL GATE MOS FIELD-EFFECT TRANSISTOR 4 PINS SUPER MINI MOLD FEATURES PACKAGE DIMENSIONS (VDS = 3.5 V) (Unit: mm) • Driving Battery 2.1±0.2 NF1 = 2.0 dB TYP. (f = 470 MHz) 0.3 +0.1 –0.05 • Low Noise Figure : NF2 = 0.8 dB TYP. (f = 55 MHz) GPS = 19.0 dB TYP. (f = 470 MHz) 1.25±0.1 2 • High Power Gain : 0.3 +0.1 –0.05 : 3 • Low VDD Use (1.3) 4 Pins Super Mini Mold : 0.65 • Small Package 0.60 Embossed Type Taping 1.25 • Automatically Mounting : 2.0±0.2 • Suitable for use as RF amplifier in CATV tuner. V Gate1 to Drain Voltage VG1D 18 V Gate2 to Drain Voltage VG2D 18 V Drain Current ID 25 mA Total Power Dissipation PD 130*2 mW Channel Temperature Tch 125 °C Storage Temperature Tstg –55 to +125 °C 0.3 +0.1 –0.05 ±8*1 PIN CONNECTIONS 1. 2. 3. 4. *1: RL ≥ 10 kΩ *2: Free air 0.15 +0.1 –0.05 VG1S VG2S 4 V Gate1 to Source Voltage Gate2 to Source Voltage 0 to 0.1 V ±8*1 0.4 +0.1 –0.05 18 0.3 VDSX 0.9±0.1 Drain to Source Voltage 1 ABSOLUTE MAXIMUM RATINGS (TA = 25 °C) Source Drain Gate2 Gate1 PRECAUTION: Avoid high static voltages or electric fields so that this device would not suffer from any damage due to those voltage or fields. The information in this document is subject to change without notice. Before using this document, please confirm that this is the latest version. Not all devices/types available in every country. Please check with local NEC Compound Semiconductor Devices representative for availability and additional information. Document No. PU10033EJ01V0DS (1st edition) (Previous No. P10585EJ2V0DS00) Date Published October 2001 CP(K) Printed in Japan The mark shows major revised points. NEC Corporation 1993 NEC Compound Semiconductor Devices 2001 3SK254 ELECTRICAL CHARACTERISTICS (TA = 25 °C) CHARACTERISTIC SYMBOL MIN. Drain to Source Breakdown Voltage BVDSX 18 Drain Current IDSX 0.1 Gate1 to Source Cutoff Voltage VG1S(off) –1.0 Gate2 to Source Cutoff Voltage VG2S(off) 0 Gate1 Reverse Current TYP. MAX. UNIT V VG1S = VG2S = –2 V, ID = 10 µA 5.0 mA 0 +1.0 V VDS = 3.5 V, VG2S = 3 V, ID = 10 µA 0.5 1.0 V VDS = 3.5 V, VG1S = 3 V, ID = 10 µA IG1SS ±20 nA VDS = 0, VG2S = 0, VG1S = ±6 V Gate2 Reverse Current IG2SS ±20 nA VDS = 0, VG1S = 0, VG2S = ±6 V Forward Transfer Admittance |yfs| 14 18 23 mS VDS = 3.5 V, VG2S = 3 V, ID = 7 mA f = 1 kHz Input Capacitance Ciss 2.4 2.9 3.4 pF Output Capacitance Coss 0.9 1.2 1.5 pF Reverse Transfer Capacitance Crss 0.01 0.03 pF Power Gain Gps 19 22 dB VDS = 3.5 V, VG2S = 3 V, ID = 7 mA 16 VDS = 3.5 V, VG2S = 3 V, VG1S = 0.5 V VDS = 3.5 V, VG2S = 3 V, ID = 7 mA f = 1 MHz Noise Figure 1 NF1 2.0 3.0 dB f = 470 MHz Noise Figure 2 NF2 0.8 2.3 dB VDS = 3.5 V, VG2S = 3 V, ID = 7 mA f = 55 MHz IDSX Classification 2 TEST CONDITIONS Rank U1E Marking U1E IDSX (mA) 0.1 to 5.0 Data Sheet PU10033EJ01V0DS 3SK254 TYPICAL CHARACTERISTICS (TA = 25 ˚C) DRAIN CURRENT vs. DRAIN TO SOURCE VOLTAGE TOTAL POWER DISSIPATION vs. AMBIENT TEMPERATURE 100 20 1.4 V 15 1.2 V 1.0 V 10 0.8 V 5 0.6 V 25 50 75 100 10 VDS – Drain to Source Voltage – V DRAIN CURRENT vs. GATE1 TO SOURCE VOLTAGE FORWARD TRANSFER ADMITTANCE vs. GATE1 TO SOURCE VOLTAGE VDS = 3.5 V 3.0 V VG2S = 3.5 V 2.5 V 2.0 V 15 10 1.5 V 5 1.0 V 0.5 1.0 1.5 2.0 2.5 40 VDS = 3.5 V f = 1 kHz 32 VG2S = 3.5 V 24 3.0 V 16 2.0 V 2.5 V 8 1.0 V 0 0.5 1.5 V 1.0 1.5 2.0 VG1S – Gate1 to Source Voltage – V VG1S – Gate1 to Source Voltage – V FORWARD TRANSFER ADMITTANCE vs. DRAIN CURRENT INPUT CAPACITANCE vs. GATE2 TO SOURCE VOLTAGE 40 2.5 5.0 VDS = 3.5 V f = 1 kHz 32 VG2S = 3.5 V 24 3.0 V 16 2.5 V 8 2.0 V 1.5 V 1.0 V 0 5 Ta – Ambient Temperature – °C 20 0 0 125 |yfs| – Forward Transfer Admittance – mS 25 ID – Drain Current – mA ID – Drain Current – mA 130 mW 0 |yfs| – Forward Transfer Admittance – mS VG2S = 3 V VG1S = 1.6 V 200 Ciss – Input Capacitance – pF PD – Total Power Dissipation – mW 25 4 8 12 16 20 ID – Drain Current – mA 4.0 ID = 7 mA (at VDS = 3.5 V, VG2S = 3 V) f = 1 MHz 3.0 2.0 1.0 0 –1.0 0 1.0 2.0 3.0 4.0 VG2S – Gate2 to Source Voltage – V Data Sheet PU10033EJ01V0DS 3 3SK254 OUTPUT CAPACITANCE vs. GATE2 TO SOURCE VOLTAGE POWER GAIN AND NOISE FIGURE vs. GATE2 TO SOURCE VOLTAGE 10 ID = 7 mA (at VDS = 3.5 V, VG2S = 3.0 V) f = 1 MHz 1.5 1.0 0.5 5 GPS – Power Gain – dB 2.0 20 NF – Noise Figure – dB Coss – Output Capacitance – pF 2.5 ID = 7 mA (at VDS = 3.5 V, VG2S = 3.0 V) f = 470 MHz 10 0 –10 NF –20 0 –1.0 0 1.0 2.0 3.0 4.0 0 –1.0 VG2S – Gate2 to Source Voltage – V 4 GPS 0 1.0 2.0 3.0 VG2S – Gate2 to Source Voltage – V Data Sheet PU10033EJ01V0DS 4.0 3SK254 GPS AND NF TEST CIRCUIT AT f = 470 MHz VG2S 1 000 pF 22 kΩ 1 000 pF Ferrite Beads INPUT 40 pF 40 pF OUTPUT L2 L1 50 Ω 15 pF 1 000 pF 1 000 pF 15 pF 50 Ω 22 kΩ L3 1 000 pF 1 000 pF VDS VG1S L1: φ 1.2 mm U.E.W φ 5 mm 1T L2: φ 1.2 mm U.E.W φ 5 mm 1T L3: REC 2.2 µ H NF TEST CIRCUIT AT f = 55 MHz VG2S VDS RFC 2.2 kΩ Ferrite Beads 1 500 pF 1 500 pF 1 000 pF INPUT 50 Ω 3.3 kΩ 27 pF 47 kΩ 47 kΩ 1 000 pF 27 pF OUTPUT 3.3 kΩ 50 Ω VG1S Data Sheet PU10033EJ01V0DS 5 3SK254 • The information in this document is current as of October, 2001. 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