54F/74F299 Octal Universal Shift/Storage Register with Common Parallel I/O Pins General Description Features The ’F299 is an 8-bit universal shift/storage register with TRI-STATEÉ outputs. Four modes of operation are possible: hold (store), shift left, shift right and load data. The parallel load inputs and flip-flop outputs are multiplexed to reduce the total number of package pins. Additional outputs, Q0 – Q7, are provided to allow easy serial cascading. A separate active LOW Master Reset is used to reset the register. Y Commercial Package Number Military Y Y Y Y Common parallel I/O for reduced pin count Additional serial inputs and outputs for expansion Four operating modes: shift left, shift right, load and store TRI-STATE outputs for bus-oriented applications Guaranteed 4000V minimum ESD protection Package Description N20A 20-Lead (0.300× Wide) Molded Dual-In-Line J20A 20-Lead Ceramic Dual-In-Line 74F299SC (Note 1) M20B 20-Lead (0.300× Wide) Molded Small Outline, JEDEC 74F299SJ (Note 1) M20D 20-Lead (0.300× Wide) Molded Small Outline, EIAJ 54F299FM (Note 2) W20A 20-Lead Cerpack 54F299LM (Note 2) E20A 20-Lead Ceramic Leadless Chip Carrier, Type C 74F299PC 54F299DM (Note 2) Note 1: Devices also available in 13× reel. Use suffix e SCX and SJX. Note 2: Military grade device with environmental and burn-in processing. Use suffix e DMQB, FMQB and LMQB. Logic Symbols IEEE/IEC TL/F/9515 – 1 TL/F/9515 – 4 TRI-STATEÉ is a registered trademark of National Semiconductor Corporation. C1995 National Semiconductor Corporation TL/F/9515 RRD-B30M75/Printed in U. S. A. 54F/74F299 Octal Universal Shift/Storage Register with Common Parallel I/O Pins May 1995 Connection Diagrams Pin Assignment for DIP, SOIC and Flatpak Pin Assignment for LCC TL/F/9515 – 3 TL/F/9515–2 Unit Loading/Fan Out 54F/74F Pin Names Description U.L. HIGH/LOW Input IIH/IIL Output IOH/IOL CP DS0 DS7 S0, S1 MR OE1, OE2 I/O0 – I/O7 Clock Pulse Input (Active Rising Edge) Serial Data Input for Right Shift Serial Data Input for Left Shift Mode Select Inputs Asynchronous Master Reset Input (Active LOW) TRI-STATE Output Enable Inputs (Active LOW) Parallel Data Inputs or TRI-STATE Parallel Outputs Serial Outputs 1.0/1.0 1.0/1.0 1.0/1.0 1.0/2.0 1.0/1.0 1.0/1.0 3.5/1.083 150/40(33.3) 50/33.3 20 mA/b0.6 mA 20 mA/b0.6 mA 20 mA/b0.6 mA 20 mA/b1.2 mA 20 mA/b0.6 mA 20 mA/b0.6 mA 70 mA/b0.65 mA b 3 mA/24 mA (20 mA) b 1 mA/20 mA Q0, Q7 Functional Description A HIGH signal on either OE1 or OE2 disables the TRISTATE buffers and puts the I/O pins in the high impedance state. In this condition the shift, hold, load and reset operations can still occur. The TRI-STATE outputs are also disabled by HIGH signals on both S0 and S1 in preparation for a parallel load operation. The ’F299 contains eight edge-triggered D-type flip-flops and the interstage logic necessary to perform synchronous shift left, shift right, parallel load and hold operations. The type of operation is determined by S0 and S1, as shown in the Mode Select Table. All flip-flop outputs are brought out through TRI-STATE buffers to separate I/O pins that also serve as data inputs in the parallel load mode. Q0 and Q7 are also brought out on other pins for expansion in serial shifting of longer words. A LOW signal on MR overrides the Select and CP inputs and resets the flip-flops. All other state changes are initiated by the rising edge of the clock. Inputs can change when the clock is in either state provided only that the recommended setup and hold times, relative to the rising edge of CP, are observed. Mode Select Table Inputs Response MR S1 S0 CP L H H H H X X X Asynchronous Reset; Q0 –Q7 e LOW H H L Parallel Load; I/On x Qn L H L Shift Right; DS0 x Q0, Q0 x Q1, etc. H L L Shift Left; DS7 x Q7, Q7 x Q6, etc. L L X Hold H e HIGH Voltage Level L e LOW Voltage Level X e Immaterial L e LOW-to-HIGH Clock Transition 2 Logic Diagram TL/F/9515 – 5 Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays. 3 Absolute Maximum Ratings (Note 1) Voltage Applied to Output in HIGH State (with VCC e 0V) b 0.5V to VCC Standard Output b 0.5V to a 5.5V TRI-STATE Output Current Applied to Output in LOW State (Max) twice the rated IOL (mA) If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/Distributors for availability and specifications. Storage Temperature b 65§ C to a 150§ C Ambient Temperature under Bias Junction Temperature under Bias Plastic b 55§ C to a 125§ C VCC Pin Potential to Ground Pin b 55§ C to a 175§ C b 55§ C to a 150§ C Recommended Operating Conditions b 0.5V to a 7.0V Free Air Ambient Temperature Military Commercial b 0.5V to a 7.0V Input Voltage (Note 2) Input Current (Note 2) ESD Last Passing Voltage (Min) b 30 mA to a 5.0 mA 4000V b 55§ C to a 125§ C 0§ C to a 70§ C Supply Voltage Military Commercial Note 1: Absolute maximum ratings are values beyond which the device may be damaged or have its useful life impaired. Functional operation under these conditions is not implied. a 4.5V to a 5.5V a 4.5V to a 5.5V Note 2: Either voltage limit or current limit is sufficient to protect inputs. DC Electrical Characteristics Symbol 54F/74F Parameter Min VIH Input HIGH Voltage VIL Input LOW Voltage VCD Input Clamp Diode Voltage VOH Output HIGH Voltage VOL Typ Units 2.0 54F 10% VCC 54F 10% VCC 74F 10% VCC 74F 10% VCC 74F 5% VCC 74F 5% VCC VCC Conditions Max V Recognized as a HIGH Signal 0.8 V Recognized as a LOW Signal b 1.2 V 2.5 2.4 2.5 2.4 2.7 2.7 Min IIN e b18 mA V Min IOH IOH IOH IOH IOH IOH e e e e e e b 1 mA (Q0, Q7, I/On) b 3 mA (I/On) b 1 mA (Q0, Q7, I/On) b 3 mA (I/On) b 1 mA (Q0, Q7, I/On) b 3 mA (I/On) Output LOW Voltage 54 10% VCC 74 10% VCC 74 10% VCC 0.5 0.5 0.5 V Min IOL e 20 mA IOL e 20 mA (Q0, Q7) IOL e 24 mA (I/On) IIH Input HIGH Current 54F 74F 20.0 5.0 mA Max VIN e 2.7V (CP, DS0, DS7, S0, S1, MR, OE1, OE2) IBVI Input HIGH Current Breakdown Test 54F 74F 100 7.0 mA Max VIN e 7.0V (CP, DS0, DS7, S0, S1, MR, OE1, OE2) IBVIT Input HIGH Current Breakdown Test (I/O) 54F 74F 1.0 0.5 mA Max VIN e 5.5V (I/On) ICEX Output HIGH Leakage Current 54F 74F 250 50 mA Max VOUT e VCC VID Input Leakage Test 74F V 0.0 IID e 1.9 mA All Other Pins Grounded IOD Output Leakage Circuit Current 74F 3.75 mA 0.0 VIOD e 150 mV All Other Pins Grounded IIL Input LOW Current b 0.6 b 1.2 mA Max VIN e 0.5V (CP, DS0, DS7, MR, OE1, OE2) VIN e 0.5V (S0, S1) IIH a IOZH Output Leakage Current 70 mA Max VI/O e 2.7V (I/On) IIL a IOZL Output Leakage Current b 650 mA Max VI/O e 0.5V (I/On) IOS Output Short-Circuit Current b 150 mA Max VOUT e 0V IZZ Bus Drainage Test 500 mA 0.0V VOUT e 5.25V ICCH Power Supply Current 68 95 mA Max VO e HIGH ICCL Power Supply Current 68 95 mA Max VO e LOW ICCZ Power Supply Current 68 95 mA Max VO e HIGH Z 4.75 b 60 4 AC Electrical Characteristics Symbol Parameter 74F 54F 74F TA e a 25§ C VCC e a 5.0V CL e 50 pF TA, VCC e Mil CL e 50 pF TA, VCC e Com CL e 50 pF Max Min Max Min Units Min Typ fmax Maximum Input Frequency 70 100 tPLH tPHL Propagation Delay CP to Q0 or Q7 4.0 4.5 7.0 6.5 8.0 8.0 4.0 4.5 9.0 9.5 4.0 4.5 8.5 8.5 tPLH tPHL Propagation Delay CP to I/On 3.5 4.0 7.0 8.5 9.0 9.0 3.5 4.0 10.0 11.0 3.5 4.0 10.0 10.0 tPHL Propagation Delay MR to Q0 or Q7 5.5 7.5 9.5 5.5 12.5 5.5 10.5 tPHL Propagation Delay MR to I/On 5.5 11.0 10.0 5.5 12.0 5.5 10.5 tPZH tPZL Output Enable Time OE to I/On 3.5 4.0 6.0 7.0 8.0 10.0 3.0 4.0 9.5 13.0 3.5 4.0 9.0 11.0 tPHZ tPLZ Output Disable Time OE to I/On 2.0 1.0 4.5 4.0 6.0 5.5 1.5 1.0 7.0 6.5 2.0 1.0 7.0 6.5 tPZH tPZL Output Enable Time Sn to I/On 3.5 4.0 9.0 10.0 3.0 4.0 10.5 13.0 3.5 4.0 10.0 11.0 ns tPHZ tPLZ Output Disable Time Sn to I/On 2.5 1.5 6.0 5.5 1.5 1.0 7.0 6.5 2.5 1.5 7.0 6.5 ns 85 Max 70 MHz ns ns ns AC Operating Requirements Symbol Parameter 74F 54F 74F TA e a 25§ C VCC e a 5.0V TA, VCC e Mil TA, VCC e Com Min Min Min Max Max ts(H) ts(L) Setup Time, HIGH or LOW S0 or S1 to CP 8.5 8.5 10.0 7.5 8.5 8.5 th(H) th(L) Hold Time, HIGH or LOW S0 or S1 to CP 0 0 0 0 0 0 ts(H) ts(L) Setup Time, HIGH or LOW I/On, DS0 or DS7 to CP 5.0 5.0 5.0 5.0 5.0 5.0 th(H) th(L) Hold Time, HIGH or LOW I/On, DS0 or DS7 to CP 2.0 2.0 2.0 2.0 2.0 2.0 tw(H) tw(L) CP Pulse Width HIGH or LOW 5.0 5.0 5.0 5.0 5.0 5.0 Units Max ns ns ns tw(L) MR Pulse Width, LOW 5.0 6.0 5.0 ns trec Recovery Time, MR to CP 7.0 12.0 7.0 ns 5 Ordering Information The device number is used to form part of a simplified purchasing code where the package type and temperature range are defined as follows: 74F 299 S Temperature Range Family 74F e Commercial 54F e Military C X Special Variations QB e Military grade device with environmental and burn-in processing X e Devices shipped in 13× reel Device Type Package Code P e Plastic DIP D e Ceramic DIP S e Small Outline SOIC JEDEC SJ e Small Outline SOIC EIAJ F e Flatpak L e Leadless Chip Carrier (LCC) Temperature Range C e Commercial (0§ C to a 70§ C) M e Military (b55§ C to a 125§ C) Physical Dimensions inches (millimeters) 20-Lead Ceramic Leadless Chip Carrier (L) NS Package Number E20A 6 Physical Dimensions inches (millimeters) (Continued) 20-Lead Ceramic Dual-In-Line Package (D) NS Package Number J20A 20-Lead (0.300× Wide) Molded Small Outline Package, JEDEC (S) NS Package Number M20B 7 Physical Dimensions inches (millimeters) (Continued) 20-Lead (0.300× Wide) Molded Small Outline Package, EIAJ (SJ) NS Package Number MD20D 20-Lead (0.300× Wide) Molded Dual-In-Line Package (P) NS Package Number N20A 8 9 54F/74F299 Octal Universal Shift/Storage Register with Common Parallel I/O Pins Physical Dimensions inches (millimeters) (Continued) 20-Lead Cerpack NS Package Number W20A LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. National Semiconductor Corporation 2900 Semiconductor Drive P.O. Box 58090 Santa Clara, CA 95052-8090 Tel: 1(800) 272-9959 TWX: (910) 339-9240 National Semiconductor GmbH Livry-Gargan-Str. 10 D-82256 F4urstenfeldbruck Germany Tel: (81-41) 35-0 Telex: 527649 Fax: (81-41) 35-1 National Semiconductor Japan Ltd. Sumitomo Chemical Engineering Center Bldg. 7F 1-7-1, Nakase, Mihama-Ku Chiba-City, Ciba Prefecture 261 Tel: (043) 299-2300 Fax: (043) 299-2500 2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. National Semiconductor Hong Kong Ltd. 13th Floor, Straight Block, Ocean Centre, 5 Canton Rd. Tsimshatsui, Kowloon Hong Kong Tel: (852) 2737-1600 Fax: (852) 2736-9960 National Semiconductores Do Brazil Ltda. Rue Deputado Lacorda Franco 120-3A Sao Paulo-SP Brazil 05418-000 Tel: (55-11) 212-5066 Telex: 391-1131931 NSBR BR Fax: (55-11) 212-1181 National Semiconductor (Australia) Pty, Ltd. Building 16 Business Park Drive Monash Business Park Nottinghill, Melbourne Victoria 3168 Australia Tel: (3) 558-9999 Fax: (3) 558-9998 National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications.