74LVC2G17 Dual non-inverting Schmitt trigger with 5 V tolerant input Rev. 8 — 2 May 2013 Product data sheet 1. General description The 74LVC2G17 provides two non-inverting buffers with Schmitt trigger input. It is capable of transforming slowly changing input signals into sharply defined, jitter-free output signals. Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of these devices as translators in a mixed 3.3 V and 5 V environment. This device is fully specified for partial power-down applications using IOFF. The IOFF circuitry disables the output, preventing the damaging backflow current through the device when it is powered down. 2. Features and benefits Wide supply voltage range from 1.65 V to 5.5 V 5 V tolerant input/output for interfacing with 5 V logic High noise immunity Complies with JEDEC standard: JESD8-7 (1.65 V to 1.95 V) JESD8-5 (2.3 V to 2.7 V) JESD-8B/JESD36 (2.7 V to 3.6 V) ESD protection: HBM JESD22-A114F exceeds 2000 V MM JESD22-A115-A exceeds 200 V 24 mA output drive (VCC = 3.0 V) CMOS low-power consumption Latch-up performance exceeds 250 mA Direct interface with TTL levels Multiple package options Specified from 40 C to +85 C and 40 C to +125 C 3. Applications Wave and pulse shapers for highly noisy environments 74LVC2G17 NXP Semiconductors Dual non-inverting Schmitt trigger with 5 V tolerant input 4. Ordering information Table 1. Ordering information Type number Package Temperature range Name Description Version 74LVC2G17GW 40 C to +125 C SC-88 plastic surface-mounted package; 6 leads SOT363 74LVC2G17GV 40 C to +125 C TSOP6 plastic surface-mounted package (TSOP6); 6 leads SOT457 74LVC2G17GM 40 C to +125 C XSON6 plastic extremely thin small outline package; no leads; 6 terminals; body 1 1.45 0.5 mm SOT886 74LVC2G17GF 40 C to +125 C XSON6 plastic extremely thin small outline package; no leads; 6 terminals; body 1 1 0.5 mm SOT891 74LVC2G17GN 40 C to +125 C XSON6 extremely thin small outline package; no leads; 6 terminals; body 0.9 1.0 0.35 mm SOT1115 74LVC2G17GS 40 C to +125 C XSON6 extremely thin small outline package; no leads; 6 terminals; body 1.0 1.0 0.35 mm SOT1202 5. Marking Table 2. Marking codes Type number Marking code[1] 74LVC2G17GW VV 74LVC2G17GV VV 74LVC2G17GM VV 74LVC2G17GF VV 74LVC2G17GN VV 74LVC2G17GS VV [1] The pin 1 indicator is located on the lower left corner of the device, below the marking code. 6. Functional diagram 1 1A 1Y 6 3 2A 2Y 4 1 6 3 4 mnb066 Fig 1. Logic symbol 74LVC2G17 Product data sheet mnb067 Fig 2. IEC logic symbol All information provided in this document is subject to legal disclaimers. Rev. 8 — 2 May 2013 © NXP B.V. 2013. All rights reserved. 2 of 19 74LVC2G17 NXP Semiconductors Dual non-inverting Schmitt trigger with 5 V tolerant input 1A 1Y 2A 2Y mnb068 Fig 3. Logic diagram 7. Pinning information 7.1 Pinning 74LVC2G17 74LVC2G17 1A 1 6 1A 1 6 1Y GND 2 5 VCC 1Y GND 2 5 VCC 2A 3 4 2Y 2A Pin configuration SOT363 and SOT457 3 4 2Y Fig 5. Pin configuration SOT886 1A 1 6 1Y GND 2 5 VCC 2A 3 4 2Y 001aaf080 001aaf079 Transparent top view Transparent top view 001aaf078 Fig 4. 74LVC2G17 Fig 6. Pin configuration SOT891, SOT1115 and SOT1202 7.2 Pin description Table 3. Pin description Symbol Pin Description 1A 1 data input GND 2 ground (0 V) 2A 3 data input 2Y 4 data output VCC 5 supply voltage 1Y 6 data output 8. Functional description Table 4. Function table[1] Input Output nA nY L L H H [1] H = HIGH voltage level; L = LOW voltage level. 74LVC2G17 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 8 — 2 May 2013 © NXP B.V. 2013. All rights reserved. 3 of 19 74LVC2G17 NXP Semiconductors Dual non-inverting Schmitt trigger with 5 V tolerant input 9. Limiting values Table 5. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). Symbol Parameter VCC supply voltage IIK input clamping current VI input voltage IOK output clamping current Conditions VI < 0 V [1] Max Unit 0.5 +6.5 V - 50 mA 0.5 +6.5 V - 50 mA Active mode [1][2] 0.5 VCC + 0.5 V Power-down mode [1][2] 0.5 +6.5 V - 50 mA VO < 0 V output voltage VO Min IO output current ICC supply current - 100 mA IGND ground current - 100 mA Tstg storage temperature 65 +150 C Ptot total power dissipation - 300 mW [1] VO = 0 V to VCC Tamb = 40 C to +125 C [3] The input and output voltage ratings may be exceeded if the input and output current ratings are observed. [2] When VCC = 0 V (Power-down mode), the output voltage can be 5.5 V in normal operation. [3] For SC-88 and SC-74 packages: above 87.5 C the value of Ptot derates linearly with 4.0 mW/K. For XSON6 packages: above 118 C the value of Ptot derates linearly with 7.8 mW/K. 10. Recommended operating conditions Table 6. Recommended operating conditions Symbol Parameter VCC Conditions Min Typ Max Unit supply voltage 1.65 - 5.5 V VI input voltage 0 - 5.5 V VO output voltage 0 - VCC V Tamb ambient temperature 40 - +125 C 11. Static characteristics Table 7. Static characteristics At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter Tamb = 40 C to +85 VOL Conditions LOW-level output voltage 74LVC2G17 Product data sheet Min Typ Max Unit IO = 100 A; VCC = 1.65 V to 5.5 V - - 0.1 V IO = 4 mA; VCC = 1.65 V - - 0.45 V IO = 8 mA; VCC = 2.3 V - - 0.3 V IO = 12 mA; VCC = 2.7 V - - 0.4 V IO = 24 mA; VCC = 3.0 V - - 0.55 V IO = 32 mA; VCC = 4.5 V - - 0.55 V C[1] VI = VT+ or VT All information provided in this document is subject to legal disclaimers. Rev. 8 — 2 May 2013 © NXP B.V. 2013. All rights reserved. 4 of 19 74LVC2G17 NXP Semiconductors Dual non-inverting Schmitt trigger with 5 V tolerant input Table 7. Static characteristics …continued At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter Conditions VOH VI = VT+ or VT HIGH-level output voltage Min Typ Max Unit IO = 100 A; VCC = 1.65 V to 5.5 V VCC 0.1 - - V IO = 4 mA; VCC = 1.65 V 1.2 - - V IO = 8 mA; VCC = 2.3 V 1.9 - - V IO = 12 mA; VCC = 2.7 V 2.2 - - V IO = 24 mA; VCC = 3.0 V 2.3 - - V IO = 32 mA; VCC = 4.5 V 3.8 - - V II input leakage current VI = 5.5 V or GND; VCC = 5.5 V - 0.1 5 A IOFF power-off leakage current VI or VO = 5.5 V; VCC = 0 V - 0.1 10 A ICC supply current VI = VCC or GND; IO = 0 A; VCC = 5.5 V - 0.1 10 A ICC additional supply current VI = VCC 0.6 V; IO = 0 A; VCC = 2.3 V to 5.5 V - 5 500 A CI input capacitance - 3.5 - pF IO = 100 A; VCC = 1.65 V to 5.5 V - - 0.1 V IO = 4 mA; VCC = 1.65 V - - 0.70 V Tamb = 40 C to +125 C LOW-level output voltage VOL VOH HIGH-level output voltage VI = VT+ or VT IO = 8 mA; VCC = 2.3 V - - 0.45 V IO = 12 mA; VCC = 2.7 V - - 0.60 V IO = 24 mA; VCC = 3.0 V - - 0.80 V IO = 32 mA; VCC = 4.5 V - - 0.80 V VI = VT+ or VT IO = 100 A; VCC = 1.65 V to 5.5 V VCC 0.1 - - V IO = 4 mA; VCC = 1.65 V 0.95 - - V IO = 8 mA; VCC = 2.3 V 1.7 - - V IO = 12 mA; VCC = 2.7 V 1.9 - - V IO = 24 mA; VCC = 3.0 V 2.0 - - V IO = 32 mA; VCC = 4.5 V 3.4 - - V - 0.1 20 A II input leakage current VI = 5.5 V or GND; VCC = 5.5 V IOFF power-off leakage current VI or VO = 5.5 V; VCC = 0 V - - 20 A ICC supply current VI = VCC or GND; IO = 0 A; VCC = 5.5 V - - 40 A ICC additional supply current VI = VCC 0.6 V; IO = 0 A; VCC = 2.3 V to 5.5 V - - 5 mA [1] All typical values are measured at VCC = 3.3 V and Tamb = 25 C. 74LVC2G17 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 8 — 2 May 2013 © NXP B.V. 2013. All rights reserved. 5 of 19 74LVC2G17 NXP Semiconductors Dual non-inverting Schmitt trigger with 5 V tolerant input 12. Dynamic characteristics Table 8. Dynamic characteristics Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 8. Symbol Parameter 40 C to +85 C Conditions power dissipation capacitance CPD Unit Min Max Min Max VCC = 1.65 V to 1.95 V 1.5 5.6 10.5 1.5 13.1 ns VCC = 2.3 V to 2.7 V 1.0 3.7 6.5 1.0 8.5 ns VCC = 2.7 V 1.0 3.8 6.5 1.0 8.5 ns VCC = 3.0 V to 3.6 V 1.0 3.6 5.7 1.0 7.1 ns VCC = 4.5 V to 5.5 V 1.0 2.7 4.3 1.0 5.4 ns - 16.3 - - - pF propagation delay nA to nY; see Figure 7 tpd 40 C to +125 C Typ[1] per buffer; VCC = 3.3 V; VI = GND to VCC [2] [3] [1] Typical values are measured at Tamb = 25 C and VCC = 1.8 V, 2.5 V, 2.7 V, 3.3 V and 5.0 V respectively. [2] tpd is the same as tPLH and tPHL. [3] CPD is used to determine the dynamic power dissipation (PD in W). PD = CPD VCC2 fi N + (CL VCC2 fo) where: fi = input frequency in MHz; fo = output frequency in MHz; CL = output load capacitance in pF; VCC = supply voltage in V; N = number of inputs switching; (CL VCC2 fo) = sum of outputs. 13. Waveforms VI nA input VM VM GND tPLH tPHL VOH VM nY output VM VOL mnb072 Measurement points are given in Table 9. VOL and VOH are typical output voltage drop that occur with the output load. Fig 7. The input (nA) to output (nY) propagation delays and the output transition times 74LVC2G17 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 8 — 2 May 2013 © NXP B.V. 2013. All rights reserved. 6 of 19 74LVC2G17 NXP Semiconductors Dual non-inverting Schmitt trigger with 5 V tolerant input Table 9. Measurement points Supply voltage Input Output VCC VM VM 1.65 V to 1.95 V 0.5 VCC 0.5 VCC 2.3 V to 2.7 V 0.5 VCC 0.5 VCC 2.7 V 1.5 V 1.5 V 3.0 V to 3.6 V 1.5 V 1.5 V 4.5 V to 5.5 V 0.5 VCC 0.5 VCC VEXT VCC VI RL VO G DUT RT CL RL mna616 Measurement points are given in Table 10. Definitions for test circuit: RL = Load resistance. CL = Load capacitance including jig and probe capacitance. RT = Termination resistance should be equal to output impedance Zo of the pulse generator. VEXT = External voltage for measuring switching times. Fig 8. Table 10. Test circuit for measuring switching times Test data Supply voltage Input Load VEXT VCC VI tr, tf CL RL tPLH, tPHL 1.65 V to 1.95 V VCC 2.0 ns 30 pF 1 k open 2.3 V to 2.7 V VCC 2.0 ns 30 pF 500 open 2.7 V 2.7 V 2.5 ns 50 pF 500 open 3.0 V to 3.6 V 2.7 V 2.5 ns 50 pF 500 open 4.5 V to 5.5 V VCC 2.5 ns 50 pF 500 open 74LVC2G17 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 8 — 2 May 2013 © NXP B.V. 2013. All rights reserved. 7 of 19 74LVC2G17 NXP Semiconductors Dual non-inverting Schmitt trigger with 5 V tolerant input 14. Transfer characteristics Table 11. Transfer characteristics At recommended operating conditions. Voltages are referenced to GND (ground = 0 V). Symbol Parameter positive-going threshold voltage VT+ negative-going threshold voltage VT 40 C to +125 C Unit Min Typ[1] Max Min Max VCC = 1.8 V 0.70 1.10 1.50 0.70 1.70 V VCC = 2.3 V 1.00 1.40 1.80 1.00 2.00 V VCC = 3.0 V 1.30 1.76 2.20 1.30 2.40 V VCC = 4.5 V 1.90 2.47 3.10 1.90 3.30 V VCC = 5.5 V 2.20 2.91 3.60 2.20 3.80 V VCC = 1.8 V 0.25 0.61 0.90 0.25 1.10 V VCC = 2.3 V 0.40 0.80 1.15 0.40 1.35 V VCC = 3.0 V 0.60 1.04 1.50 0.60 1.70 V VCC = 4.5 V 1.00 1.55 2.00 1.00 2.20 V VCC = 5.5 V 1.20 1.86 2.30 1.20 2.50 V VCC = 1.8 V 0.15 0.49 1.00 0.15 1.20 V VCC = 2.3 V 0.25 0.60 1.10 0.25 1.30 V VCC = 3.0 V 0.40 0.73 1.20 0.40 1.40 V VCC = 4.5 V 0.60 0.92 1.50 0.60 1.70 V VCC = 5.5 V 0.70 1.02 1.70 0.70 1.90 V see Figure 9 and Figure 10 see Figure 9 and Figure 10 hysteresis voltage (VT+ VT); see Figure 9, Figure 10 and Figure 11 VH [1] 40 C to +85 C Conditions All typical values are measured at Tamb = 25 C. 15. Waveforms transfer characteristics VO VI VT+ VH VT− VO VI VH VT− Fig 9. VT+ Transfer characteristic 74LVC2G17 Product data sheet mnb155 mnb154 VT+ and VT limits at 70 % and 20 %. Fig 10. Definition of VT+, VT and VH All information provided in this document is subject to legal disclaimers. Rev. 8 — 2 May 2013 © NXP B.V. 2013. All rights reserved. 8 of 19 74LVC2G17 NXP Semiconductors Dual non-inverting Schmitt trigger with 5 V tolerant input mnb071 14 ICC (mA) 12 10 8 6 4 2 0 0 0.5 1 1.5 2 VI (V) VCC = 3.0 V. Fig 11. Typical transfer characteristic mnb156 50 ICC (mA) (1) 40 30 20 (2) 10 0 2 3 4 5 VCC (V) 6 (1) Positive-going edge (2) Negative-going edge Linear change of VI between 0.8 V to 2.0 V. All values given are typical unless otherwise specified. Fig 12. Average ICC as a function of VCC 74LVC2G17 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 8 — 2 May 2013 © NXP B.V. 2013. All rights reserved. 9 of 19 74LVC2G17 NXP Semiconductors Dual non-inverting Schmitt trigger with 5 V tolerant input 16. Package outline Plastic surface-mounted package; 6 leads SOT363 D E B y X A HE 6 5 v M A 4 Q pin 1 index A A1 1 2 e1 3 bp c Lp w M B e detail X 0 1 2 mm scale DIMENSIONS (mm are the original dimensions) UNIT A A1 max bp c D E e e1 HE Lp Q v w y mm 1.1 0.8 0.1 0.30 0.20 0.25 0.10 2.2 1.8 1.35 1.15 1.3 0.65 2.2 2.0 0.45 0.15 0.25 0.15 0.2 0.2 0.1 OUTLINE VERSION REFERENCES IEC JEDEC SOT363 JEITA SC-88 EUROPEAN PROJECTION ISSUE DATE 04-11-08 06-03-16 Fig 13. Package outline SOT363 (SC-88) 74LVC2G17 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 8 — 2 May 2013 © NXP B.V. 2013. All rights reserved. 10 of 19 74LVC2G17 NXP Semiconductors Dual non-inverting Schmitt trigger with 5 V tolerant input Plastic surface-mounted package (TSOP6); 6 leads D SOT457 E B y A HE 6 5 X v M A 4 Q pin 1 index A A1 c 1 2 3 Lp bp e w M B detail X 0 1 2 mm scale DIMENSIONS (mm are the original dimensions) UNIT A A1 bp c D E e HE Lp Q v w y mm 1.1 0.9 0.1 0.013 0.40 0.25 0.26 0.10 3.1 2.7 1.7 1.3 0.95 3.0 2.5 0.6 0.2 0.33 0.23 0.2 0.2 0.1 OUTLINE VERSION REFERENCES IEC JEDEC SOT457 JEITA SC-74 EUROPEAN PROJECTION ISSUE DATE 05-11-07 06-03-16 Fig 14. Package outline SOT457 (SC-74) 74LVC2G17 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 8 — 2 May 2013 © NXP B.V. 2013. All rights reserved. 11 of 19 74LVC2G17 NXP Semiconductors Dual non-inverting Schmitt trigger with 5 V tolerant input SOT886 XSON6: plastic extremely thin small outline package; no leads; 6 terminals; body 1 x 1.45 x 0.5 mm b 1 2 3 4x (2) L L1 e 6 5 e1 4 e1 6x A (2) A1 D E terminal 1 index area 0 1 2 mm scale Dimensions (mm are the original dimensions) Unit mm max nom min A(1) 0.5 A1 b D E 0.04 0.25 1.50 1.05 0.20 1.45 1.00 0.17 1.40 0.95 e e1 0.6 0.5 L L1 0.35 0.40 0.30 0.35 0.27 0.32 Notes 1. Including plating thickness. 2. Can be visible in some manufacturing processes. Outline version SOT886 sot886_po References IEC JEDEC JEITA European projection Issue date 04-07-22 12-01-05 MO-252 Fig 15. Package outline SOT886 (XSON6) 74LVC2G17 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 8 — 2 May 2013 © NXP B.V. 2013. All rights reserved. 12 of 19 74LVC2G17 NXP Semiconductors Dual non-inverting Schmitt trigger with 5 V tolerant input XSON6: plastic extremely thin small outline package; no leads; 6 terminals; body 1 x 1 x 0.5 mm 1 SOT891 b 3 2 4× (1) L L1 e 6 5 e1 4 e1 6× A (1) A1 D E terminal 1 index area 0 1 2 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max A1 max b D E e e1 L L1 mm 0.5 0.04 0.20 0.12 1.05 0.95 1.05 0.95 0.55 0.35 0.35 0.27 0.40 0.32 Note 1. Can be visible in some manufacturing processes. OUTLINE VERSION REFERENCES IEC JEDEC JEITA EUROPEAN PROJECTION ISSUE DATE 05-04-06 07-05-15 SOT891 Fig 16. Package outline SOT891 (XSON6) 74LVC2G17 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 8 — 2 May 2013 © NXP B.V. 2013. All rights reserved. 13 of 19 74LVC2G17 NXP Semiconductors Dual non-inverting Schmitt trigger with 5 V tolerant input XSON6: extremely thin small outline package; no leads; 6 terminals; body 0.9 x 1.0 x 0.35 mm 1 SOT1115 b 3 2 (4×)(2) L L1 e 6 5 4 e1 e1 (6×)(2) A1 A D E terminal 1 index area 0 0.5 scale Dimensions Unit mm 1 mm A(1) A1 b D E e e1 max 0.35 0.04 0.20 0.95 1.05 nom 0.15 0.90 1.00 0.55 min 0.12 0.85 0.95 0.3 L L1 0.35 0.40 0.30 0.35 0.27 0.32 Note 1. Including plating thickness. 2. Visible depending upon used manufacturing technology. Outline version sot1115_po References IEC JEDEC JEITA European projection Issue date 10-04-02 10-04-07 SOT1115 Fig 17. Package outline SOT1115 (XSON6) 74LVC2G17 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 8 — 2 May 2013 © NXP B.V. 2013. All rights reserved. 14 of 19 74LVC2G17 NXP Semiconductors Dual non-inverting Schmitt trigger with 5 V tolerant input XSON6: extremely thin small outline package; no leads; 6 terminals; body 1.0 x 1.0 x 0.35 mm 1 SOT1202 b 3 2 (4×)(2) L L1 e 6 5 4 e1 e1 (6×)(2) A1 A D E terminal 1 index area 0 0.5 scale Dimensions Unit mm 1 mm A(1) A1 b D E e e1 L L1 max 0.35 0.04 0.20 1.05 1.05 0.35 0.40 nom 0.15 1.00 1.00 0.55 0.35 0.30 0.35 min 0.12 0.95 0.95 0.27 0.32 Note 1. Including plating thickness. 2. Visible depending upon used manufacturing technology. Outline version sot1202_po References IEC JEDEC JEITA European projection Issue date 10-04-02 10-04-06 SOT1202 Fig 18. Package outline SOT1202 (XSON6) 74LVC2G17 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 8 — 2 May 2013 © NXP B.V. 2013. All rights reserved. 15 of 19 74LVC2G17 NXP Semiconductors Dual non-inverting Schmitt trigger with 5 V tolerant input 17. Abbreviations Table 12. Abbreviations Acronym Description CMOS Complementary Metal-Oxide Semiconductor DUT Device Under Test ESD ElectroStatic Discharge HBM Human Body Model MM Machine Model TTL Transistor-Transistor Logic 18. Revision history Table 13. Revision history Document ID Release date Data sheet status Change notice Supersedes 74LVC2G17 v.8 20130502 Product data sheet - 74LVC2G17 v.7 Modifications: • Table 3: the description of pin 6 changed from data input to data output. 74LVC2G17 v.6 20110921 Product data sheet - 74LVC2G17 v.5 74LVC2G17 v.5 20100806 Product data sheet - 74LVC2G17 v.4 74LVC2G17 v.4 20061009 Product data sheet - 74LVC2G17 v.3 74LVC2G17 v.3 20050926 Product data sheet - 74LVC2G17 v.2 74LVC2G17 v.2 20040908 Product specification - 74LVC2G17 v.1 74LVC2G17 v.1 20030813 Product specification - - 74LVC2G17 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 8 — 2 May 2013 © NXP B.V. 2013. All rights reserved. 16 of 19 74LVC2G17 NXP Semiconductors Dual non-inverting Schmitt trigger with 5 V tolerant input 19. Legal information 19.1 Data sheet status Document status[1][2] Product status[3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification. [1] Please consult the most recently issued document before initiating or completing a design. [2] The term ‘short data sheet’ is explained in section “Definitions”. [3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com. 19.2 Definitions Draft — The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet — A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. 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This document supersedes and replaces all information supplied prior to the publication hereof. 74LVC2G17 Product data sheet Suitability for use — NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in life support, life-critical or safety-critical systems or equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors and its suppliers accept no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk. Applications — Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. 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Customer is responsible for doing all necessary testing for the customer’s applications and products using NXP Semiconductors products in order to avoid a default of the applications and the products or of the application or use by customer’s third party customer(s). NXP does not accept any liability in this respect. Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) will cause permanent damage to the device. Limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the Recommended operating conditions section (if present) or the Characteristics sections of this document is not warranted. Constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device. Terms and conditions of commercial sale — NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, unless otherwise agreed in a valid written individual agreement. In case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. NXP Semiconductors hereby expressly objects to applying the customer’s general terms and conditions with regard to the purchase of NXP Semiconductors products by customer. No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. All information provided in this document is subject to legal disclaimers. Rev. 8 — 2 May 2013 © NXP B.V. 2013. All rights reserved. 17 of 19 74LVC2G17 NXP Semiconductors Dual non-inverting Schmitt trigger with 5 V tolerant input Export control — This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from competent authorities. Non-automotive qualified products — Unless this data sheet expressly states that this specific NXP Semiconductors product is automotive qualified, the product is not suitable for automotive use. It is neither qualified nor tested in accordance with automotive testing or application requirements. NXP Semiconductors accepts no liability for inclusion and/or use of non-automotive qualified products in automotive equipment or applications. In the event that customer uses the product for design-in and use in automotive applications to automotive specifications and standards, customer (a) shall use the product without NXP Semiconductors’ warranty of the product for such automotive applications, use and specifications, and (b) whenever customer uses the product for automotive applications beyond NXP Semiconductors’ specifications such use shall be solely at customer’s own risk, and (c) customer fully indemnifies NXP Semiconductors for any liability, damages or failed product claims resulting from customer design and use of the product for automotive applications beyond NXP Semiconductors’ standard warranty and NXP Semiconductors’ product specifications. Translations — A non-English (translated) version of a document is for reference only. The English version shall prevail in case of any discrepancy between the translated and English versions. 19.4 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. 20. Contact information For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: [email protected] 74LVC2G17 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 8 — 2 May 2013 © NXP B.V. 2013. All rights reserved. 18 of 19 74LVC2G17 NXP Semiconductors Dual non-inverting Schmitt trigger with 5 V tolerant input 21. Contents 1 2 3 4 5 6 7 7.1 7.2 8 9 10 11 12 13 14 15 16 17 18 19 19.1 19.2 19.3 19.4 20 21 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features and benefits . . . . . . . . . . . . . . . . . . . . 1 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2 Pinning information . . . . . . . . . . . . . . . . . . . . . . 3 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3 Functional description . . . . . . . . . . . . . . . . . . . 3 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 4 Recommended operating conditions. . . . . . . . 4 Static characteristics. . . . . . . . . . . . . . . . . . . . . 4 Dynamic characteristics . . . . . . . . . . . . . . . . . . 6 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Transfer characteristics . . . . . . . . . . . . . . . . . . 8 Waveforms transfer characteristics. . . . . . . . . 8 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 10 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Revision history . . . . . . . . . . . . . . . . . . . . . . . . 16 Legal information. . . . . . . . . . . . . . . . . . . . . . . 17 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 17 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Contact information. . . . . . . . . . . . . . . . . . . . . 18 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. © NXP B.V. 2013. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: [email protected] Date of release: 2 May 2013 Document identifier: 74LVC2G17