IRFF210 Data Sheet March 1999 2.2A, 200V, 1.500 Ohm, N-Channel Power MOSFET • 2.2A, 200V Formerly developmental type TA17442. Ordering Information PACKAGE 1887.3 Features This N-Channel enhancement mode silicon gate power field effect transistor is an advanced power MOSFET designed, tested, and guaranteed to withstand a specified level of energy in the breakdown avalanche mode of operation. All of these power MOSFETs are designed for applications such as switching regulators, switching convertors, motor drivers, relay drivers, and drivers for high power bipolar switching transistors requiring high speed and low gate drive power. These types can be operated directly from integrated circuits. PART NUMBER File Number • rDS(ON) = 1.500Ω • Single Pulse Avalanche Energy Rated • SOA is Power Dissipation Limited • Nanosecond Switching Speeds • Linear Transfer Characteristics • High Input Impedance • Related Literature - TB334 “Guidelines for Soldering Surface Mount Components to PC Boards” Symbol BRAND D IRFF210 TO-205AF IRFF210 NOTE: When ordering, include the entire part number. G S Packaging JEDEC TO-205AF SOURCE DRAIN (CASE) GATE 1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper ESD Handling Procedures. http://www.intersil.com or 407-727-9207 | Copyright © Intersil Corporation 1999 IRFF210 Absolute Maximum Ratings TC = 25oC, Unless Otherwise Specified Drain to Source Voltage (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .VDS Drain to Gate Voltage (RGS = 20kΩ) (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VDGR Continuous Drain Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ID Pulsed Drain Current (Note 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IDM Gate to Source Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .VGS Maximum Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .PD Linear Derating Factor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Single Pulse Avalanche Energy Rating (Note 4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .EAS Operating and Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TJ , TSTG Maximum Temperature for Soldering Leads at 0.063in (1.6mm) from Case for 10s. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TL Package Body for 10s, See Techbrief 334 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Tpkg IRFF210 200 200 2.2 9.0 ± 20 15 0.12 30 -55 to 150 UNITS V V A A V W W/oC mJ oC 300 260 oC oC CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTE: 1. TJ = 25oC to 125oC. TC = 25oC, Unless Otherwise Specified Electrical Specifications MIN TYP MAX UNITS Drain to Source Breakdown Voltage PARAMETER SYMBOL BVDSS VGS = 0V, ID = 250µA (Figure 10) 200 - - V Gate to Threshold Voltage VGS(TH) VGS = VDS , ID = 250µA 2.0 - 4.0 V - - 25 µA - - 250 µA 2.2 - - A Zero-Gate Voltage Drain Current IDSS TEST CONDITIONS VDS = Rated BVDSS , VGS = 0V VDS = 0.8 x Rated BVDSS, VGS = 0V, TJ = 125oC On-State Drain Current (Note 2) ID(ON) Gate to Source Leakage Forward Drain to Source On Resistance (Note 2) Forward Transconductance (Note 2) Turn-On Delay Time Rise Time IGSS rDS(ON) ±100 nA 1.0 1.500 Ω 0.8 1.3 - S ID ≈ 2.2A, RG = 9.1Ω, VGS = 10V, RL = 33Ω for VDS = 75V, RL = 44Ω for VDS = 100V, VDD ≈ 0.5BVDSS (Figures 15, 16) MOSFET Switching Times are Essentially Independent of Operating Temperature - 8 15 ns - 15 25 ns - 10 15 ns - 8 15 ns VGS = 10V, ID = 2.2A, VDS = 0.8 x Rated BVDSS , IG(REF) = 1.5mA (Figures 14, 19, 20) Gate Charge is Essentially Independent of Operating Temperature - 5.0 7.5 nC - 2.0 - nC - 3.0 - nC VGS = 0V, VDS = 25V, f = 1.0MHz (Figure 11) - 135 - pF Qg(TOT) Gate to Source Charge - - VGS > ID(ON) rDS(ON)MAX , ID = 1.25A (Figure 12) tf Total Gate Charge (Gate to Source + Gate to Drain) - VGS = 10V, ID = 1.25A (Figures 8, 9) gfs td(OFF) Fall Time VGS = ±20V td(ON) tr Turn-Off Delay Time VDS > ID(ON) x rDS(ON)MAX , VGS = 10V (Figure 7) Qgs Gate to Drain “Miller” Charge Qgd Input Capacitance CISS Output Capacitance COSS - 60 - pF Reverse to Transfer Capacitance CRSS - 16 - pF - 5.0 - nH - 15 - nH - - 8.33 oC/W - - 175 oC/W Internal Drain Inductance LD Internal Source Inductance LS Measured from the Drain Modified MOSFET Lead, 5mm (0.2in) from Symbol Showing the Header to Center of Die Internal Device Inductances Measured from the D Source Lead, 5mm (0.2in) from Header to Source Bonding Pad LD G LS S Junction to Case RθJC Junction to Ambient RθJA 2 Free Air Operation IRFF210 Source to Drain Diode Specifications PARAMETER SYMBOL Continuous Source to Drain Current ISD Pulse Source to Drain Current (Note 3) ISDM TEST CONDITIONS MIN TYP MAX UNITS - - 2.2 A - - 9.0 A TJ = 25oC, ISD = 2.2A, VGS = 0V (Figure 13) - - 2.0 V TJ = 150oC, ISD = 2.2A, dISD/dt = 100A/µs TJ = 150oC, ISD = 2.2A, dISD/dt = 100A/µs - 290 - ns - 2.0 - µC Modified MOSFET Symbol Showing the Integral Reverse P-N Junction Rectifier D G S Source to Drain Diode Voltage (Note 2) VSD Reverse Recovery Time trr Reverse Recovered Charge QRR NOTES: 2. Pulse test: pulse width ≤ 300µs, duty cycle ≤ 2%. 3. Repetitive rating: pulse width limited by Max junction temperature. See Transient Thermal Impedance curve (Figure 3). 4. VDD = 20V, start TJ = 25oC, L = 11.16mH, RG = 50Ω, peak IAS , 2.2A (Figures 14, 15). Typical Performance Curves 2.5 ID , DRAIN CURRENT (A) 1.0 0.8 0.6 0.4 0.2 0 0 50 100 150 2.0 1.5 1.0 0.5 0 25 50 TC , CASE TEMPERATURE (oC) 75 100 125 150 TC , CASE TEMPERATURE (oC) FIGURE 1. NORMALIZED POWER DISSIPATION vs CASE TEMPERATURE FIGURE 2. MAXIMUM CONTINUOUS DRAIN CURRENT vs CASE TEMPERATURE 2 1.0 ZθJC, NORMALIZED THERMAL IMPEDANCE POWER DISSIPATION MULTIPLIER 1.2 0.5 0.2 0.1 PDM 0.1 t1 0.05 0.02 0.01 NOTES: DUTY FACTOR: D = t1/t2 TJ = PDM x ZθJC(t) x RθJC + TC SINGLE PULSE 0.01 10-5 10-4 10-3 10-2 t1, RECTANGULAR PULSE DURATION (s) 0.1 FIGURE 3. NORMALIZED MAXIMUM TRANSIENT THERMAL IMPEDANCE 3 t2 1 10 IRFF210 Typical Performance Curves 5 50 OPERATION IN THIS AREA IS LIMITED BY rDS(ON) 10 10µs 100µs 1 1ms TC = 25oC TJ = MAX RATED RθJC = 8.33 K/W 0.1 10ms 4 VGS = 7V 3 2 VGS = 6V 1 DC 10 102 VDS , DRAIN TO SOURCE VOLTAGE (V) VGS = 5V VGS = 4V 0 103 0 ID , ON-STATE DRAIN CURRENT (A) ID , DRAIN CURRENT (A) VGS = 9V VGS = 8V 3 VGS = 7V 2 VGS = 6V 1 VGS = 5V VGS = 4V 0 1 2 3 40 50 4 VDS > ID(ON) x rDS(ON) MAX 80µs PULSE TEST TJ = 125oC TJ = 25oC 4 TJ = -55oC 3 2 1 0 5 0 2 VDS , DRAIN TO SOURCE VOLTAGE (V) 4 6 8 10 VGS , GATE TO SOURCE VOLTAGE (V) FIGURE 6. SATURATION CHARACTERISTICS FIGURE 7. TRANSFER CHARACTERISTICS 4 2.2 2µs DURATION INITIAL, TJ = 25oC HEATING EFFECT OF 2µs PULSE IS MINIMAL NORMALIZED DRAIN TO SOURCE ON RESISTANCE rDS(ON) , DRAIN TO SOURCE ON RESISTANCE (Ω) 30 5 VGS = 10V 4 20 FIGURE 5. OUTPUT CHARACTERISTICS 5 80µs PULSE TEST 10 VDS , DRAIN TO SOURCE VOLTAGE (V) FIGURE 4. FORWARD BIAS SAFE OPERATING AREA 0 80µs PULSE TEST VGS = 8V 100ms SINGLE PULSE 1 10V VGS = 9V ID , DRAIN CURRENT (A) ID , DRAIN CURRENT (A) (Continued) 3 VGS = 10V 2 1 VGS = 20V ID = 1.25A VGS = 10V 1.8 1.4 1.0 0.6 0.2 0 0 2 4 6 ID , DRAIN CURRENT (A) 8 FIGURE 8. DRAIN TO SOURCE ON RESISTANCE vs GATE VOLTAGE AND DRAIN CURRENT 4 10 -40 0 40 80 120 TJ, JUNCTION TEMPERATURE (oC) FIGURE 9. NORMALIZED DRAIN TO SOURCE ON RESISTANCE vs JUNCTION TEMPERATURE 160 IRFF210 Typical Performance Curves (Continued) 500 VGS = 0V, f = 1MHz CISS = CGS + CGD CRSS = CGD COSS ≈ CDS + CGD ID = 250µA 1.15 400 C, CAPACITANCE (pF) NORMALIZED DRAIN TO SOURCE BREAKDOWN VOLTAGE 1.25 1.05 0.95 300 200 CISS 0.85 100 COSS CRSS 0.75 -40 0 40 80 0 160 120 0 10 20 30 40 VDS , DRAIN TO SOURCE VOLTAGE (V) TJ, JUNCTION TEMPERATURE (oC) FIGURE 10. NORMALIZED DRAIN TO SOURCE BREAKDOWN VOLTAGE vs JUNCTION TEMPERATURE FIGURE 11. CAPACITANCE vs DRAIN TO SOURCE VOLTAGE 10 ISD , SOURCE TO DRAIN CURRENT (A) 4.0 80µs PULSE TEST 3.6 3.2 2.8 2.4 TJ = -55oC 2.0 TJ = 25oC 1.6 TJ = 125oC 1.2 0.8 0.4 TJ = 150oC TJ = 25oC 1 0.1 0 0 1 2 3 ID , DRAIN CURRENT (A) 4 0 5 FIGURE 12. TRANSCONDUCTANCE vs DRAIN CURRENT 1 2 3 4 VSD , SOURCE TO DRAIN VOLTAGE (V) FIGURE 13. SOURCE TO DRAIN DIODE VOLTAGE 20 VGS , GATE TO SOURCE VOLTAGE (V) gfs , TRANSCONDUCTANCE (S) 50 ID = 2.2A VDS = 40V VDS = 100V 15 VDS = 160V 10 5 0 0 2 4 6 8 10 Qg(TOT) , TOTAL GATE CHARGE (nC) FIGURE 14. GATE TO SOURCE VOLTAGE vs GATE CHARGE 5 5 IRFF210 Test Circuits and Waveforms VDS BVDSS tP L VDS IAS VARY tP TO OBTAIN VDD + RG REQUIRED PEAK IAS - VDD DUT VGS 0V tP 0 IAS 0.01Ω tAV FIGURE 16. UNCLAMPED ENERGY WAVEFORMS FIGURE 15. UNCLAMPED ENERGY TEST CIRCUIT tON tOFF td(ON) td(OFF) tf tr VDS RL 90% + RG - 10% 10% 0 VDD 90% 90% DUT VGS 0 50% 50% PULSE WIDTH 10% VGS FIGURE 17. SWITCHING TIME TEST CIRCUIT FIGURE 18. RESISTIVE SWITCHING WAVEFORMS VDS (ISOLATED SUPPLY) CURRENT REGULATOR VDD Qg(TOT) 12V BATTERY 0.2µF SAME TYPE AS DUT 50kΩ Qgd Qgs 0.3µF D Ig(REF) VDS DUT G 0 S 0 IG CURRENT SAMPLING RESISTOR VDS ID CURRENT SAMPLING RESISTOR FIGURE 19. GATE CHARGE TEST CIRCUIT 6 VGS Ig(REF) 0 FIGURE 20. GATE CHARGE WAVEFORMS IRFF210 All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification. Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. 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