IRFF9120 Data Sheet June 1999 4A, 100V, 0.60 Ohm, P-Channel Power MOSFET • 4A, 100V • rDS(ON) = 0.60Ω • Single Pulse Avalanche Energy Rated • SOA is Power-Dissipation Limited • Nanosecond Switching Speeds • Linear Transfer Characteristics Formerly developmental type TA17501. • High Input Impedance Ordering Information Symbol IRFF9120 NOTE: PACKAGE TO-205AF 2287.2 Features This P-Channel enhancement mode silicon gate power field effect transistor is designed for applications such as switching regulators, switching converters, motor drivers, relay drivers, and drivers for high power bipolar switching transistors requiring high speed and low gate drive power. These types can be operated directly from integrated circuits. PART NUMBER File Number BRAND D IRFF9120 When ordering, use the entire part number. G S Packaging JEDEC TO-205AF SOURCE DRAIN (CASE) GATE 4-94 CAUTION: These devices are sensitive to electrostatic discharge; follow proper ESD Handling Procedures. http://www.intersil.com or 407-727-9207 | Copyright © Intersil Corporation 1999 IRFF9120 Absolute Maximum Ratings TC = 25oC, Unless Otherwise Specified Drain to Source Voltage (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VDS Drain to Gate Voltage (RGS = 20kΩ) (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VDGR Continuous Drain Current, TC = 25oC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ID Pulsed Drain Current (Note 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IDM Gate to Source Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VGS Maximum Power Dissipation, (Figure 14) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PD Linear Derating Factor (Figure 14). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Single Pulse Avalanche Energy Rating (Note 4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . EAS Operating and Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TJ , TSTG Maximum Temperature for Soldering Leads at 0.063in (1.6mm) from Case for 10s. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TL Package Body for 10s, See Techbrief 334 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Tpkg IRFF9120 -100 -100 -4 -16 ±20 20 0.16 370 -55 to 150 UNITS V V A A V W W/oC mJ oC 300 260 oC oC CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTE: 1. TJ = 25oC to 125oC. Electrical Specifications TC = 25oC, Unless Otherwise Specified PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS Drain to Source Breakdown Voltage BVDSS VGS = 0V, ID = 250µA -100 - - V Gate Threshold Voltage VGS(TH) VDS = VGS, ID = 250µA -2.0 - -4.0 V - - -250 µA Zero Gate Voltage Drain Current On-State Drain Current (Note 2) Gate to Source Leakage Forward Gate to Source Leakage Reverse Drain to Source On-State Resistance (Note 2) Forward Transconductance (Note 2) Turn-On Delay Time IDSS VDS = Max Rating x 0.8, VGS = 0V, TJ = 125oC - - -1000 µA VDS > ID(ON) x rDS(ON)MAX, VGS = -10V -4 - - A IGSS VGS = -20V - - -100 nA IGSS VGS = 20V - - 100 nA VGS = 10V, ID = -2A - 0.5 0.6 Ω 1.25 2 - S - 25 50 ns - 50 100 ns - 50 100 ns - 50 100 ns - 16 22 nC - 9 - nC - 7 - nC - 300 - pF - 200 - pF - 50 - pF - 5.0 - nH - 15 - nH - - 6.25 oC/W - - 175 oC/W ID(ON) rDS(ON) gfs tD(ON) Rise Time tr Turn-Off Delay Time tD(OFF) Fall Time VDS = Max Rating, VGS = 0V VDS > ID(ON) x rDS(ON) Max, ID = 2A VDD ≅ 0.5BVDSS, ID = 4A, RG = 9.1Ω (Figure 18) MOSFET Switching Times are Essentially Independent of Operating Temperature tf Total Gate Charge (Gate to Source + Gate to Drain) QG(TOT) Gate to Source Charge QGS Gate to Drain “Miller” Charge QGD Input Capacitance CISS Output Capacitance COSS Reverse Transfer Capacitance CRSS VGS = 10V, ID = 4A, VDS = 0.8 Max BVDSS (See Figure 18 for Test Circuit) Gate Charge is Essentially Independent of Operating Temperature VGS = 0V, VDS = 25V, f = 1.0MHz, See Figure 10 Internal Drain Inductance LD Measured from the Drain Lead, 5.0mm (0.2in) From Header to Center of Die Internal Source Inductance LS Measured from the Source Lead, 5.0mm (0.2in) from Header to Source Bonding Pad Modified MOSFET Symbol Showing the Internal Device Inductances D G S Junction to Case RθJC Junction to Ambient RθJA 4-95 Typical Socket Mount IRFF9120 Source to Drain Diode Specifications PARAMETER SYMBOL Continuous Source Current ISD Pulse Source Current (Note 3) ISM TEST CONDITIONS Modified MOSFET Symbol Showing the Integral Reverse P-N Junction Rectifier D MIN TYP MAX UNITS - - -4 A - - -16 A - - -1.5 V - 230 - ns - 1.3 - µC G S Source to Drain Diode Voltage (Note 2) VSD Diode Reverse Recovery Time trr Reverse Recovery Charge QRR TJ = 25oC, ISD = -4A, VGS = 0V TJ = 150oC, ISD = 4A, dISD/dt = 100A/µs TJ = 150oC, ISD = -4A, dISD/dt = 100A/µs NOTES: 2. Pulse test: Pulse width ≤ 300µs, Duty Cycle 2%. 3. Repetitive rating: Pulse width limited by maximum junction temperature. See Transient Thermal Impedance Curve (Figure 3). 4. VDD = 25V, starting TJ = 250oC, L = 34.7mH, RG = 25Ω, peak IAS = 4.0A. See Figures 15 and 16) Typical Performance Curves -5 1.0 ID, DRAIN CURRENT (A) POWER DISSIPATION MULTIPLIER 1.2 0.8 0.6 0.4 -4 -3 -2 -1 0.2 0 0 0 50 100 25 150 50 100 75 150 125 TC, CASE TEMPERATURE (oC) TC, CASE TEMPERATURE (oC) FIGURE 1. NORMALIZED POWER DISSIPATION vs CASE TEMPERATURE FIGURE 2. MAXIMUM CONTINUOUS DRAIN CURRENT vs CASE TEMPERATURE ZθJC, NORMALIZED THERMAL IMPEDANCE 1.0 0.5 0.2 0.1 PDM 0.1 t1 0.05 t2 NOTES: DUTY FACTOR: D = t1/t2 PEAK TJ = PDM x ZθJC x RθJC + TC 0.02 0.01 SINGLE PULSE 0.01 10-5 10-4 10-3 10-2 10-1 t1, RECTANGULAR PULSE DURATION (s) FIGURE 3. NORMALIZED MAXIMUM TRANSIENT THERMAL IMPEDANCE 4-96 1 10 IRFF9120 Typical Performance Curves (Continued) 10 OPERATION IN THIS REGION IS LIMITED BY rDS(ON) -10V 10 1ms 1 10ms 100ms TC = 25oC TJ = MAX RATED SINGLE PULSE -8 ID, DRAIN CURRENT (A) ID DRAIN CURRENT (A) 10µs -8V -6 VGS = -7V -4 -6V -2 -5V DC -4V 0.1 1 10 VDS DRAIN VOLTAGE (V) 0 100 -10 -8V -9V -20 -30 -40 -50 FIGURE 5. OUTPUT CHARACTERISTICS 4 ID, DRAIN CURRENT (A) ID DRAIN CURRENT (A) PULSE DURATION = 80µs DUTY CYCLE = 0.5% MAX -10V -10 VDS , DRAIN TO SOURCE VOLTAGE (V) FIGURE 4. FORWARD BIAS SAFE OPERATING AREA 5 -9V PULSE DURATION = 80µs DUTY CYCLE = 0.5% MAX -7V 3 V = -6V 2 -5V 1 -8 PULSE DURATION = 80µs DUTY CYCLE = 0.5% MAX VDS ≥ ID(ON) x rDS(ON) MAXIMUM TJ = 125oC TJ = 25oC TJ = 55oC -6 -4 -2 -4V 0 0 -1 -2 -3 -4 -5 0 -2 VDS, DRAIN TO SOURCE VOLTAGE (V) FIGURE 6. SATURATION CHARACTERISTICS NORMALIZED DRAIN TO SOURCE ON RESISTANCE VOLTAGE 1.6 ON RESISTANCE rDS(ON), DRAIN TO SOURCE PULSE DURATION = 2µs VGS = -10V 1.2 0.8 0 VGS = -20V 0 -5 -10 -15 -20 -25 ID, DRAIN CURRENT (A) FIGURE 8. DRAIN TO SOURCE ON RESISTANCE vs GATE VOLTAGE AND DRAIN CURRENT 4-97 -8 -6 -10 FIGURE 7. TRANSFER CHARACTERISTICS 2.0 0.4 -4 VGS, GATE TO SOURCE VOLTAGE (V) 2.2 VGS = -10V ID = -2A 1.8 1.4 1.0 0.6 0.2 -40 0 40 80 120 TJ, JUNCTION TEMPERATURE (oC) FIGURE 9. NORMALIZED DRAIN TO SOURCE ON RESISTANCE vs JUNCTION TEMPERATURE 160 IRFF9120 (Continued) 1.25 500 1.15 400 C, CAPACITANCE (pF) NORMALIZED DRAIN TO SOURCE BREAKDOWN VOLTAGE Typical Performance Curves 1.05 0.95 VGS = 0V, f = 1MHz CISS = CGS + CGD CRSS = CGD COSS ≈ CDS + CGD CISS 300 COSS 200 100 0.85 0 0.75 -40 0 40 120 80 160 CRSS 0 -10 TJ , JUNCTION TEMPERATURE (oC) FIGURE 10. NORMALIZED DRAIN TO SOURCE BREAKDOWN VOLTAGE vs JUNCTION TEMPERATURE -50 TJ = 125oC 1 -8 TJ = 150oC -10 TJ = 25oC -1 -0.1 -0.4 0 -4 -6 ID , DRAIN CURRENT (A) PULSE DURATION = 80µs DUTY CYCLE = 0.5% MAX ISD, SOURCE TO DRAIN CURRENT (A) gfs , TRANSCONDUCTANCE (S) 2 -2 -40 FIGURE 11. CAPACITANCE vs DRAIN TO SOURCE VOLTAGE TJ = -55oC TJ = 25oC 0 -30 -100 PULSE DURATION = 80µs DUTY CYCLE = 0.5% MAX 3 -20 VDS, DRAIN TO SOURCE VOLTAGE (V) -10 FIGURE 12. TRANSCONDUCTANCE vs DRAIN CURRENT -0.6 -0.8 -1.0 -1.2 -1.4 -1.6 VSD , SOURCE TO DRAIN VOLTAGE (V) FIGURE 13. SOURCE TO DRAIN DIODE VOLTAGE VGS , GATE TO SOURCE VOLTAGE (V) 0 ID = -8A -5 -10 VDS = -80V VDS = -50V VDS = -20V -15 -20 0 4 8 12 16 20 Qg(TOT), TOTAL GATE CHARGE (nC) FIGURE 14. GATE TO SOURCE VOLTAGE vs GATE CHARGE 4-98 -1.8 IRFF9120 Test Circuits and Waveforms VDS tAV L 0 VARY tP TO OBTAIN - RG REQUIRED PEAK IAS + VDD DUT 0V VDD tP VGS IAS IAS VDS tP 0.01Ω BVDSS FIGURE 15. UNCLAMPED ENERGY TEST CIRCUIT FIGURE 16. UNCLAMPED ENERGY WAVEFORMS tON tOFF td(OFF) td(ON) tr 0 RL - DUT VGS + 10% 10% VDS VDD RG tf 90% 90% VGS 0 10% 50% 50% PULSE WIDTH 90% FIGURE 17. SWITCHING TIME TEST CIRCUIT FIGURE 18. RESISTIVE SWITCHING WAVEFORMS -VDS (ISOLATED SUPPLY) CURRENT REGULATOR 0 VDS DUT 12V BATTERY 0.2µF 50kΩ 0.3µF Qgs Qg(TOT) DUT G VGS Qgd D VDD 0 S Ig(REF) IG CURRENT SAMPLING RESISTOR +VDS ID CURRENT SAMPLING RESISTOR FIGURE 19. GATE CHARGE TEST CIRCUIT 4-99 0 Ig(REF) FIGURE 20. GATE CHARGE WAVEFORMS IRFF9120 All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification. Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. 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