IRFF220 Data Sheet March 1999 3.5A, 200V, 0.800 Ohm, N-Channel Power MOSFET • 3.5A, 200V • rDS(ON) = 0.800Ω • Single Pulse Avalanche Energy Rated • SOA is Power Dissipation Limited • Nanosecond Switching Speeds • Linear Transfer Characteristics • High Input Impedance • Related Literature - TB334 “Guidelines for Soldering Surface Mount Components to PC Boards” Formerly developmental type TA9600. Ordering Information PACKAGE 1889.3 Features This N-Channel enhancement mode silicon gate power field effect transistor is an advanced power MOSFET designed, tested, and guaranteed to withstand a specified level of energy in the breakdown avalanche mode of operation. All of these power MOSFETs are designed for applications such as switching regulators, switching convertors, motor drivers, relay drivers, and drivers for high power bipolar switching transistors requiring high speed and low gate drive power. These types can be operated directly from integrated circuits. PART NUMBER File Number Symbol BRAND D IRFF220 TO-205AF IRFF220 NOTE: When ordering, include the entire part number. G S Packaging JEDEC TO-205AF DRAIN (CASE) SOURCE GATE 1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper ESD Handling Procedures. http://www.intersil.com or 407-727-9207 | Copyright © Intersil Corporation 1999 IRFF220 Absolute Maximum Ratings TC = 25oC, Unless Otherwise Specified Drain to Source Voltage (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .VDS Drain to Gate Voltage (RGS = 20kΩ) (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VDGR Continuous Drain Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ID Pulsed Drain Current (Note 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IDM Gate to Source Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .VGS Maximum Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .PD Linear Derating Factor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Single Pulse Avalanche Energy Rating (Note 4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .EAS Operating and Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TJ, TSTG Maximum Temperature for Soldering Leads at 0.063in (1.6mm) from Case for 10s. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TL Package Body for 10s, See Techbrief 334 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Tpkg IRFF220 200 200 3.5 14 ±20 20 0.16 85 -55 to 150 UNITS V V A A V W W/oC mJ oC 300 260 oC oC CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTE: 1. TJ = 25oC to 125oC. TC = 25oC, Unless Otherwise Specified Electrical Specifications MIN TYP MAX UNITS Drain to Source Breakdown Voltage PARAMETER SYMBOL BVDSS VGS = 0V, ID = 250µA (Figure 10) 200 - - V Gate to Threshold Voltage VGS(TH) VGS = VDS, ID = 250µA 2.0 - 4.0 V - - 25 µA VDS = 0.8 x Rated BVDSS , VGS = 0V, TJ = 125oC - - 250 µA VDS > ID(ON) x rDS(ON)MAX , VGS = 10V (Figure 7) 3.5 - - A Zero-Gate Voltage Drain Current On-State Drain Current (Note 2) IDSS ID(ON) Gate to Source Leakage Forward Drain to Source On Resistance (Note 2) Forward Transconductance (Note 2) Turn-On Delay Time IGSS rDS(ON) gfs td(ON) Rise Time tr Turn-Off Delay Time td(OFF) Fall Time tf Total Gate Charge (Gate to Source + Gate to Drain) Qg(TOT) Gate to Source Charge Qgs Gate to Drain “Miller” Charge Qgd Input Capacitance CISS Output Capacitance Reverse Transfer Capacitance TEST CONDITIONS VDS = Rated BVDSS, VGS = 0V VGS = ±20V - - ±100 nA VGS = 10V, ID = 2.0A (Figures 8, 9) - 0.5 0.800 Ω VDS > ID(ON) x rDS(ON)MAX , ID = 2.0A (Figure 12) 1.5 2.25 - S VDD = 0.5 x Rated BVDSS, RG = 9.1Ω, VGS = 10V, ID ≈ 3.5A (Figures 17, 18) RL = 27.4Ω for VDSS = 100V, RL = 20.3Ω for VDSS = 75V, MOSFET Switching Times are Essentially Independent of Operating Temperature - 20 40 ns VGS = 10V, ID = 3.5A, VDS = 0.8 x Rated BVDSS, Ig(REF) = 1.5mA (Figures 14, 19, 20) Gate Charge is Essentially Independent of Operating Temperature - 30 60 ns - 50 100 ns - 30 60 ns - 11 15 nC - 5.0 - nC - 6.0 - nC - 450 - pF COSS - 150 - pF CRSS - 40 - pF - 5.0 - nH - 15 - nH - - 6.25 oC/W - - 175 oC/W VGS = 0V, VDS = 25V, f = 1.0MHz (Figure 11) Internal Drain Inductance LD Measured from the Drain Lead, 5mm (0.2in) from Header to Center of Die Internal Source Inductance LS Measured from the Source Lead, 5mm (0.2in) from Header and Source Bonding Pad Modified MOSFET Symbol Showing the Internal Device Inductances D LD G LS S Junction to Case RθJC Junction to Ambient RθJA 2 Free Air Operation IRFF220 Source to Drain Diode Specifications PARAMETER SYMBOL Continuous Source to Drain Current ISD Pulse Source to Drain Current (Note 3) ISDM TEST CONDITIONS MIN TYP MAX UNITS - - 3.5 A - - 14 A TJ = 25oC, ISD = 3.5A, VGS = 0V (Figure 13) - - 2.0 V TJ = 150oC, ISD = 3.5A, dISD/dt = 100A/µs TJ = 150oC, ISD = 3.5A, dISD/dt = 100A/µs - 350 - ns - 2.3 - µC Modified MOSFET Symbol Showing the Integral Reverse P-N Junction Rectifier D G S Source to Drain Diode Voltage (Note 2) VSD Reverse Recovery Time trr Reverse Recovered Charge QRR NOTES: 2. Pulse test: pulse width ≤ 300µs, duty cycle ≤ 2%. 3. Repetitive rating: pulse width limited by Max junction temperature. See Transient Thermal Impedance curve (Figure 3). 4. VDD = 20V, start TJ = 25oC, L = 12.5mH, RG = 50Ω, peak IAS = 3.5A (Figures 15, 16). Typical Performance Curves 5 ID, DRAIN CURRENT (A) 1.0 0.8 0.6 0.4 0.2 0 0 50 100 4 3 2 1 0 25 150 50 TC, CASE TEMPERATURE (oC) 75 100 125 150 TC , CASE TEMPERATURE (oC) FIGURE 1. NORMALIZED POWER DISSIPATION vs CASE TEMPERATURE FIGURE 2. MAXIMUM CONTINUOUS DRAIN CURRENT vs CASE TEMPERATURE 2 1.0 THERMAL IMPEDANCE ZθJC, NORMALIZED TRANSIENT POWER DISSIPATION MULTIPLIER 1.2 0.5 0.2 PDM 0.1 0.1 t1 0.05 t2 0.02 NOTES: DUTY FACTOR: D = t1/t2 TJ = PDM x ZθJC x RθJC + TC 0.01 SINGLE PULSE 0.01 10-5 10-4 10-3 10-2 0.1 t1, SQUARE WAVE PULSE DURATION (s) FIGURE 3. NORMALIZED MAXIMUM TRANSIENT THERMAL IMPEDANCE 3 1 10 IRFF220 Typical Performance Curves (Continued) 50 10 VGS = 7V 10V 10µs 10 ID, DRAIN CURRENT (A) ID, DRAIN CURRENT (A) 80µs PULSE TEST 100µs 1ms OPERATION IN THIS AREA IS LIMITED BY rDS(ON) 1.0 10ms 100ms TC = 25oC DC 0.1 TJ = MAX RATED SINGLE PULSE 0.05 1 10 100 VDS , DRAIN TO SOURCE VOLTAGE (V) 8 VGS = 6V 6 4 VGS = 5V 2 VGS = 4V 0 1000 0 80 100 10 8V VGS = 10V 4 VGS = 6V VGS = 5V 3 2 1 VDS > ID(ON) x rDS(ON) MAX ID, ON-STATE DRAIN CURRENT (A) 80µs PULSE TEST ID, DRAIN CURRENT (A) 60 FIGURE 5. OUTPUT CHARACTERISTICS 5 VGS = 4V 80µs PULSE TEST 8 6 4 TJ = 125oC TJ = -25oC TJ = -55oC 2 0 0 0 2 4 6 8 VDS, DRAIN TO SOURCE VOLTAGE (V) 0 10 FIGURE 6. SATURATION CHARACTERISTICS 2 4 6 8 VGS, GATE TO SOURCE VOLTAGE (V) 10 FIGURE 7. TRANSFER CHARACTERISTICS 2.2 1.5 NORMALIZED DRAIN TO SOURCE ON RESISTANCE CURRENT PULSE 2µs TJ = 25oC ON RESISTANCE (Ω) 40 VDS , DRAIN TO SOURCE VOLTAGE (V) FIGURE 4. FORWARD BIAS SAFE OPERATING AREA rDS(ON), DRAIN TO SOURCE 20 1.0 VGS = 10V VGS = 20V 0.5 ID = 2A VGS = 10V 1.8 1.4 1.0 0.6 0.2 0 5 10 15 ID, DRAIN CURRENT (A) NOTE: Heating effect of 2µs pulse is minimal. FIGURE 8. DRAIN TO SOURCE ON RESISTANCE vs GATE VOLTAGE AND DRAIN CURRENT 4 20 -40 0 40 80 120 TJ, JUNCTION TEMPERATURE (oC) FIGURE 9. NORMALIZED DRAIN TO SOURCE ON RESISTANCE vs JUNCTION TEMPERATURE 160 IRFF220 Typical Performance Curves 1000 ID = 250µA 1.15 C, CAPACITANCE (pF) NORMALIZED DRAIN TO SOURCE BREAKDOWN VOLTAGE 1.25 (Continued) 1.05 0.95 0.85 VGS = 0V, f = 1MHz CISS = CGS + CGD CRSS = CGD COSS ≈ CDS + CGS 800 600 CISS 400 200 COSS CRSS 0.75 -40 0 40 80 0 160 120 10 20 30 40 VDS, DRAIN TO SOURCE VOLTAGE (V) TJ, JUNCTION TEMPERATURE (oC) FIGURE 10. NORMALIZED DRAIN TO SOURCE BREAKDOWN VOLTAGE vs JUNCTION TEMPERATURE FIGURE 11. CAPACITANCE vs DRAIN TO SOURCE VOLTAGE 5 102 ISD, SOURCE TO DRAIN CURRENT (A) TJ = -55oC TJ = 25oC 3 TJ = 125oC 2 1 0 0 2 4 6 ID, DRAIN CURRENT (A) 8 TJ = 25oC TJ = 150oC 10 TJ = 150oC TJ = 25oC 1 2 1 3 VSD, SOURCE TO DRAIN VOLTAGE (V) 0 10 FIGURE 12. TRANSCONDUCTANCE vs DRAIN CURRENT FIGURE 13. SOURCE TO DRAIN DIODE VOLTAGE 20 VGS, GATE TO SOURCE VOLTAGE (V) gfs, TRANSCONDUCTANCE (S) 80µs PULSE TEST 4 ID = 3.5A VDS = 40V VDS = 100V VDS = 160V 15 10 5 0 0 4 8 12 16 20 Qg(TOT), TOTAL GATE CHARGE (nC) FIGURE 14. GATE TO SOURCE VOLTAGE vs GATE CHARGE 5 50 4 IRFF220 Test Circuits and Waveforms VDS BVDSS L tP VARY tP TO OBTAIN IAS + RG REQUIRED PEAK IAS - VGS VDS VDD VDD DUT tP 0V IAS 0 0.01Ω tAV FIGURE 15. UNCLAMPED ENERGY TEST CIRCUIT FIGURE 16. UNCLAMPED ENERGY WAVEFORMS tON tOFF td(ON) td(OFF) tf tr RL VDS 90% 90% + RG - VDD 10% 10% 0 DUT 90% VGS VGS 0 FIGURE 17. SWITCHING TIME TEST CIRCUIT 0.2µF 50% PULSE WIDTH 10% FIGURE 18. RESISTIVE SWITCHING WAVEFORMS VDS (ISOLATED SUPPLY) CURRENT REGULATOR 12V BATTERY 50% VDD Qg(TOT) SAME TYPE AS DUT 50kΩ Qgd 0.3µF VGS Qgs D VDS DUT G 0 Ig(REF) S 0 IG CURRENT SAMPLING RESISTOR VDS ID CURRENT SAMPLING RESISTOR FIGURE 19. GATE CHARGE TEST CIRCUIT 6 Ig(REF) 0 FIGURE 20. GATE CHARGE WAVEFORM IRFF220 All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification. Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. 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