Cascadable Silicon Bipolar MMIC␣ Amplifier Technical Data MSA-1100 • High Dynamic Range Cascadable 50␣ Ω or 75␣ Ω Gain Block • 3 dB Bandwidth: 50␣ MHz to 1.6␣ GHz • 12␣ dB Typical 50␣ Ω Gain at 0.5␣ GHz • 3.5␣ dB Typical Noise Figure at 0.5␣ GHz Description The MSA-1100 is a high performance silicon bipolar Monolithic Microwave Integrated Circuit (MMIC) chip. This MMIC is designed for high dynamic range in either 50 or 75␣ Ω systems by The MSA-series is fabricated using HP’s 10 GHz fT, 25␣ GHz f MAX, silicon bipolar MMIC process which uses nitride self-alignment, ion implantation, and gold metallization to achieve excellent performance, uniformity and reliability. The use of an external bias resistor for temperature and current stability also allows bias flexibility. The recommended assembly procedure is gold-eutectic die attach at 400°C and either wedge or ball bonding using 0.7 mil gold wire. Typical Biasing Configuration R bias (Required) VCC ≥ 8 V C Fbk RFC (Optional) 4 C block 3 IN 1 5965-9555E OUT MSA 2 3 5 2 • 17.5 dBm Typical P1dB at 0.5␣ GHz C block Chip Outline[1] AK combining low noise figure with high IP3. Typical applications include narrow and broadband linear amplifiers in industrial and military systems. Features Vd = 5.5 V 6-450 1 4 This chip is intended to be used with an external blocking capacitor completing the shunt feedback path (closed loop). Data sheet characterization is given for a 200␣ pF capacitor. Low frequency performance can be extended by using a larger valued capacitor.[1] Note: 1. Refer to the APPLICATIONS section “Silicon MMIC Chip Use” for additional information. MSA-1100 Absolute Maximum Ratings Parameter Device Current Power Dissipation[2,3] RF Input Power Junction Temperature Storage Temperature Absolute Maximum[1] 100 mA 650 mW +13 dBm 200°C –65 to 200°C Thermal Resistance[2,4]: θjc[2] = 57°C/W Notes: 1. Permanent damage may occur if any of these limits are exceeded. 2. TMounting␣ Surface (TMS) = 25°C. 3. Derate at 17.5 mW/°C for TMounting␣ Surface > 163°C. 4. The small spot size of this technique results in a higher, though more accurate determination of θjc than do alternate methods. Electrical Specifications[1], TA = 25°C Symbol Parameters and Test Conditions[2]: Id = 60 mA, ZO = 50 Ω GP Power Gain (|S21| 2) f = 0.1 GHz ∆GP Gain Flatness f = 0.1 to 1.0 GHz f3 dB 3 dB Bandwidth[3] VSWR Units Min. Typ. dB 12.5 dB ± 0.7 GHz 1.6 Input VSWR f = 0.1 to 1.0 GHz 1.7:1 Output VSWR f = 0.1 to 1.0 GHz 1.9:1 NF 50 Ω Noise Figure f = 0.5 GHz dB 3.5 P1 dB Output Power at 1 dB Gain Compression f = 0.5 GHz dBm 17.5 IP3 Third Order Intercept Point f = 0.5 GHz dBm 30.0 tD Group Delay f = 0.5 GHz psec 125 Vd Device Voltage dV/dT Device Voltage Temperature Coefficient V mV/°C 4.5 5.5 Max. 6.5 –8.0 Notes: 1. The recommended operating current range for this device is 40 to 75 mA. Typical performance as a function of current is on the following page. 2. RF performance of the chip is determined by packaging and testing 10 devices per wafer. 3. Referenced from 0.05 GHz gain (G P). Part Number Ordering Information Part Number MSA-1100-GP4 Devices Per Tray 100 6-451 MSA-1100 Typical Scattering Parameters[1,2] (TA = 25°C, Id = 60 mA) S21 S11 S12 S22 Freq. GHz Mag Ang dB Mag Ang dB Mag Ang Mag Ang k 0.001 0.005 0.010 0.050 0.100 0.200 0.400 0.600 0.800 1.000 1.500 2.000 2.500 3.000 3.500 4.000 .72 .19 .16 .04 .05 .07 .14 .19 .25 .31 .40 .47 .50 .52 .51 .50 –26 –73 –69 –59 –66 –78 –92 –102 –110 –117 –132 –145 –150 –158 –164 –169 19.3 14.1 13.9 12.8 12.8 12.8 12.7 12.5 12.3 12.0 10.9 9.6 8.3 7.0 5.7 4.6 9.23 5.09 4.97 4.39 4.38 4.36 4.31 4.22 4.11 4.00 3.52 3.01 2.60 2.23 1.92 1.70 168 165 168 175 175 170 162 153 144 137 117 100 89 77 68 61 –23.4 –16.7 –16.6 –16.0 –16.0 –15.9 –15.6 –15.3 –14.9 –14.4 –13.4 –12.6 –12.0 –11.6 –11.1 –10.5 .067 .147 .148 .159 .158 .161 .165 .171 .180 .190 .214 .235 .251 .263 .278 .297 46 11 9 3 2 4 7 10 13 14 15 14 16 17 19 22 .72 .19 .16 .04 .05 .08 .14 .21 .27 .33 .42 .46 .45 .42 .38 .34 –27 –77 –79 –102 –100 –100 –105 –111 –116 –122 –136 –148 –152 –156 –155 –152 .52 .96 .99 1.06 1.06 1.05 1.01 .96 .90 .83 .70 .64 .63 .66 .73 .79 Notes: 1. S-parameters are de-embedded from 200 mil BeO package measured data using the package model found in the DEVICE MODELS section. 2. S-parameter data assumes an external 200 pF capacitor. Low frequency performance can be extended using a larger valued capacitor. 6-452 Typical Performance, TA = 25°C 24 14 21 0.1 GHz 0.5 GHz 12 18 18 P1 dB 17 16 15 13 10 9 6 11 6 Open Loop Closed Loop 3 12 GP 2.0 GHz 8 NF (dB) 12 4 0 .02 .05 .1 .3 .5 1.0 2.0 3.0 NF 4 3 20 40 60 –55 –25 80 +25 +85 +125 I d (mA) TEMPERATURE (°C) Figure 2. Power Gain vs. Current. Figure 3. Output Power at 1 dB Gain Compression, Noise Figure and Power Gain vs. Case Temperature, f = 0.5 GHz, Id = 60 mA. FREQUENCY (GHz) Figure 1. Typical Power Gain vs. Frequency, Id = 60 mA. 5 22 P1 dB (dBm) 20 18 16 14 I d = 75 mA I d = 60 mA I d = 40 mA 5.0 4.0 NF (dB) 12 3.0 0.1 0.2 0.3 0.5 1.0 2.0 FREQUENCY (GHz) Figure 4. Output Power at 1 dB Gain Compression and Noise Figure vs. Frequency. MSA-1100 Bonding Diagram MSA-1100 Chip Dimensions A11 Ground 5 MSA Die 2 1 4 Output Trace (3) Output (Backside Contact) (4) Optional 3 Topside Output* 5 Capacitor (200 pF typ) 335 µm 13.2 mil 2 3 (backside contact) (2) Ground AK Input Trace Gp (dB) 1.0 GHz GHz, 1.0 Gp (dB) G p (dB) P1 dB (dBm) (Unless otherwise noted, performance is for a MSA-1100 used with an external 200␣ pF capacitor. See bonding diagram.) Ground (1) Input 4 1 Numbers refer to pin contacts listed on the Chip Outline. 495 µm 19.5 mil Bondpad for Feedback Capacitor (5) Unless otherwise specified, tolerances are ±13 µm / ±0.5 mils. Chip thickness is 114 µm / 4.5 mil. Bond Pads are 41 µm / 1.6 mil typical on each side. * Output contact is made by die attaching the backside of the die. 6-453