VISHAY SI4720CY

Si4720CY
Vishay Siliconix
Battery Disconnect Switch
Level-Shifted Gate Drive with Internal MOSFET
Two Independent Inputs
Ultra Low Power Consumption in Off State
(Leakage Current Only)
Logic Supply Voltage is Not Required
Solution for Bi-Directional Blocking
Bi-Directional Conduction Switch
6- to 30-V Operation
Ground Referenced Logic Level Inputs
Integrated Low rDS(on) MOSFET
The Si4720CY is two level-shifted p-channel MOSFETs.
Operating together, these MOSFETs can be used as a reverse
blocking switch for battery disconnect applications. It is a
solution for multiple battery technology designs or designs that
require isolation from the power bus during charging.
The Si4720CY is available in a 16-pin SOIC package and is
rated for the commercial temperature range of –25 to 85C.
6
IN1
5
9, 10, 11
ESD
GND1
Logic
and
Gate
Drive
G1
D1
Level
Shift
12
VGS
Limiter
7, 8
S1
Half a circuit shown here.
Document Number: 70664
S-49524—Rev. B, 21-Jul-97
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Si4720CY
Vishay Siliconix
Voltage Referenced to GND
VS, VDa . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to 32 V
VSD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to 30 V
VIN1, VIN2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to 15 V
VGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 V
Storage Temperature . . . . . . . . . . . . . . . . . . . –55 to 150C
Power Dissipationb
(t = 10 sec) . . . . . . . . . . . . . . . . 2.5 W
(t = steady state) . . . . . . . . . . . 1.5 W
Notes
a. VSD ≤ 30 VDC
b. Device mounted with all leads soldered to 1” x 1” FR4 with laminated
copper PC board.
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation
of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
VS, VD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 V to 30 V
VIN1, VIN2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 V to 13.2 V
IDS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 A to 6 A
Operating Temperature Range . . . . . . . . . . . . –25 to 85C
Junction Temperature . . . . . . . . . . . . . . . . . . . –25 to 150C
P
Parameter
On-Resistance
Leakage Current
S b l
Symbol
Tempa
rDS
VS = 10 V, ID = 1 A, VIN = H
Room
IDS(off)
VDS = 10 V
Room
IS(off)
Supply Current
IS(on)
Input Voltage Low
VINL
Input Voltage High
VINH
Input Leakage Current
IINH
Turn-On Delay
Turn-Off Delay
IN
t D or S
to
Limits
Test Conditions
Unless Otherwise Specified
tON(IN)
Minb
Typc
Maxb
Unit
0.0155
0.020
1
Room
VS = 21 V
1
Room
VS = 10 V and VS = 21 V
VIN = 5.0 V
VS = 10 V, RL = 5 ,, Figure 1
1.1
Full
Full
1
2.5
Full
Room
5
2.2
A
A
6
2.9
10
Room
1.5
2.1
Room
1.05
Room
1.3
2.5
Room
50
100
10.2
18
V
A
tOFF(IN)
Break-Before-Maked
tBBM
Rise Time
tRISE
Fall Time
tFALL
Voltage Across Pin 6 and 7
VGS
VS = 30 V
Room
Forward Diode
VSD
ID = –1 A
Room
VS = 10 V, RL = 5 ,, Figure 1
s
ns
V
1.1
Notes
a. Room = 25C, Full = as determined by the operating temperature suffix.
b. The algebraic convention whereby the most negative value is a minimum and the most positive a maximum.
c. Typical values are for DESIGN AID ONLY, not guaranteed nor subject to production testing.
d. Guaranteed by design, not subject to production testing.
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Document Number: 70664
S-49524—Rev. B, 21-Jul-97
Si4720CY
Vishay Siliconix
TIMING DIAGRAMS
10 V
SOURCE
50%
50%
VIN
0V
90%
DRAIN
VD
90%
10%
10%
5Ω
tON(IN)
tOFF(IN)
tr
tf
FIGURE 1.
PIN CONFIGURATION AND TRUTH TABLE
VIN1
VIN2
Switch 1
Switch 2
0
0
Off
Off
0
1
Off
On
SO-16
D2
1
16
S2
D2
2
15
S2
D2
3
14
G2(OUT)
4
13
IN2
12
GND1
1
0
On
Off
GND2
1
1
On
On
IN1
5
G1(OUT)
6
11
D1
S1
7
10
D1
S1
8
9
D1
Top View
Order Number: Si4720CY
PIN DESCRIPTION (SUBJECT TO CHANGE)
Pin Number
Symbol
1, 2, 3
D2
4, 12
GND
5
IN1
6
G1(OUT)
Description
Drain connection for MOSFET-2.
Ground
Logic input, IN1. High level turns on the switch.
Gate output to MOSFET-1.
7, 8
S1
Source connection for MOSFET-1
9, 10, 11
D1
Drain connection for MOSFET-1.
13
IN2
Logic input, IN2. High level turns on the switch.
14
G2(OUT)
15, 16
S2
Document Number: 70664
S-49524—Rev. B, 21-Jul-97
Gate output to MOSFET-2.
Source connection for MOSFET-2.
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Si4720CY
Vishay Siliconix
On-Resistance vs. Drain Current
On-Resistance vs. Source Voltage
0.10
r DS(on) – Drain-Source On-Resistance ( Ω )
r DS(on) – Drain-Source On-Resistance ( Ω )
0.030
0.025
0.020
VS = 10 V
0.015
0.010
0.005
0.08
0.06
0.04
IS = 1 A
0.02
0
0.000
0
1
2
3
4
5
0
6
2
4
6
Normalized On-Resistance vs.
Junction Temperature
12
14
16
18
20
Output Capacitance vs. Source Voltage
1.8
2500
VS = 10 V
IS = 1 A
2000
1.4
C OSS (pF)
r DS(on) – On-Resistance ( Ω )
(Normalized)
10
VS (V)
IS (A)
1.6
8
1.2
1.0
1500
1000
VIN = 0 V
0.8
500
0.6
0.4
–50
0
–25
0
25
50
75
100
125
150
0
5
10
TJ – Junction Temperature (C)
10.000
15
20
25
30
VS (V)
On-Supply Current vs. Source Voltage
Off-Supply Current vs. Source Voltage
10.000
TJ = 150C
TJ = 150C
1.000
1.000
I S ( µA)
I S ( µA)
TJ = 25C
0.100
0.100
TJ = 25C
0.010
0.001
0
0.010
5
10
15
VS (V)
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2-4
20
25
30
0.001
0
5
10
15
20
25
30
VS (V)
Document Number: 70664
S-49524—Rev. B, 21-Jul-97
Si4720CY
Vishay Siliconix
Input Voltage Trip Point vs. Temperature
Drain-Source Diode Forward Voltage
10
1.8
I S – Source Current (A)
1.6
V IN Trip Point
TJ = 150C
TJ = 25C
1.4
VS = 21 V
1.2
VS = 10 V
1.0
0.8
–50
1
0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
–25
VSD – Source-to-Drain Voltage (V)
Turn-On Delay vs. Temperature
1.8
3.2
1.6
t d(off) (µs)
t d(on) (µs)
100
125
150
125
150
125
150
VS = 10 V
Rl = 5 Ω
2.8
2.4
1.4
1.2
–25
0
25
50
75
100
125
1.0
–50
150
–25
0
Temperature (C)
25
50
75
100
Temperature (C)
Rise Time vs. Temperature
Fall Time vs. Temperature
80
1.8
VS = 10 V
Rl = 5 Ω
70
VS = 10 V
Rl = 5 Ω
60
t fall (ns)
1.4
t rise (µs)
75
Turn-off Delay vs. Temperature
3.6
1.2
50
1.0
40
0.8
30
0.6
–50
50
2.0
VS = 10 V
Rl = 5 Ω
1.6
25
TA = Ambient Temperature (C)
4.0
2.0
–50
0
–25
0
25
50
75
Temperature (C)
Document Number: 70664
S-49524—Rev. B, 21-Jul-97
100
125
150
20
–50
–25
0
25
50
75
100
Temperature (C)
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Si4720CY
Vishay Siliconix
Single Pulse Power
80
Power (W)
60
40
20
0
0.01
0.1
1
10
100
Time (sec)
Normalized Thermal Transient Impedance, Junction-to-Ambient
2
1
Thermal Impedance
Duty Cycle = 0.5
0.2
Notes:
0.1
0.1
PDM
0.05
t1
t2
1. Duty Cycle, D =
0.02
t1
t2
2. Per Unit Base = RthJA = 125C/W
3. TJM – TA = PDMZthJA(t)
Single Pulse
0.01
10–4
4. Surface Mounted
10–3
10–2
10–1
1
10
100
Square Wave Pulse Duration (sec)
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Document Number: 70664
S-49524—Rev. B, 21-Jul-97
Si4720CY
Vishay Siliconix
Si4720CY
Si4435DY
D1
S1
Battery 1
G1
Drive
Logic In 1
Si4435DY
D2
S2
DC/DC
Battery 2
G2
Drive
Logic In 2
FIGURE 2.
S1
S2
G1
G2
Drive
Si4720CY
D1
Drive
D2
Logic In
Battery 2
DC/DC
S1
Si4720CY
G1
S2
Drive
D1
Battery 1
G2
Drive
D2
Logic In
FIGURE 3.
Document Number: 70664
S-49524—Rev. B, 21-Jul-97
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Si4720CY
Vishay Siliconix
1/2 Si4720
AC/DC
Display
Power
1/2 Si4720
Charger
Logic In
7 – 30 V
3 – 5 Cell
Li-Ion
Logic In
Drive
Drive
DC/DC
5V
3.3 V
FIGURE 4. Low-Cost Laptop PC
1/2 Si4720
1/2 Si4720
Display
Power
AC/DC
Charger
Logic In
Logic In
Drive
Drive
DC/DC
7 – 30 V
3 – 5 Cell
Li-Ion
5V
3.3 V
1/2 Si4720
1/2 Si4720
Si6415
Logic In
7 – 30 V
3 – 5 Cell
Li-Ion
Drive
Logic In
Drive
1/2 Si4720
1/2 Si4720
Si6415
Logic In
Drive
Logic In
Drive
FIGURE 5. High-Performance Laptop PC
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Document Number: 70664
S-49524—Rev. B, 21-Jul-97