Circuit Note CN-0232 Devices Connected/Referenced Fractional-N PLL Synthesizer with ADF4350 Integrated VCO Circuits from the Lab™ reference circuits are engineered and tested for quick and easy system integration to help solve today’s analog, mixed-signal, and RF design challenges. For more information and/or support, visit www.analog.com/CN0232. ADF4153 Fractional-N PLL Frequency Synthesizer Minimizing Spurious Outputs Using a Synthesizer with an Integrated VCO and an External PLL Circuit EVALUATION AND DESIGN SUPPORT CIRCUIT FUNCTION AND BENEFITS Circuit Evaluation Boards ADF4350 Evaluation Board (EVAL-ADF4350EB2Z) ADF4153 Evaluation Board (EVAL-ADF4153EBZ1) Design and Integration Files Schematics, Layout Files, Bill of Materials The circuit shown in Figure 1 uses the ADF4350 synthesizer with an integrated VCO and an external PLL to minimize spurious outputs by isolating the PLL synthesizer circuitry from the VCO circuit. DVDD 10 1nF 1nF 26 4 29 REFIN 6 30 32 VP 28 VVCO 25 1nF RFOUTA+ 1nF 51Ω 1nF RFOUTB+ RFOUTB+ 14 51Ω RFOUTB– 15 VVCO 1 CLK SPI COMPATIBLE SERIAL BUS 51Ω 51Ω MUXOUT LD SDVDD 17 VVCO LOCK DETECT VDD CE 16 3.3V PDBRF VVCO AVDD 3.3V PHASE FREQUENCY DETECTOR 2 DATA 3 LE CHARGE PUMP VCO 22 RSET 51Ω 51Ω RFOUTA– 13 4.7kΩ COUNTERS RFOUTA+ 12 1nF 51Ω VTUNE 20 ADF4350 CPOUT 7 REFERENCE VCO TUNING VOLTAGE SW 5 CPGND SDGND AGND AGNDVCO DGND TEMP VCOM VREF TCXO 26MHz 8 31 9 11 18 21 27 10pF 3.3V 19 0.1µF 23 24 10pF 0.1µF 10pF 0.1µF VDD 7 15 16 AVDD DVDD VP 10 SDVDD 14 MUXOUT 1nF 1nF 8 REFIN PHASE FREQUENCY DETECTOR 12 DATA CHARGE PUMP CP 2 LOOP FILTER 360Ω 100nF 13 LE 22nF 4.7nF 200Ω 1 RSET COUNTERS 4.7kΩ ADF4153 CPGND AGND DGND 3 4 9 100pF RFINA 6 100pF RFINB 5 RF IN 51Ω 51Ω 10125-001 SPI COMPATIBLE SERIAL BUS 11 CLK Figure 1. ADF4153 PLL Connected to ADF4350 (Simplified Schematic: All Connections and Decoupling Not Shown) Rev. 0 Circuits from the Lab™ circuits from Analog Devices have been designed and built by Analog Devices engineers. Standard engineering practices have been employed in the design and construction of each circuit, and their function and performance have been tested and verified in a lab environment at room temperature. However, you are solely responsible for testing the circuit and determining its suitability and applicability for your use and application. Accordingly, in no event shall Analog Devices be liable for direct, indirect, special, incidental, consequential or punitive damages due to any cause whatsoever connected to the use of any Circuits from the Lab circuits. (Continued on last page) One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 ©2012 Analog Devices, Inc. All rights reserved. CN-0232 Circuit Note Devices with integrated PLLs and VCOs may have feed through from the digital PLL circuitry to the VCO, leading to higher spurious levels due to the close proximity of the PLL circuitry to the VCO. The circuit shown in Figure 1 uses the ADF4350, a fully integrated fractional-N PLL and VCO that can generate frequencies from 137.5 MHz to 4400 MHz, together with the ADF4153 PLL. In addition to improvements in spurious performance, another possible advantage of using an external PLL is the possibility of increased frequency resolution. For example, if the ADF4157 PLL is selected in place of the ADF4153, the frequency resolution of the PLL can be as fine as 0.7 Hz. CIRCUIT DESCRIPTION For frequency generation, the internal PLL must be enabled and the desired frequency must be programmed. Then, once sufficient time has elapsed for band select, the internal PLL can be disabled, and, finally, the external PLL can be enabled. The external PLL compares the reference frequency and the VCO output frequency to generate a stable dc voltage to lock the PLL. Figure 2 shows the output frequency spurs measured at RFOUTA+ using the ADF4350 internal PLL and VCO with the ADF4153 PLL disabled. Note the presence of PFD spurs at 13 MHz and 26 MHz. Figure 3 shows the output spurs measured at RFOUTA+ with the ADF4350 internal PLL circuit disabled and the external ADF4153 PLL active. In this mode, the charge pump output of the ADF4153 drives the loop filter, which in turn drives the VTUNE input of the ADF4350. The VTUNE input controls the ADF4350 VCO output frequency. The ADF4350 is a wideband PLL and VCO consisting of three separate multiband VCOs. Each VCO covers a range of approximately 700 MHz (with some overlap between the frequencies of the VCO). This permits a fundamental VCO frequency range of between 2.2 GHz to 4.4 GHz. Frequencies lower than 2.2 GHz can be generated using internal dividers within the ADF4350. COMMON VARIATIONS For most applications, the internal PLL of the ADF4350 is used to lock the VCO. In addition to locking the PLL, the PLL circuitry performs an additional vital function of VCO band select, using the internal reference (R) and feedback (N) counters of the internal PLL to compare the VCO output with the reference input. Different PLLs can be selected. The fractional-N PLL in both the ADF4350 and ADF4153 has a minimum frequency resolution of PFD/4095. If finer resolution is required, the ADF4157 can be selected. The resolution of this PLL is PFD/225, thereby providing an ultrafine resolution of <1 Hz. In making a comparison between Figure 2 and Figure 3, the spurs due to the phase frequency detector (PFD) frequency, at 13 MHz and 26 MHz, in Figure 2 have disappeared into the noise floor in Figure 3. For applications requiring simpler software programmability, the ADF4150 PLL is software compatible with the ADF4350, easing the software programming sequence. Rev. 0 | Page 2 of 6 Circuit Note CN-0232 R&S FSUP SIGNAL SOURCE ANALYZER RESIDUAL NOISE (T1 WITHOUT SPURS) SETTINGS SIGNAL FREQUENCY: SIGNAL LEVEL: CROSS CORR MODE: INTERNAL REF TUNED: 1.6000GHz 5.44dBm HARMONIC 1 INTERNAL PHASE DET PHASE NOISE (dBc/Hz) RF ATTEN: 5dB TOP –70dBc/Hz MARKER 1 (T1) 1kHz –91.84dBc/Hz INT PHN (1.0k .. 30.0M): RESIDUAL PM: RESIDUAL FM: RMS JITTER: MARKER 2 (T1) 10.98633kHz –93.42dBc/Hz SPUR LIST –49.1dBc 1.000MHz 2.001MHz 0.285° 3.000MHz 3.24kHz 0.4946ps 13.000MHz –83.82dBc –99.68dBc –89.92dBc –94.70dBc MARKER 3 (T1) MARKER 4 (T1) 13.00011MHz 26.00002MHz –94.7dBc –87.89dBc –70 LOOP BW 300Hz –80 1 SPUR POWER (dBc) –90 4 2 3 –100 –110 –120 –130 –140 –150 –170 1k 10k 100k 1M 10M 30M FREQUENCY OFFSET (Hz) 10125-002 SPR OFF TH 0dB –160 Figure 2. ADF4350 PFD Spurs at 1.6 GHz R&S FSUP SIGNAL SOURCE ANALYZER RESIDUAL NOISE (T1 WITHOUT SPURS) SETTINGS SIGNAL FREQUENCY: SIGNAL LEVEL: CROSS CORR MODE: INTERNAL REF TUNED: 1.6000GHz 1.71dBm HARMONIC 1 INTERNAL PHASE DET PHASE NOISE (dBc/Hz) RF ATTEN: 5dB TOP –70dBc/Hz MARKER 1 (T1) 1kHz –101.23dBc/Hz INT PHN (1.0k .. 30.0M): RESIDUAL PM: RESIDUAL FM: RMS JITTER: MARKER 2 (T1) 1kHz –101.23dBc/Hz SPUR LIST –53.3dBc 0.174° 1.846kHz 0.3025ps 1000.0kHz –90.44dBc 2.000MHz –85.60dBc 3.000MHz –96.36dBc 4.000MHz –99.28dBc MARKER 3 (T1) MARKER 4 (T1) 100kHz 1MHz –120.62dBc –144.68dBc –70 LOOP BW 300Hz –80 12 –100 –110 3 –120 –130 4 –140 –150 –160 –170 1k SPR OFF TH 0dB 10k 100k 1M 10M 30M FREQUENCY OFFSET (Hz) Figure 3. ADF4350 PFD Spurs at 1.6 GHz Using ADF4153 PLL Rev. 0 | Page 3 of 6 10125-003 SPUR POWER (dBc) –90 CN-0232 Circuit Note CIRCUIT EVALUATION AND TEST Functional Block Diagram The CN-0232 uses the EVAL-ADF4350EB2Z board for evaluation of the described circuit, and with some minor modifications, allows for quick setup and evaluation. The EVAL-ADF4350EB2Z board uses the standard ADF4350 programming software, contained on the CD that accompanies the evaluation board. The EVAL-ADF4153EBZ1 evaluation board comes with the software for the ADF4153 PLL. For this experiment, the EVAL-ADF4153EBZ1 and the EVALADF4350EB2Z are used. The EVAL-ADF4350EB2Z is selected because it contains the auxiliary RFOUTB+ output stage, which is connected via SMA cable to the EVAL-ADF4153EBZ1, as shown in Figure 4. Equipment Needed Both PLLs use the same reference input (REFIN) frequency; therefore, an SMA splitter connects the same REFIN to both boards. • • • • • • The loop filter output on the EVAL-ADF4153EBZ1 is connected to the VTUNE pin of the ADF4350 via a shielded coaxial cable to ensure that no extra noise or spurs appear on the pin. Both parts are programmed separately. It may be necessary to use different PCs for each board to ensure no conflicts occur between hardware drivers. EVAL-ADF4350EB2Z with programming software. EVAL-ADF4153EBZ1 with programming software. 5.5 V power supply. R&S SMA100A signal generator or equivalent. R&S FSUP26 spectrum analyzer or equivalent. Two PCs with Windows® XP, Windows, Vista (32-bit), or Windows 7 (32-bit), one with an USB port and the other with a printer port. Alternatively, the EVAL-ADF4xxxXUSB USB adaptor kit can be used instead of the printer port, if none is available. Getting Started The UG-110 user guide details the installation and use of the EVAL-ADF4350EB2Z evaluation software. UG-110 also contains board setup instructions and the board schematic, layout, and bill of materials. The SMA coaxial cable is required to connect RFOUTB+ of the EVAL-ADF4350EB2Z to RFIN of the EVAL-ADF4153EBZ1. A simple SMA splitter is also needed to share the reference source between the two boards. Some flexible microcoaxial cable is required to connect the output of the ADF4153 loop filter to the ADF4350 VTUNE input. To minimize unwanted interference, both sides of the cable must be grounded to suitable GND points on each board. The UG-167 user guide contains similar information relevant to the EVAL-ADF4153EBZ1. Necessary modifications to the board are the removal of the VCO (Y1). To reconfigure this board as an input, remove the R7 resistor and change R8 and R9 to 0 Ω. The PLL loop filter on the ADF4350 board is unused and should be removed. At this point, the microcoaxial cable can be used to connect the output of the ADF4153 loop filter (T7) to the VTUNE pin of the ADF4350 (T4). It is of critical importance that the outer shielding of this cable is connected to a ground point on both boards. POWER SUPPLY 5.5V COM J14 USB RFOUTA+ J15 RFOUTA− J3 ADF4350 J1 EVALUATION BOARD (EVAL-ADF4350EB2Z) J4 T4 50Ω TERM RFOUTB+ RFOUTB− REFERENCE FREQUENCY GENERATOR (R&S SMA100A) SPECTRUM ANALYZER (R&S FSUP26) J2 PC J5 50Ω TERM VTUNE CP OUT T7 ADF4153 EVALUATION BOARD (EVAL-ADF4153EBZ1) EVALADF4xxxX-USB PC USB PRINTER 9V BATTERY RFIN+ J2 Figure 4. Test Setup Functional Diagram Rev. 0 | Page 4 of 6 10125-004 J5 Circuit Note CN-0232 Initialization Procedure The ADF4350 must go through the band select process for every new frequency. 2. 3. Initialize the ADF4350 as normal (program R5, R4, R3, R2, R1, R0), except set DB4, R2 to 1 (ICP three-state enabled), because the ADF4350 charge pump is unused. Set DB9, R4 to 0 for divided VCO output on RFOUTB+. Enable RFOUTB+ (auxiliary out). This signal is fed to the ADF4153 over the coax cable. Initialize the ADF4153 (as per the data sheet) to accept the VCO output frequency as the RF input frequency. Note that the band select switch is internal; therefore, an external switch to remove the PLL VTUNE is not required. When the ADF4153 achieves lock, the ADF4350 counter reset to 1 (DB3, R2) must be activated. Not activating the counter reset degrades spur performance. Additionally, all ADF4350 synthesizer blocks can be powered down using the test mode bit (DB10, R5). 10125-005 1. Frequency Update 1. 2. 3. 4. 5. Program DB10, R5 to 0 to reactivate the ADF4350 synthesizer blocks. Program DB3, R2 of the ADF4350 to 0 to deactivate the counter reset because these counters are required for band select. Program the ADF4350 and ADF4153 N-counter registers as appropriate for the new frequency. When the ADF4153 achieves lock, the ADF4350 counter reset (DB3, R2) can be activated. Additionally all synthesizer blocks can be powered down using the test mode bit (DB10, R5). Repeat Step 1 to Step 4 as required for new frequencies. Figure 5. ADF4350 Software Window The software screen captures shown in Figure 5 and Figure 6 show the software windows for 26 MHz REFIN (ADF4350) and 13 MHz PFD (ADF4153). 10125-006 After setting up the equipment, use standard RF test methods to measure the spectral purity of the output signal. Figure 6. ADF4153 Software Window Rev. 0 | Page 5 of 6 CN-0232 Circuit Note LEARN MORE CN0232 Design Support Package: http://www.analog.com/CN0232-DesignSupport UG-110, User Guide for the EVAL-ADF4350EB2Z board UG-167, User Guide for the EVAL-ADF4153EBZ1 board MT-031 Tutorial, Grounding Data Converters and Solving the Mystery of “AGND” and “DGND”, Analog Devices. MT-086 Tutorial, Fundamentals of Phase Locked Loops (PLLs), Analog Devices. MT-101 Tutorial, Decoupling Techniques, Analog Devices. ADIsimPLL Design Tool Data Sheets and Evaluation Boards ADF4350 Evaluation Board (EVAL-ADF4350EB2Z) ADF4153 Evaluation Board (EVAL-ADF4153EBZ1) ADF4153 Data Sheet ADF4350 Data Sheet REVISION HISTORY 4/12—Revision 0: Initial Version (Continued from first page) Circuits from the Lab circuits are intended only for use with Analog Devices products and are the intellectual property of Analog Devices or its licensors. While you may use the Circuits from the Lab circuits in the design of your product, no other license is granted by implication or otherwise under any patents or other intellectual property by application or use of the Circuits from the Lab circuits. Information furnished by Analog Devices is believed to be accurate and reliable. However, Circuits from the Lab circuits are supplied "as is" and without warranties of any kind, express, implied, or statutory including, but not limited to, any implied warranty of merchantability, noninfringement or fitness for a particular purpose and no responsibility is assumed by Analog Devices for their use, nor for any infringements of patents or other rights of third parties that may result from their use. Analog Devices reserves the right to change any Circuits from the Lab circuits at any time without notice but is under no obligation to do so. ©2012 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. CN10125-0-4/12(0) Rev. 0 | Page 6 of 6