19-2661; Rev 1; 9/05 Quick-PWM Step-Down Controllers with Inductor Saturation Protection and Dynamic Output Voltages ♦ ♦ ♦ ♦ ♦ ♦ ♦ ♦ ♦ Inductor Saturation Protection Accurate Current Limit Ultra-High Efficiency Quick-PWM with 100ns Load-Step Response MAX1992 1.8V/2.5V Fixed or 0.7V to 5.5V Adjustable Output Range MAX1993 External Reference Input Dynamically Selectable Output Voltage (0.7V to 5.5V) Optional Power-Good and Fault Blanking During Transitions ±1% VOUT Accuracy Over Line and Load 2V to 28V Battery Input Range (VIN) 200/300/450/600kHz Switching Frequency Overvoltage/Undervoltage Protection Option 1.7ms Digital Soft-Start Drives Large Synchronous Rectifier FETs 2V ±0.7% Reference Output Power-Good Window Comparator Ordering Information TEMP RANGE PIN-PACKAGE MAX1992ETG PART -40°C to +85°C 24 Thin QFN 4mm × 4mm MAX1992ETG+ -40°C to +85°C 24 Thin QFN 4mm × 4mm MAX1993ETG -40°C to +85°C 24 Thin QFN 4mm × 4mm MAX1993ETG+ -40°C to +85°C 24 Thin QFN 4mm × 4mm + Denotes lead-free package. Pin Configurations Active Termination Buses (MAX1993) CPU/Chipset/GPU with Dynamic Voltage Cores (MAX1993) BST LX DH V+ SKIP 15 14 13 12 CSN PGND 20 11 CSP AGND 21 VCC 22 MAX1992 10 OUT 9 FB SHDN 23 8 N.C. OVP/UVP 24 7 N.C 1 2 3 4 5 6 REF DDR Memory Termination (MAX1993) 16 ILIM 1.8V and 2.5V Supplies 17 19 N.C. Core/IO Supplies as Low as 0.7V 18 VDD TON Notebook Computers DL TOP VIEW Applications PGOOD Single-stage buck conversion allows the MAX1992/ MAX1993 to directly step down high-voltage batteries for the highest possible efficiency. Alternatively, two-stage conversion (stepping down from another system supply rail instead of the battery) at the maximum switching frequency allows the minimum possible physical size. The MAX1992 powers the CPU core, chipset, DRAM, or other supply rails as low as 0.7V. The MAX1993 powers chipsets and graphics processor cores, which require dynamically adjustable output voltages. The MAX1993 provides a tracking input that can be used for active termination buses. The MAX1992/MAX1993 are available in a 24-pin thin QFN package with optional overvoltage and undervoltage protection. For dual step-down PWM controllers with inductor saturation protection, external reference input voltage, and dynamically selectable output voltages, refer to the MAX1540/MAX1541 data sheet. ♦ ♦ ♦ ♦ ♦ LSAT The MAX1992/MAX1993 pulse-width modulation (PWM) controllers provide high-efficiency, excellent transient response, and high DC output accuracy. The devices step down high-voltage batteries to generate lowvoltage CPU core or chipset/RAM supplies in notebook computers. Maxim’s proprietary Quick-PWM™ quick-response, constant on-time PWM control scheme handles wide input/output voltage ratios with ease and provides 100ns “instant-on” response to load transients, while maintaining a relatively constant switching frequency. Efficiency is enhanced by the ability to drive very large synchronousrectifier MOSFETs. Current sensing to ensure reliable overload and inductor saturation protection is available using an external current-sense resistor in series with the output. Alternatively, the controller can sense the current across the synchronous rectifier alone or use lossless inductor sensing for lowest power dissipation. Features THIN QFN 4mm x 4mm A "+" SIGN WILL REPLACE THE FIRST PIN INDICATOR ON LEAD-FREE PACKAGES. Quick-PWM is a trademark of Maxim Integrated Products, Inc. Pin Configurations continued at end of data sheet. ________________________________________________________________ Maxim Integrated Products For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at 1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com. 1 MAX1992/MAX1993 General Description MAX1992/MAX1993 Quick-PWM Step-Down Controllers with Inductor Saturation Protection and Dynamic Output Voltages ABSOLUTE MAXIMUM RATINGS (Note 1) V+ to AGND............................................................-0.3V to +30V VCC to AGND............................................................-0.3V to +6V VDD to PGND............................................................-0.3V to +6V PGOOD, ILIM, SKIP, SHDN to AGND ......................-0.3V to +6V REFIN, FB, CSP to AGND.........................................-0.3V to +6V GATE, OD to GND (MAX1993 only) .........................-0.3V to +6V TON, OVP/UVP, LSAT to AGND .................-0.3V to (VCC + 0.3V) REF, OUT to AGND ....................................-0.3V to (VCC + 0.3V) FBLANK to GND (MAX1993 only) ..............-0.3V to (VCC + 0.3V) DL to PGND................................................-0.3V to (VDD + 0.3V) CSN to AGND............................................................-2V to +30V DH to LX .....................................................-0.3V to (BST + 0.3V) LX to AGND ...............................................................-2V to +30V BST to LX..................................................................-0.3V to +6V AGND to PGND (MAX1992 only) ..........................-0.3V to +0.3V REF Short Circuit to AGND.........................................Continuous Continuous Power Dissipation (TA = +70°C) 24-Pin 4mm x 4mm Thin QFN (derated 20.8mW/°C above +70°C)...........................1667mW Operating Temperature Range MAX199_ETG ..................................................-40°C to +85°C Junction Temperature ......................................................+150°C Storage Temperature Range .............................-65°C to +150°C Lead Temperature (soldering, 10s) .................................+300°C Note 1: For the MAX1993, AGND and PGND refer to a single pin designated GND. Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ELECTRICAL CHARACTERISTICS (V+ = 15V, VCC = VDD = SHDN = 5V, SKIP = GND, TA = 0°C to +85°C, unless otherwise noted. Typical values are at TA = +25°C.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS PWM CONTROLLER Input Voltage Range Output Voltage Accuracy (MAX1992 Fixed) Feedback Voltage Accuracy (MAX1992 Adjustable) Feedback Voltage Accuracy (MAX1993) VIN VBIAS VCC, VDD VOUT MAX1992 V+ = 4.5V to 28V, SKIP = VCC (Note 2) FB = VCC 1.782 1.8 1.818 0.693 0.7 0.707 REFIN = 0.35 × REF 0.693 0.7 0.707 REFIN = REF 1.980 2 2.020 VFB MAX1993 V+ = 4.5V to 28V, SKIP = VCC (Note 2) 0.1 VCC = 4.5V to 5.5V, V+ = 4.5V to 28V IFB MAX1992 % 0.25 % -0.1 +0.1 µA 0.7 5.5 V FB = GND 90 190 FB = VCC or adjustable 70 145 270 400 800 1400 10 25 Ω 0.3 0.4 V RDISCHARGE 0.2 tSS V V ILOAD = 0 to 3A, SKIP = VCC ROUT V V OUT Synchronous Rectifier Discharge Mode Turn-On Level 2 5.5 2.525 MAX1993 Soft-Start Ramp Time 4.5 2.5 Output Adjust Range OUT Discharge Mode On-Resistance 28 2.475 MAX1992 V+ = 4.5V to 28V, SKIP = VCC (Note 2) Line Regulation Error OUT Input Resistance 2 FB = GND VFB Load Regulation Error FB Input Bias Current Battery voltage, V+ Rising edge on SHDN to full current limit 1.7 _______________________________________________________________________________________ 350 kΩ ms Quick-PWM Step-Down Controllers with Inductor Saturation Protection and Dynamic Output Voltages MAX1992/MAX1993 ELECTRICAL CHARACTERISTICS (continued) (V+ = 15V, VCC = VDD = SHDN = 5V, SKIP = GND, TA = 0°C to +85°C, unless otherwise noted. Typical values are at TA = +25°C.) PARAMETER SYMBOL CONDITIONS TON = GND (600kHz) On-Time tON Minimum Off-Time tOFF(MIN) Quiescent Supply Current (VCC) ICC Quiescent Supply Current (VDD) IDD Quiescent Supply Current (V+) IV+ V+ = 15V, VOUT = 1.5V (Note 3) MIN TYP MAX 170 194 219 TON = REF (450kHz) 213 243 273 TON = open (300kHz) 316 352 389 TON = VCC (200kHz) 461 516 571 (Note 3) 400 500 FB forced above the regulation point, LSAT = GND 0.55 0.85 UNITS ns ns mA FB forced above the regulation point, VLSAT > 0.5V 1 <1 5 µA 25 40 µA SHDN = GND <1 7 µA Shutdown Supply Current (VDD) SHDN = GND <1 5 µA Shutdown Supply Current (V+) SHDN = GND, V+ = 28V, VCC = VDD = 0 or 5V <1 5 µA Shutdown Supply Current (VCC) FB forced above the regulation point REFERENCE Reference Voltage VREF Reference Load Regulation REF Lockout Voltage ΔVREF VCC = 4.5V to 5.5V, IREF = 0 TA = +25°C to +85°C 1.986 2 2.014 TA = 0°C to +85°C 1.983 2 2.017 IREF = -10µA to 50µA REFIN Voltage Range REFIN Input Bias Current -0.01 VREF(UVLO) Rising edge, hysteresis = 350mV +0.01 1.95 0.7 IREFIN V V V VREF V 0.01 0.05 µA 16 20 % FAULT DETECTION With respect to error comparator threshold, OVP/UVP = VCC Overvoltage Trip Threshold Overvoltage Fault Propagation Delay tOVP Output Undervoltage Protection Trip Threshold Output Undervoltage Protection Blanking Time Output Undervoltage Fault Propagation Delay tBLANK 12 FB forced 2% above trip threshold 10 With respect to error comparator threshold, OVP/UVP = VCC 65 From rising edge of SHDN 10 tUVP 70 µs 75 % 35 ms 10 µs PGOOD Lower Trip Threshold With respect to error comparator threshold, hysteresis = 1% -13 -10 -7 % PGOOD Upper Trip Threshold With respect to error comparator threshold, hysteresis = 1% +7 +10 +13 % PGOOD Propagation Delay tPGOOD FB forced 2% beyond PGOOD trip threshold 10 µs _______________________________________________________________________________________ 3 MAX1992/MAX1993 Quick-PWM Step-Down Controllers with Inductor Saturation Protection and Dynamic Output Voltages ELECTRICAL CHARACTERISTICS (continued) (V+ = 15V, VCC = VDD = SHDN = 5V, SKIP = GND, TA = 0°C to +85°C, unless otherwise noted. Typical values are at TA = +25°C.) PARAMETER SYMBOL PGOOD Output Low Voltage IPGOOD Fault Blanking Time tFBLANK VCC Undervoltage Lockout Threshold MIN TYP ISINK = 4mA PGOOD Leakage Current Thermal Shutdown Threshold CONDITIONS TSHDN FB = REF (PGOOD high impedance), PGOOD forced to 5.5V MAX UNITS 0.3 V 1 µA FBLANK = VCC 120 218 320 FBLANK = open 80 140 205 FBLANK = REF 35 63 95 Hysteresis = 15°C 160 Rising edge, PWM disabled below this level VUVLO(VCC) hysteresis = 20mV 4.1 4.25 µs °C 4.4 V V CURRENT LIMIT ILIM Adjustment Range Current-Limit Input Range 0.25 2.00 CSP 0 2.7 CSN -0.3 +28.0 -0.5 +0.5 µA 55 mV CSP/CSN Input Current Valley Current-Limit Threshold (Fixed) VLIM(VAL) VCSP - VCSN, ILIM = VCC Valley Current-Limit Threshold (Adjustable) VLIM(VAL) VCSP - VCSN Current-Limit Threshold (Negative) VNEG Current-Limit Threshold (Zero Crossing) VZX ILIM Saturation Fault Sink Current IILIM(LSAT) 50 VILIM = 250mV 15 25 35 VILIM = 2.00V 170 200 230 -75 -60 -45 VCSP - VCSN, SKIP = ILIM = VCC, TA = +25°C With respect to valley current-limit threshold, VCSP - VCSN, SKIP = GND, ILIM = VCC With respect to valley current-limit threshold, ILIM = VCC Inductor Saturation Current-Limit Threshold 45 2.5 mV mV mV LSAT = VCC 180 200 220 LSAT = open 157 175 193 LSAT = REF 135 150 165 4 6 8 µA 0.1 µA Ω VCSP - VCSN > inductor saturation current limit, 0.25V < VILIM < 2.0V VCSP - VCSN < inductor saturation current limit ILIM Leakage Current V % GATE DRIVERS DH Gate Driver On-Resistance RDH DL Gate Driver On-Resistance RDL DH Gate Driver Source/Sink Current IDH DL Gate Driver Source Current 4 BST - LX forced to 5V 1.5 5 DL, high state 1.5 5 DL, low state 0.6 3 DH forced to 2.5V, BST - LX forced to 5V IDL(SOURCE) DL forced to 2.5V Ω 1 A 1 A _______________________________________________________________________________________ Quick-PWM Step-Down Controllers with Inductor Saturation Protection and Dynamic Output Voltages MAX1992/MAX1993 ELECTRICAL CHARACTERISTICS (continued) (V+ = 15V, VCC = VDD = SHDN = 5V, SKIP = GND, TA = 0°C to +85°C, unless otherwise noted. Typical values are at TA = +25°C.) PARAMETER DL Gate Driver Sink Current Dead Time SYMBOL IDL(SINK) tDEAD CONDITIONS MIN TYP DL forced to 2.5V 3 DL rising 35 DH rising 26 MAX UNITS A ns INPUTS AND OUTPUTS GATE = VCC 10 25 Ω OD Leakage Current GATE = GND, OD forced to 5.5V 1 200 nA Logic Input Threshold SHDN, SKIP, GATE rising edge, hysteresis = 225mV 1.7 2.20 V Logic Input Current SHDN, SKIP, GATE +1 µA Dual Mode™ Threshold Voltage MAX1992 FB OD On-Resistance ROD TON, OVP/UVP, LSAT, FBLANK Four-Level Input Logic Levels 1.20 -1 High 1.9 2.0 2.1 Low 0.05 0.1 0.15 High VCC 0.4V Open 3.15 3.85 REF 1.65 2.35 Low TON, OVP/UVP, LSAT, FBLANK forced to GND or VCC Four-Level Logic Input Current V V 0.5 -3 +3 µA MAX UNITS ELECTRICAL CHARACTERISTICS (V+ = 15V, VCC = VDD = SHDN = 5V, SKIP = GND, TA = -40°C to +85°C, unless otherwise noted.) (Note 4) PARAMETER SYMBOL CONDITIONS MIN PWM CONTROLLER Input Voltage Range Output Voltage Accuracy (MAX1992 Fixed) Feedback Voltage Accuracy (MAX1992 Adjustable) Feedback Voltage Accuracy (MAX1993) VIN Battery voltage, V+ VBIAS VCC, VDD VOUT MAX1992, V+ = 4.5V to 28V, SKIP = VCC (Note 2) 2 28 4.5 5.5 FB = GND 2.462 2.538 FB = VCC 1.773 1.827 0.689 0.711 REFIN = 0.35 × REF 0.689 0.711 REFIN = REF 1.970 2.030 170 219 V VFB MAX1992, V+ = 4.5V to 28V, SKIP = VCC (Note 2) VFB MAX1993, V+ = 4.5V to 28V, SKIP = VCC (Note 2) On-Time tON V V TON = GND (600kHz) V+ = 15V, VOUT = 1.5V (Note 3) V TON = REF (450kHz) 213 273 TON = open (300kHz) 316 389 TON = VCC (200kHz) 461 571 ns Dual Mode is a trademark of Maxim Integrated Products, Inc. _______________________________________________________________________________________ 5 MAX1992/MAX1993 Quick-PWM Step-Down Controllers with Inductor Saturation Protection and Dynamic Output Voltages ELECTRICAL CHARACTERISTICS (continued) (V+ = 15V, VCC = VDD = SHDN = 5V, SKIP = GND, TA = -40°C to +85°C, unless otherwise noted.) (Note 4) PARAMETER Minimum Off-Time Quiescent Supply Current (VCC) SYMBOL tOFF(MIN) ICC Quiescent Supply Current (VDD) IDD Quiescent Supply Current (V+) IV+ MAX UNITS (Note 3) CONDITIONS MIN 500 ns FB forced above the regulation point, LSAT = GND 0.85 mA FB forced above the regulation point, VLSAT > 0.5V 1.0 FB forced above the regulation point 5 µA 40 µA Shutdown Supply Current (VCC) SHDN = GND 7 µA Shutdown Supply Current (VDD) SHDN = GND 5 µA Shutdown Supply Current (V+) SHDN = GND, V+ = 28V, VCC = VDD = 0 or 5V 5 µA 1.980 2.020 V 0.7 VREF V REFERENCE Reference Voltage VREF VCC = 4.5V to 5.5V, IREF = 0 REFIN Voltage Range FAULT DETECTION Overvoltage Trip Threshold With respect to error comparator threshold, OVP/UVP = VCC 10 20 % Output Undervoltage Protection Trip Threshold With respect to error comparator threshold, OVP/UVP = VCC 65 75 % PGOOD Lower Trip Threshold With respect to error comparator threshold, hysteresis = 1% -14 -6 % PGOOD Upper Trip Threshold With respect to error comparator threshold, hysteresis = 1% +6 +14 % Rising edge, PWM disabled below this level hysteresis = 20mV 4.1 4.4 V VCC Undervoltage Lockout Threshold VUVLO(VCC) CURRENT LIMIT Current-Limit Input Range CSP 0 2.7 CSN -0.3 +28.0 V Valley Current-Limit Threshold (Fixed) VLIM(VAL) VCSP - VCSN, ILIM = VCC 35 65 mV Valley Current-Limit Threshold (Adjustable) VLIM(VAL) VCSP - VCSN, VILIM = 2.00V 160 240 mV 6 _______________________________________________________________________________________ Quick-PWM Step-Down Controllers with Inductor Saturation Protection and Dynamic Output Voltages (V+ = 15V, VCC = VDD = SHDN = 5V, SKIP = GND, TA = -40°C to +85°C, unless otherwise noted.) (Note 4) PARAMETER SYMBOL CONDITIONS MIN MAX UNITS 1.20 2.20 V INPUTS AND OUTPUTS Logic Input Threshold SHDN, SKIP, GATE rising edge, hysteresis = 225mV Dual Mode Threshold Voltage MAX1992 FB TON, OVP/UVP, LSAT, FBLANK Four-Level Input Logic Levels High 1.9 2.1 Low 0.05 0.15 High VCC 0.4V Open 3.15 3.85 REF 1.65 2.35 Low V V 0.5 Note 2: When the inductor is in continuous conduction, the output voltage has a DC regulation level higher than the error comparator threshold by 50% of the output ripple. In discontinuous conduction (SKIP = GND, light load), the output voltage has a DC regulation level higher than the trip level by approximately 1.5% due to slope compensation. Note 3: On-time and off-time specifications are measured from 50% point to 50% point at the DH pin with LX = GND, VBST = 5V, and a 250pF capacitor connected from DH to LX. Actual in-circuit times can differ due to MOSFET switching speeds. Note 4: Specifications to -40°C are guaranteed by design, not production tested. Typical Operating Characteristics (MAX1992 Circuit of Figure 1, MAX1993 Circuit of Figure 9, VIN = 12V, VDD = VCC = 5V, SKIP = VCC, TON = open, TA = +25°C, unless otherwise noted.) 2.5V OUTPUT VOLTAGE vs. LOAD CURRENT VIN = 7V VIN = 12V 70 VIN = 20V SKIP = GND SKIP = VCC MAX1992 toc02 2.52 VIN = 20V 2.51 2.50 VIN = 7V 1 LOAD CURRENT (A) 80 VIN = 7V 70 VIN = 12V VIN = 20V 60 2.47 0.1 90 2.48 50 0.01 SKIP = GND SKIP = VCC 2.53 2.49 60 100 EFFICIENCY (%) 80 SKIP = GND SKIP = VCC 2.54 OUTPUT VOLTAGE (V) 90 EFFICIENCY (%) 2.55 MAX1992 toc01 100 EFFICIENCY vs. LOAD CURRENT (VOUT = 1.8V) MAX1992 toc03 EFFICIENCY vs. LOAD CURRENT (VOUT = 2.5V) 10 50 0 1 2 3 LOAD CURRENT (A) 4 5 0.01 0.1 1 10 LOAD CURRENT (A) _______________________________________________________________________________________ 7 MAX1992/MAX1993 ELECTRICAL CHARACTERISTICS (continued) Typical Operating Characteristics (continued) (MAX1992 Circuit of Figure 1, MAX1993 Circuit of Figure 9, VIN = 12V, VDD = VCC = 5V, SKIP = VCC, TON = open, TA = +25°C, unless otherwise noted.) 1.8V OUTPUT VOLTAGE vs. LOAD CURRENT VIN = 20V 1.81 VIN = 7V 150 100 1 2 3 MAX1992 toc06 MAX1992 toc05 200 320 4A LOAD 280 NO LOAD 240 0 5 4 200 0 1 2 3 5 4 0 4 8 12 16 20 24 LOAD CURRENT (A) LOAD CURRENT (A) INPUT VOLTAGE (V) SWITCHING FREQUENCY vs. TEMPERATURE MAXIMUM OUTPUT CURRENT vs. INPUT VOLTAGE MAXIMUM OUTPUT CURRENT vs. TEMPERATURE 280 5.1 MAXIMUM IOUT (A) 4A LOAD 320 5.2 MAXIMUM IOUT (A) 360 5.2 28 MAX1992 toc09 5.5 MAX1992 toc07 400 MAX1992 toc08 0 4.9 4.6 NO LOAD 5.0 4.9 4.3 200 4.8 4.0 -40 -15 10 35 85 60 0 4 8 12 16 20 24 INPUT VOLTAGE (V) NO-LOAD SUPPLY CURRENT vs. INPUT VOLTAGE (FORCED-PWM MODE) NO-LOAD SUPPLY CURRENT vs. INPUT VOLTAGE (SKIP MODE) 7 6 5 IIN 4 SKIP = AGND 1.2 SUPPLY CURRENT (mA) IBIAS 8 1.5 MAX1992 toc10 9 3 2 0.9 0.6 IBIAS 8 12 16 20 INPUT VOLTAGE (V) 24 60 85 2.010 2.006 2.002 1.998 IIN 0 4 35 1.994 SKIP = VCC 0 0 10 REFERENCE LOAD REGULATION 0.3 1 -15 TEMPERATURE (°C) TEMPERATURE (°C) 10 -40 28 MAX1992 toc12 240 REFERENCE VOLTAGE (V) SWITCHING FREQUENCY (kHz) 250 360 50 1.80 8 300 400 SWITCHING FREQUENCY (kHz) 1.83 SKIP = GND SKIP = VCC 350 MAX1992 toc11 OUTPUT VOLTAGE (V) 1.84 400 SWITCHING FREQUENCY (kHz) MAX1992 toc04 SKIP = GND SKIP = VCC 1.82 SWITCHING FREQUENCY vs. INPUT VOLTAGE SWITCHING FREQUENCY vs. LOAD CURRENT 1.85 SUPPLY CURRENT (mA) MAX1992/MAX1993 Quick-PWM Step-Down Controllers with Inductor Saturation Protection and Dynamic Output Voltages 28 1.990 0 4 8 12 16 20 INPUT VOLTAGE (V) 24 28 -20 0 20 40 IREF (μA) _______________________________________________________________________________________ 60 80 100 Quick-PWM Step-Down Controllers with Inductor Saturation Protection and Dynamic Output Voltages (MAX1992 Circuit of Figure 1, MAX1993 Circuit of Figure 9, VIN = 12V, VDD = VCC = 5V, SKIP = VCC, TON = open, TA = +25°C, unless otherwise noted.) ILIM SATURATION FAULT CURRENT vs. ILIM VOLTAGE STARTUP WAVEFORMS (HEAVY LOAD) MAX1992 toc14 MAX1992 toc13 7 6 MAX1992 toc15 5V 5V A 0 A 0 4A 5 IILIM(LSAT) (μA) STARTUP WAVEFORMS (LIGHT LOAD) B 2A 0 0 2V C 3V 2A 4 3 2 0 1 5V B C 0 D D 0 0 0 0 0.4 0.8 1.2 1.6 2.0 VILIM (V) 400μs/div 200μs/div A. SHDN = 0 TO 5V; 5V/div B. INDUCTOR CURRENT: 2A/div C. OUTPUT VOLTAGE (VOUT): 2V/div D. PGOOD: 5V/div, 0.7Ω LOAD A. SHDN = 0 TO 5V; 5V/div B. INDUCTOR CURRENT: 2A/div C. OUTPUT VOLTAGE (VOUT): 2V/div D. PGOOD: 5V/div, 100Ω LOAD SHUTDOWN WAVEFORMS (DISCHARGE MODE ENABLED) SHUTDOWN WAVEFORMS (DISCHARGE MODE DISABLED) LOAD TRANSIENT (FORCED-PWM OPERATION) MAX1992 toc17 MAX1992 toc16 MAX1992 toc18 5V A B A 0 4A A 0 2.6V B 0 B 2.5V 5V C C 0 2.5V 12V 5V 20ms/div A. SHDN = 5V TO 0; 5V/div B. INDUCTOR CURRENT: 2A/div C. DL: 5V/div D. OUTPUT VOLTAGE (VOUT): 2V/div E. PGOOD: 5V/div, 100Ω LOAD, OVP/UVP = OPEN OR G C 0 D D E 2.4V 5A D E 0 1.0ms/div A. SHDN = 5V TO 0; 5V/div B. INDUCTOR CURRENT: 2A/div C. DL: 5V/div D. OUTPUT VOLTAGE (VOUT): 2V/div E. PGOOD: 5V/div, 100Ω LOAD, OVP/UVP = VCC OR REF 0 20μs/div A. LOAD: IOUT = 0.2A TO 4A; 5A/div B. 2.5V OUTPUT: 100mV/div C. INDUCTOR CURRENT: 5A/div D. LX: 10V/div, SKIP = VCC _______________________________________________________________________________________ 9 MAX1992/MAX1993 Typical Operating Characteristics (continued) MAX1992/MAX1993 Quick-PWM Step-Down Controllers with Inductor Saturation Protection and Dynamic Output Voltages Typical Operating Characteristics (continued) (MAX1992 Circuit of Figure 1, MAX1993 Circuit of Figure 9, VIN = 12V, VDD = VCC = 5V, SKIP = VCC, TON = open, TA = +25°C, unless otherwise noted.) LOAD TRANSIENT (PULSE-SKIPPING OPERATION) OUTPUT OVERLOAD WAVEFORMS (UVP DISABLED) MAX1992 toc19 OUTPUT OVERLOAD WAVEFORMS (UVP ENABLED) MAX1992 toc20 MAX1992 toc21 10A 4A 10A A 0 2.6V A 0 2.5V B 0 5V C 0 5A 0 B 2.5V 2.4V 5A 2.5V C 0 5A 0 0 12V 5V B C D 0 5V D D 0 0 A 20μs/div E 0 40μs/div 20μs/div A. LOAD CURRENT (0 TO 250mΩ): 10A/div B. 2.5V OUTPUT: 2V/div C. INDUCTOR CURRENT: 5A/div D. PGOOD: 5V/div, OVP/UVP = OPEN OR GND A. LOAD: IOUT = 0.2A TO 4A; 5A/div B. 2.5V OUTPUT: 100mV/div C. INDUCTOR CURRENT: 5A/div D. LX: 10V/div, SKIP = GND INDUCTOR SATURATION PROTECTION (LSAT DISABLED) A. LOAD CURRENT (0 TO 250mΩ): 10A/div B. 2.5V OUTPUT: 2V/div C. DL: 5V/div D. INDUCTOR CURRENT: 5A/div E. PGOOD: 5V/div, OVP/UVP = VCC OR REF INDUCTOR SATURATION PROTECTION (ΔVILIM = 200mV) MAX1992 toc22 INDUCTOR SATURATION PROTECTION (ΔVILIM = 400mV) MAX1992 toc23 5A MAX1992 toc24 5A 5A A 0 A 0 A 0 2.5V 2.5V B 2.5V B 0.67V C 0.67V C 7.5A 0.67V 7.5A 7.5A A. LOAD CURRENT: IOUT = 0 TO 5A; 5A/div B. 2.5V OUTPUT: 200mV/div C. VILIM: 100mV/div D. INDUCTOR CURRENT: 5A/div; LSAT = AGND; L = 3.3μH, 3.5A 10 D D E 0 0 20μs/div C 5V 0.47V D 0 B 20μs/div A. LOAD CURRENT: IOUT = 0 TO 5A; 5A/div B. 2.5V OUTPUT: 200mV/div C. VILIM: 200mV/div D. INDUCTOR CURRENT: 5A/div, LSAT = REF; L = 3.3μH, 3.5A 20μs/div A. LOAD CURRENT: IOUT = 0 TO 5A; 5A/div B. 2.5V OUTPUT: 1V/div C. PGOOD: 5V/div D. VILIM: 400mV/div E. INDUCTOR CURRENT: 5A/div, LSAT = REF; L = 3.3μH, 3.5A ______________________________________________________________________________________ Quick-PWM Step-Down Controllers with Inductor Saturation Protection and Dynamic Output Voltages (MAX1992 Circuit of Figure 1, MAX1993 Circuit of Figure 9, VIN = 12V, VDD = VCC = 5V, SKIP = VCC, TON = open, TA = +25°C, unless otherwise noted.) MAX1993 DYNAMIC OUTPUT VOLTAGE TRANSITION (CREFIN = 1nF) MAX1993 DYNAMIC OUTPUT VOLTAGE TRANSITION (CREFIN = 100pF) MAX1992 toc25 MAX1992 toc26 5V A 0 1.5V 5V A 0 1.5V B 1.5V C 1.0V B 1.5V C 1.0V D 5V 2.5A D 5V 5A E 0 E 0 -5A -2.5A 100μs/div 40μs/div A. VGATE = 0 TO 5V; 5V/div B. OUTPUT = 1.5V TO 1.0V; 0.5V/div C. VREFIN: 0.5V/div D. PGOOD: 5V/div E. INDUCTOR CURRENT: 2.5A/div 100mA LOAD, SKIP = GND, CIRCUIT OF FIGURE 9 A. VGATE = 0 TO 5V; 5V/div B. OUTPUT = 1.5V TO 1.0V; 0.5V/div C. VREFIN: 0.5V/div D. PGOOD: 5V/div E. INDUCTOR CURRENT: 2.5A/div 100mA LOAD, SKIP = GND, CIRCUIT OF FIGURE 9 Pin Description PIN MAX1992 MAX1993 NAME FUNCTION 1 1 TON On-Time Selection Control Input. This four-level logic input sets the K-factor value used to determine the DH on-time (see the On-Time One-Shot section). Connect to analog ground (AGND or GND), REF, VCC, or leave TON unconnected to select the following nominal switching frequencies: VCC = 200kHz Open = 300kHz REF = 450kHz AGND = 600kHz 2, 7, 8 — N.C. No Connection. Not internally connected. — 2 FBLANK Fault Blanking Control Input. This four-level logic input enables or disables fault blanking, and sets the minimum forced-PWM operation time (tFBLANK). When fault blanking is enabled, PGOOD, OVP protection, and UVP protection are blanked for the selected time period after a transition is detected on GATE. Additionally, the controller enters forced-PWM mode for the duration of tFBLANK anytime GATE changes states. Connect FBLANK as follows: VCC = 140µs (min) tFBLANK, fault blanking enabled Open = 90µs (min) tFBLANK, fault blanking enabled REF = 40µs (min) tFBLANK, fault blanking enabled AGND = 90µs (min) tFBLANK, fault blanking disabled ______________________________________________________________________________________ 11 MAX1992/MAX1993 Typical Operating Characteristics (continued) Quick-PWM Step-Down Controllers with Inductor Saturation Protection and Dynamic Output Voltages MAX1992/MAX1993 Pin Description (continued) PIN MAX1992 3 4 5 3 4 5 NAME LSAT FUNCTION Inductor Saturation Control Input. This four-level logic input sets the inductor current saturation limit as a multiple of the valley current-limit threshold set by ILIM, or disables the function if not required. Connect LSAT to the following pins to set the saturation current limit: VCC = 2 × ILIM(VAL) Open = 1.75 × ILIM(VAL) REF = 1.5 × ILIM(VAL) AGND = disable LSAT protection See the Inductor Saturation Limit and Setting the Current Limit sections. PGOOD Open-Drain Power-Good Output. PGOOD is low when the output voltage is more than 10% (typ) above or below the normal regulation point, during soft-start, and in shutdown. After the soft-start circuit has terminated, PGOOD becomes high impedance if the output is in regulation. For the MAX1993, PGOOD is blanked—forced high-impedance state—when FBLANK is enabled and the controller detects a transition on GATE. ILIM Valley Current-Limit Threshold Adjustment. The valley current-limit threshold defaults to 50mV if ILIM is tied to VCC. In adjustable mode, the valley current-limit threshold across CSP and CSN is precisely 1/10th the voltage seen at ILIM over a 250mV to 2.5V range. The logic threshold for switchover to the 50mV default value is approximately VCC - 1V. When the inductor saturation protection threshold is exceeded, ILIM sinks 6µA. See the Current-Limit Protection (ILIM) section. 6 6 REF 2.0V Reference Voltage Output. Bypass REF to analog ground with a 0.1µF or greater ceramic capacitor. The reference can source up to 50µA for external loads. Loading REF degrades output voltage accuracy according to the REF load regulation error. The reference is disabled when the MAX1992/MAX1993 is shut down. — 7 REFIN External Reference Input. REFIN sets the feedback regulation voltage (VFB = VREFIN) of the MAX1993. — 8 OD Open-Drain Output. Controlled by GATE. FB Feedback Input. MAX1992: Connect to VCC for a +1.8V fixed output or to AGND for a +2.5V fixed output. For an adjustable output (0.7V to 5.5V), connect FB to a resistive divider from the output voltage. The FB regulation level is +0.7V. MAX1993: The FB regulation level is set by the voltage at REFIN. OUT Output Voltage Sense. Connect directly to the positive terminal of the output capacitors as shown in the standard application circuits (Figures 1 and 9). OUT senses the output voltage to determine the on-time for the high-side switching MOSFET. For the MAX1992, OUT also serves as the feedback input when using the preset internal output voltages as shown in Figure 7. When discharge mode is enabled by OVP/UVP, the output capacitor is discharged through an internal 10Ω resistor connected between OUT and ground. CSP Positive Current-Sense Input. Connect to the positive terminal of the current-sense element. Figure 10 and Table 7 describe several current-sensing options. The PWM controller does not begin a cycle unless the current sensed is less than the valley current-limit threshold programmed at ILIM. 9 10 11 12 MAX1993 9 10 11 ______________________________________________________________________________________ Quick-PWM Step-Down Controllers with Inductor Saturation Protection and Dynamic Output Voltages PIN MAX1992 MAX1993 NAME FUNCTION 12 12 CSN Negative Current-Sense Input. Connect to the negative terminal of the current-sense element. Figure 10 and Table 7 describe several current-sensing options. The PWM controller does not begin a cycle unless the current sensed is less than the valley current-limit threshold programmed at ILIM. 13 13 SKIP Pulse-Skipping Control Input. Connect SKIP to VCC for low-noise, forced-PWM mode or connect SKIP to analog ground (AGND or GND) to enable pulse-skipping operation. 14 14 V+ Battery Voltage-Sense Connection. The controller only uses V+ to set the on-time oneshot timing. The DH on-time is inversely proportional to input voltage over a range of 2V to 28V. 15 15 DH High-Side Gate-Driver Output. DH swings from LX to BST. 16 16 LX Inductor Connection. Connect LX to the switched side of the inductor. LX serves as the lower supply rail for the DH high-side gate driver. 17 17 BST Boost Flying Capacitor Connection. Connect to an external capacitor and diode as shown in Figure 6. An optional resistor in series with BST allows the DH pullup current to be adjusted. 18 18 DL Low-Side Gate-Driver Output. DL swings from PGND to VDD (MAX1992) or GND to VDD (MAX1993). 19 19 VDD Supply Voltage Input for the DL Gate Driver. Connect to the system supply voltage (+4.5V to +5.5V). Bypass VDD to PGND with a 1µF or greater ceramic capacitor. 20 — PGND Power Ground. Ground connection for the DL low-side gate driver. Analog and Power Ground. AGND and PGND connect together internally. Connect backside pad to GND. — 20 GND 21 — AGND Analog Ground. Connect backside pad to AGND. — 21 GATE Buffered N-Channel MOSFET Gate Input. A logic low on GATE turns off the internal MOSFET so OD appears as a high impedance. A logic high on GATE turns on the internal MOSFET, pulling OD to ground. 22 22 VCC Analog Supply Input. Connect to the system supply voltage (+4.5V to +5.5V) through a series 20Ω resistor. Bypass VCC to analog ground with a 1µF or greater ceramic capacitor. ______________________________________________________________________________________ 13 MAX1992/MAX1993 Pin Description (continued) Quick-PWM Step-Down Controllers with Inductor Saturation Protection and Dynamic Output Voltages MAX1992/MAX1993 Pin Description (continued) PIN MAX1992 MAX1993 23 23 24 24 NAME FUNCTION SHDN Shutdown Control Input. Connect to VCC for normal operation. Connect to analog ground to put the controller into its 1µA shutdown state. When discharge mode is enabled by OVP/UVP, the output is discharged through a 10Ω resistor between OUT and ground, and DL is forced high after VOUT drops below 0.3V. When discharge mode is disabled by OVP/UVP, OUT remains a high-impedance input and DL is forced low, so LX also appears as a high-impedance input. A rising edge on SHDN clears the fault-protection latch. OVP/UVP Overvoltage/Undervoltage Protection and Discharge Mode Control Input. This fourlevel logic input selects between various output fault-protection options (Table 6) by selectively enabling OVP protection and UVP protection. When enabled, the OVP limit defaults at 116% of the nominal output voltage, and the UVP limit defaults at 70% of the nominal output voltage. Discharge mode is enabled when UVP protection is also enabled. Connect OVP/UVP to the following pins for the desired function: VCC = enable OVP and discharge mode, enable UVP Open = enable OVP and discharge mode, disable UVP REF = disable OVP and discharge mode, enable UVP AGND = disable OVP and discharge mode, and UVP See the Fault Protection and Shutdown and Output Discharge sections. Table 1. Component Selection for Standard Applications VOUT = 2.5V AT 5A (FIGURE 1) VOUT = 1.8V AT 5A VOUT = 1.0V / 1.5V AT 4A (FIGURE 9) VIN = 7V to 24V, TON = OPEN (300kHz) VIN = 7V to 24V, TON = OPEN (300kHz) VIN = 4.5V to 5.5V, TON = GND (600kHz) MAX1992 FB = AGND FB = VCC Not recommended MAX1993 Adjustable FB, REFIN = REF FB = OUT, VREFIN = 1.8V FB = OUT, VREFIN = 1.0V / 1.5V CIN, input capacitor 10µF, 25V Taiyo Yuden TMK432BJ106KM 10µF, 25V Taiyo Yuden TMK432BJ106KM 100µF, 10V Sanyo POSCAP 10TPA100M COUT, output capacitor 220µF, 4V, 15mΩ Sanyo POSCAP 4TPE220MF 220µF, 4V, 15mΩ Sanyo POSCAP 4TPE220MF 220µF, 6V, 12mΩ Sanyo POSCAP 6TPD220M NH high-side MOSFET Fairchild Semiconductor 1/2 FDS6982A Fairchild Semiconductor 1/2 FDS6982A Fairchild Semiconductor 1/2 FDS6982S NL low-side MOSFET Fairchild Semiconductor 1/2 FDS6982A Fairchild Semiconductor 1/2 FDS6982A Fairchild Semiconductor 1/2 FDS6982S DL Schottky rectifier (optional) Nihon EP10QS03L 1A, 30V, 0.45Vf Nihon EP10QS03L 1A, 30V, 0.45Vf Nihon EP10QS03L 1A, 30V, 0.45Vf L1 inductor 4.3µH Sumida CDEP105(L) 3.2µH Sumida CDEP105(L) 1.4µH Sumida CDEP105(L) RSENSE 15mΩ ±1% 0.5W resistor IRC LR2010-01-R015F or Dale WSL-2010-R015F 15mΩ ±1% 0.5W resistor IRC LR2010-01-R015F or Dale WSL-2010-R015F 15mΩ ±1% 0.5W resistor IRC LR2010-01-R015F or Dale WSL-2010-R015F COMPONENT 14 ______________________________________________________________________________________ Quick-PWM Step-Down Controllers with Inductor Saturation Protection and Dynamic Output Voltages MAX1992/MAX1993 Table 2. Component Suppliers SUPPLIER PHONE WEBSITE Central Semiconductor 631-435-1110 (USA) www.centralsemi.com Coilcraft 800-322-2645 (USA) www.coilcraft.com Coiltronics 561-752-5000 (USA) www.coiltronics.com Fairchild Semiconductor 888-522-5372 (USA) www.fairchildsemi.com International Rectifier 310-322-3331 (USA) www.irf.com Kemet 408-986-0424 (USA) www.kemet.com 714-373-7366 (USA) www.panasonic.com 65-231-3226 (Singapore) 408-749-9714 (USA) www.secc.co.jp Panasonic Sanyo Siliconix (Vishay) 203-268-6261 (USA) www.vishay.com Sumida 408-982-9660 (USA) www.sumida.com 03-3667-3408 (Japan) 408-573-4150 (USA) www.t-yuden.com 847-803-6100 (USA) 81-3-5201-7241 (Japan) www.component.tdk.com 858-675-8013 (USA) www.tokoam.com Taiyo Yuden TDK TOKO C1 1μF R1 20Ω R2 100kΩ VDD VCC LSAT POWER GOOD DBST CMPSH-3 +5V BIAS SUPPLY C2 1μF V+ PGOOD BST SHDN DH CIN 10μF INPUT (VIN)* 7V TO 20V NH ON OFF FLOAT (300kHz) RSENSE 15mΩ OUTPUT (VOUT) 2.5V LX TON SKIP MAX1992 CREF 0.22μF NL DL DL COUT 220μF PGND REF R3 100kΩ CILIM 470pF L1 4.3μH CBST 0.1μF AGND CSP ILIM R4 49.9kΩ CSN OUT FB OVP/UVP POWER GROUND ANALOG GROUND *LOWER INPUT VOLTAGES REQUIRE ADDITIONAL INPUT CAPACITANCE. SEE TABLE 1 FOR COMPONENT SPECIFICATIONS. BOLD LINES INDICATE HIGH CURRENT TRACES. Figure 1. MAX1992 Standard Application Circuit ______________________________________________________________________________________ 15 MAX1992/MAX1993 Quick-PWM Step-Down Controllers with Inductor Saturation Protection and Dynamic Output Voltages Detailed Description The MAX1992/MAX1993 buck controllers are ideal for low-voltage power supplies for notebook computers. Maxim’s proprietary Quick-PWM pulse-width modulator in the MAX1992/MAX1993 is designed for handling fast load steps while maintaining a relatively constant operating frequency and inductor operating point over a wide range of input voltages. The Quick-PWM architecture circumvents the poor load-transient timing problems of fixed-frequency current-mode PWMs while avoiding the problems caused by widely varying switching frequencies in conventional constant-on-time and constant-off-time PWM schemes. See Table 1 for component selections and Table 2 for a list of component suppliers. +5V Bias Supply (VCC and VDD) The MAX1992/MAX1993 require an external 5V bias supply in addition to the battery. Typically, this 5V bias supply is the notebook’s 95%-efficient 5V system supply. Keeping the bias supply external to the IC improves efficiency and eliminates the cost associated with the 5V linear regulator that would otherwise be needed to supply the PWM circuit and gate drivers. If stand-alone capability is needed, the 5V supply can be generated with an external linear regulator such as the MAX1615. The 5V bias supply must provide VCC (PWM controller) and VDD (gate-drive power), so the maximum current drawn is: IBIAS = ICC + fSW (QG(LOW) + QG(HIGH)) = 2mA to 20mA (typ) where ICC is 550µA (typ), fSW is the switching frequency, and Q G(LOW) and Q G(HIGH) are the MOSFET data sheet’s total gate-charge specification limits at VGS = 5V. The V+ battery input and 5V bias inputs (VCC and VDD) can be connected together if the input source is a fixed 4.5V to 5.5V supply. If the 5V bias supply is powered up prior to the battery supply, the enable signal (SHDN going from low to high) must be delayed until the battery voltage is present in order to ensure startup. Free-Running Constant-On-Time PWM Controller with Input Feed Forward The Quick-PWM control architecture is a pseudofixedfrequency, constant on-time, current-mode regulator with voltage feed forward (Figure 2). This architecture relies on the output filter capacitor’s ESR to act as a current-sense resistor, so the output ripple voltage provides the PWM ramp signal. The control algorithm is simple: the high-side switch on-time is determined solely by a one-shot whose pulse width is inversely proportional to input voltage and directly proportional to output voltage. Another one-shot sets a minimum offtime (400ns typ). The on-time one-shot is triggered if the error comparator is low, the low-side switch current is below the valley current-limit threshold, and the minimum off-time one-shot has timed out. On-Time One-Shot (TON) The heart of the PWM core is the one-shot that sets the high-side switch on-time. This fast, low-jitter, adjustable one-shot includes circuitry that varies the on-time in response to battery and output voltage. The high-side switch on-time is inversely proportional to the battery voltage as measured by the V+ input and is proportional to the output voltage: On-time = K (VOUT + 0.075V) / VIN Table 3. Approximate K-Factor Errors TON SETTING (kHz) TYPICAL K-FACTOR (µs) K-FACTOR ERROR (%) MINIMUM VIN AT VOUT = 2.5V (h = 1.5) (V) TYPICAL APPLICATION COMMENTS 200 (TON = VCC) 5.0 ±10 3.14 4-cell Li+ notebook Use for absolute best efficiency 300 (TON = open) 3.3 ±10 3.47 4-cell Li+ notebook Considered mainstream by current standards 450 (TON = REF) 2.2 ±12.5 4.13 3-cell Li+ notebook Useful in 3-cell systems for lighter loads than the CPU core or where size is key 600 (TON = GND) 1.7 ±12.5 5.61 +5V input 16 Good operating point for compound buck designs or desktop circuits ______________________________________________________________________________________ Quick-PWM Step-Down Controllers with Inductor Saturation Protection and Dynamic Output Voltages TON tOFF(MIN) ON-TIME COMPUTE Q OUT TRIG MAX1992 MAX1993 1-SHOT S tON Q TRIG MAX1992/MAX1993 V+ 1-SHOT BST DH Q LX R ILIM ERROR AMP R Q S VDD 1.14 x INTREF S DL Q ENABLE OVP OVP/UVP R FAULT LATCH QUAD LEVEL DECODE PGND SATURATION LIMIT CSP CSN QUAD LEVEL DECODE BLANK LSAT VCC - 1.0V 20ms TIMER ENABLE UVP R 9R SKIP CSP 0.7 x INTREF ILIM POR CSP CURRENT LIMIT ZERO CROSSING CSN CSN 0.5V REF INTREF *OD *GATE VCC 0.9 x INTREF 1.1 x INTREF 13R MAX1993 ONLY 2.0V REF AGND 0.7V MAX1992 vs. MAX1993 INTERNAL OPTION PGOOD 7R *REFIN *FBLANK FB MAX1992 FB DECODE (FIGURE 7) BLANK FBLANK DECODE AND TIMER *MAX1993 ONLY. IN THE MAX1993, AGND AND PGND ARE INTERNALLY CONNECTED AND CALLED GND. OUT DISCHARGE LOGIC SHDN Figure 2. MAX1992/MAX1993 Functional Diagram ______________________________________________________________________________________ 17 MAX1992/MAX1993 Quick-PWM Step-Down Controllers with Inductor Saturation Protection and Dynamic Output Voltages where K (switching period) is set by the TON pin-strap connection (Table 3), and 0.075V is an approximation to accommodate the expected drop across the low-side MOSFET switch. This algorithm results in a nearly constant switching frequency despite the lack of a fixed-frequency clock generator. The benefits of a constant switching frequency are twofold: 1) the frequency can be selected to avoid noise-sensitive regions such as the 455kHz IF band; 2) the inductor ripple-current operating point remains relatively constant, resulting in easy design methodology and predictable output voltage ripple. The on-time one-shot has good accuracy at the operating points specified in the Electrical Characteristics (approximately ±12.5% at 600kHz and 450kHz and ±10% at 200kHz and 300kHz). On-times at operating points far removed from the conditions specified in the Electrical Characteristics can vary over a wider range. For example, the 600kHz setting typically runs approximately 10% slower with inputs much greater than 5V due to the very short on-times required. The constant on-time translates only roughly to a constant switching frequency. The on-times guaranteed in the Electrical Characteristics are influenced by resistive losses and by switching delays in the high-side MOSFET. Resistive losses—including the inductor, both MOSFETs, output capacitor ESR, and PC board copper losses in the output and ground—tend to raise the switching frequency as the load increases. The dead-time effect increases the effective on-time, reducing the switching frequency as one or both dead times are added to the effective ontime. It occurs only in PWM mode (SKIP = VCC) and during dynamic output voltage transitions when the inductor current reverses at light or negative load currents. With reversed inductor current, the inductor’s EMF causes LX to go high earlier than normal, extending the on-time by a period equal to the DH-rising dead time. For loads above the critical conduction point, where the dead-time effect is no longer a factor, the actual switching frequency is: fSW = VOUT + VDROP1 t ON ( VIN + VDROP2 ) where VDROP1 is the sum of the parasitic voltage drops in the inductor discharge path, including synchronous rectifier, inductor, and PC board resistances; VDROP2 is the sum of the resistances in the charging path, including the high-side switch, inductor, and PC board resistances; and t ON is the on-time calculated by the MAX1992/MAX1993. 18 Automatic Pulse-Skipping Mode (SKIP = GND) In skip mode (SKIP = GND), an inherent automatic switchover to PFM takes place at light loads (Figure 3). This switchover is affected by a comparator that truncates the low-side switch on-time at the inductor current’s zero crossing. The zero-crossing comparator differentially senses the inductor current across the current-sense resistor (CSP to CSN). Once VCSP - VCSN drops below 5% of the current-limit threshold (2.5mV for the default 50mV current-limit threshold), the comparator forces DL low (Figure 2). This mechanism causes the threshold between pulse-skipping PFM and nonskipping PWM operation to coincide with the boundary between continuous and discontinuous inductor-current operation (also known as the critical conduction point). The load-current level at which PFM/PWM crossover occurs, ILOAD(SKIP), is equal to one-half the peak-to-peak ripple current, which is a function of the inductor value (Figure 3). This threshold is relatively constant, with only a minor dependence on battery voltage: K ⎞ ⎛ V − VOUT ⎞ ⎛V ILOAD(SKIP) ≈ ⎜ OUT ⎟ ⎜ IN ⎟ ⎝ 2L ⎠ ⎝ VIN ⎠ where K is the on-time scale factor (Table 3). For example, in the standard application circuit (K = 3.3µs, VOUT = 2.5V, VIN = 12V, and L = 4.3µH), the pulse-skipping switchover occurs at: ⎛ 2.5V × 3.3μs ⎞ ⎛ 12V − 2.5V ⎞ ⎟ = 0.76A ⎜ ⎟⎜ ⎠ 12V ⎝ 2 × 4.3μH ⎠ ⎝ The crossover point occurs at an even lower value if a swinging (soft-saturation) inductor is used. The switching waveforms can appear noisy and asynchronous when light loading causes pulse-skipping operation, but this is a normal operating condition that results in high light-load efficiency. Trade-offs in PFM noise vs. light-load efficiency are made by varying the inductor value. Generally, low inductor values produce a broader efficiency vs. load curve, while higher values result in higher full-load efficiency (assuming that the coil resistance remains fixed) and less output voltage ripple. Penalties for using higher inductor values include larger physical size and degraded load-transient response (especially at low input voltage levels). ______________________________________________________________________________________ Quick-PWM Step-Down Controllers with Inductor Saturation Protection and Dynamic Output Voltages Forced-PWM mode is most useful for reducing audiofrequency noise, improving load-transient response, and providing sink-current capability for dynamic output voltage adjustment. The MAX1993 uses forcedPWM operation during all dynamic output voltage transitions (GATE transition detected) in order to ensure fast, accurate transitions. Because forced-PWM operation disables the zero-crossing comparator, the inductor current reverses under light loads, quickly discharging the output capacitors. FBLANK determines how long the MAX1993 maintains forced-PWM operation—140µs (FBLANK = VCC), 90µs (FBLANK = open or AGND), or 40µs (FBLANK = REF). VIN - VOUT L IPEAK INDUCTOR CURRENT Forced-PWM Mode (SKIP = VCC) The low-noise forced-PWM mode (SKIP = VCC) disables the zero-crossing comparator, which controls the low-side switch on-time. This forces the low-side gatedrive waveform to constantly be the complement of the high-side gate-drive waveform, so the inductor current reverses at light loads while DH maintains a duty factor of VOUT/VIN. Forced-PWM mode keeps the switching frequency fairly constant. However, forced-PWM operation comes at a cost: the no-load 5V bias current remains between 2mA and 20mA, depending on the external MOSFETs and switching frequency. ΔI = Δt MAX1992/MAX1993 DC output accuracy specifications refer to the threshold of the error comparator. When the inductor is in continuous conduction, the MAX1992/MAX1993 regulate the valley of the output ripple, so the actual DC output voltage is higher than the trip level by 50% of the output ripple voltage. In discontinuous conduction (SKIP = GND and IOUT < ILOAD(SKIP)), the output voltage has a DC regulation level higher than the errorcomparator threshold by approximately 1.5% because of slope compensation. ILOAD = IPEAK/2 0 ON-TIME TIME Figure 3. Pulse-Skipping/Discontinuous Crossover Point MAX1992 MAX1993 CREF REF RA TO VALLEY CURRENT-LIMIT COMPARATOR (FIGURE 2) CILIM ILIM 6μA RB FROM LSAT COMPARATOR AND LOGIC (FIGURE 2) Figure 4. Adjustable Current-Limit Threshold Current-Limit Protection (ILIM) IPEAK ILOAD INDUCTOR CURRENT Valley Current Limit The current-limit circuit employs a unique “valley” current-sensing algorithm that uses a current-sense resistor between CSP and CSN as the current-sensing element (Figure 10). If the magnitude of the currentsense signal is above the valley current-limit threshold, the PWM controller is not allowed to initiate a new cycle (Figure 5). The actual peak current is greater than the valley current-limit threshold by an amount equal to the inductor ripple current. Therefore, the exact currentlimit characteristic and maximum load capability are a function of the current-sense resistance, inductor value, and battery voltage. When combined with the undervoltage protection circuit, this current-limit method is effective in almost every circumstance. ILIMIT ( LIR2 ) ILIM(VAL) = ILOAD(MAX) 1- 0 TIME Figure 5. “Valley” Current-Limit Threshold Point ______________________________________________________________________________________ 19 MAX1992/MAX1993 Quick-PWM Step-Down Controllers with Inductor Saturation Protection and Dynamic Output Voltages In forced-PWM mode, the MAX1992/MAX1993 also implement a negative current limit to prevent excessive reverse inductor currents when VOUT is sinking current. The negative current-limit threshold is set to approximately 120% of the positive current limit and tracks the positive current limit when ILIM is adjusted. The current-limit threshold is adjusted with an external resistor-divider at ILIM. A 2µA to 20µA divider current is recommended for accuracy and noise immunity. The current-limit threshold adjustment range is from 25mV to 200mV. In the adjustable mode, the current-limit threshold voltage is precisely 1/10th the voltage seen at ILIM. The threshold defaults to 50mV when ILIM is connected to VCC. The logic threshold for switchover to the 50mV default value is approximately VCC - 1V. Carefully observe the PC board layout guidelines to ensure that noise and DC errors do not corrupt the differential current-sense signals seen by CSP and CSN. Place the IC close to the sense resistor with short, direct traces, making a Kelvin-sense connection to the current-sense resistor. Inductor Saturation Limit The LSAT connection selects an upper current-sense limit as the inductor saturation threshold or disables the inductor saturation protection feature altogether (LSAT = GND). When enabled, the inductor saturation threshold is set as a multiple of the positive valley current-limit threshold (Table 4) and tracks the valley current limit when ILIM is adjusted. The inductor saturation threshold should be selected to give sufficient headroom above the peak inductor current so switching noise does not accidentally trip the saturation protection. Selecting too high a threshold can cause an inductor saturation to go undetected. For an inductor with a low LIR (the ratio of the inductor ripple current to the designed maximum load current) of approximately 20%, the lowest saturation threshold of 1.5 x ILIM(VAL) (LSAT = REF) may be acceptable. When using an inductor with a higher LIR, increase the inductor saturation threshold accordingly. When inductor saturation is enabled, the MAX1992/ MAX1993 continuously monitor the inductor current through the voltage across the current-sense resistor. When the inductor saturation threshold is exceeded, the MAX1992/MAX1993 immediately turn off the high-side gate driver and enable a 6µA discharge current on ILIM (Figure 4) at the beginning of the next DH on-time. 20 This reduces the voltage on ILIM by ΔVILIM where: ⎛ R × RB ⎞ ΔVILIM = −⎜ A ⎟IILIM (LSAT) ⎝ RA + RB ⎠ where IILIM(LSAT) is 6µA ILIM saturation fault sink current (see the Electrical Characteristics table). When using the default 50mV valley current-limit threshold (ILIM = VCC), the ILIM saturation fault sink current does not lower the current-limit threshold (see Figure 2). If the inductor current remains below the saturation threshold during the next cycle, the ILIM discharge current is disabled, and the ILIM voltage returns to its original set point. The inductor should not remain in saturation once the controller reduces the valley current limit. However, if the inductor remains in saturation, the output voltage may drop low enough to trip the undervoltage fault protection (UVP enabled), causing the MAX1992/MAX1993 to shut down and latch off. Adding a capacitor from ILIM to GND slows the ILIM voltage change by the time constant τ = (RA//RB) x CILIM. A suitable time constant is between 5 to 10 switching cycles. If the inductor saturation occurs only during a short load transient, the time constant allows the power supply to recover before the output voltage drops below the output undervoltage threshold. Set ΔVILIM to be at least 30% (LIR) of the ILIM set voltage. Calculate RA and RB using the equations below: RA = ⎛ ΔV ⎞ ILIM ⎜ ⎟ IILIM(LSAT) ⎝ VILIM(SET) ⎠ VREF ⎛ ΔV ⎞ ILIM with ⎜ ⎟ set at 30% ⎝ VILIM(SET) ⎠ RB = RA ⎛ V ⎞ REF − 1⎟ ⎜ ⎝ VILIM(SET) ⎠ Inductor saturation works best using a current-sense resistor in series with the inductor. A low-side currentsense resistor configuration can sense the saturation Table 4. LSAT Configuration Table LSAT INDUCTOR SATURATION THRESHOLD VCC 2.00 × ILIM(VAL) Open 1.75 × ILIM(VAL) REF 1.50 × ILIM(VAL) GND Disabled ______________________________________________________________________________________ Quick-PWM Step-Down Controllers with Inductor Saturation Protection and Dynamic Output Voltages MOSFET Gate Drivers (DH, DL) The DH and DL drivers are optimized for driving moderately sized high-side and larger low-side power MOSFETs. This is consistent with the low duty factor seen in notebook applications, where a large VIN - VOUT differential exists. An adaptive dead-time circuit monitors the DL output and prevents the high-side MOSFET from turning on until DL is off. A similar adaptive dead-time circuit monitors the DH output, preventing the low-side MOSFET from turning on until DH is off. There must be a low-resistance, low-inductance path from the DL and DH drivers to the MOSFET gates in order for the adaptive dead-time circuits to work properly; otherwise, the sense circuitry in the MAX1992/MAX1993 interpret the MOSFET gates as “off” while charge actually remains. Use very short, wide traces (50 mils to 100 mils wide if the MOSFET is 1in from the driver). The internal pulldown transistor that drives DL low is robust, with a 0.6Ω (typ) on-resistance. This helps prevent DL from being pulled up because of capacitive coupling from the drain to the gate of the low-side MOSFETs when the inductor node (LX) quickly switches from ground to VIN. Applications with high-input voltages and long inductive driver traces can require additional gate-to-source capacitance to ensure that fast-rising LX edges do not pull up the low-side MOSFETs gate, causing shootthrough currents. The capacitive coupling between LX and DL created by the MOSFET’s gate-to-drain capacitance (CRSS), gate-to-source capacitance (CISS - CRSS), and additional board parasitics should not exceed the following minimum threshold. ⎛C ⎞ VGS( TH) < VIN ⎜ RSS ⎟ ⎝ CISS ⎠ Lot-to-lot variation of the threshold voltage can cause problems in marginal designs. Alternatively, adding a resistor of less than 10Ω in series with BST can remedy the problem by increasing the turn-on time of the highside MOSFET without degrading the turn-off time (Figure 6). MAX1992/MAX1993 current only at the start of the off-cycle. See Setting the Current Limit section for various current-sense configurations (Figure 10) and LSAT recommendations. CBYP MAX1992 MAX1993 VDD BST (RBST)* DBST INPUT (VIN) CBST DH NH L LX VDD DL NL (CNL)* PGND (RBST)* OPTIONAL—THE RESISTOR LOWERS EMI BY DECREASING THE SWITCHING NODE RISE TIME. (CNL)* OPTIONAL—THE CAPACITOR REDUCES LX TO DL CAPACITIVE COUPLING THAT CAN CAUSE SHOOT-THROUGH CURRENTS. Figure 6. Optional Gate Driver Circuitry POR, UVLO, and Soft-Start Power-on reset (POR) occurs when VCC rises above approximately 2V, resetting the fault latch and soft-start counter, powering up the reference, and preparing the PWM for operation. Until VCC reaches 4.25V (typ), VCC undervoltage lockout (UVLO) circuitry inhibits switching. The controller inhibits switching by pulling DH low and holding DL low when OVP and shutdown discharge are disabled or forcing DL high when OVP and shutdown discharge are enabled (Table 6). When VCC rises above 4.25V, the controller activates the PWM controller and initializes soft-start. Soft-start allows a gradual increase of the internal currentlimit level during startup to reduce the input surge currents. The MAX1992/MAX1993 divide the soft-start period into five phases. During the first phase, the controller limits the current limit to only 20% of the full current limit. If the output does not reach regulation within 425µs, softstart enters the second phase, and the current limit is increased by another 20%. This process repeats until the maximum current limit is reached after 1.7ms or when the output reaches the nominal regulation voltage, whichever occurs first (see soft-start waveforms in the Typical Operating Characteristics). Adding a capacitor in parallel with the external ILIM resistors creates a continuously adjustable analog soft-start function. ______________________________________________________________________________________ 21 MAX1992/MAX1993 Quick-PWM Step-Down Controllers with Inductor Saturation Protection and Dynamic Output Voltages Power-Good Output (PGOOD) Shutdown and Output Discharge PGOOD is the open-drain output for a window comparator that continuously monitors the output. PGOOD is actively held low in shutdown and during soft-start. After the digital soft-start terminates, PGOOD becomes high impedance as long as the output voltage is within ±10% of the nominal regulation voltage set by FB. When the output voltage drops 10% below or rises 10% above the nominal regulation voltage, the MAX1992/ MAX1993 pull PGOOD low. Any fault condition forces PGOOD low until the fault latch is cleared by toggling SHDN or cycling VCC power below 1V. For logic level output voltages, connect an external pullup resistor between PGOOD and VCC. A 100kΩ resistor works well in most applications. Note that the PGOOD window detector is completely independent of the overvoltage and undervoltage protection fault detectors. When output discharge is enabled (OVP/UVP = VCC or open) and SHDN is pulled low, or the output undervoltage fault latch is set (OVP/UVP = V CC or REF), the MAX1992/MAX1993 discharge the output through an internal 10Ω switch to ground. While the output is discharging, DL is forced low and the PWM controller is disabled, but the reference remains active to provide an accurate threshold. Once the output voltage drops below 0.3V, the MAX1992/MAX1993 shut down the reference and pull DL high, effectively clamping the output and LX switching node to ground. When output discharge is disabled (OVP/UVP = REF or GND), the controller does not actively discharge the output, and the DL driver remains low. Under these conditions, the output discharge rate is determined by the load current and output capacitance. The controller detects and latches the discharge mode state set by OVP/UVP on startup. Fault Blanking (MAX1993 FBLANK) The MAX1993 automatically enters forced-PWM operation during all dynamic output voltage transitions (GATE transition detected) in order to ensure fast, accurate transitions. FBLANK determines how long the MAX1993 maintains forced-PWM operation (Table 5)—at least 140µs (FBLANK = V CC ), 90µs (FBLANK = open or GND), or 40µs (FBLANK = REF). When fault blanking is enabled (FBLANK = VCC, open, or REF), the MAX1993 also disables the overvoltage and undervoltage fault protection and forces PGOOD to a high-impedance state during the transition period selected by FBLANK (Table 5). This prevents fault protection from latching off the controller and the PGOOD signal from going low when the output voltage change (ΔVOUT) cannot occur as fast as the REFIN voltage change (ΔVREFIN). Table 5. FBLANK Configuration Table FBLANK FAULT BLANKING MINIMUM FORCEDPWM DURATION (µs) VCC Enabled 140 22 Open Enabled 90 REF Enabled 40 GND Disabled 90 Fault Protection The MAX1992/MAX1993 provide over/undervoltage fault protection. Drive OVP/UVP to enable and disable fault protection as shown in Table 6. Once activated, the controller continuously monitors the output for undervoltage and overvoltage fault conditions. Overvoltage Protection (OVP) When the output voltage rises above 116% of the nominal regulation voltage and OVP is enabled (OVP/UVP = VCC or open), the OVP circuit sets the fault latch, shuts down the PWM controller, and immediately pulls DH low and forces DL high. This turns on the synchronous rectifier MOSFET with 100% duty, rapidly discharging the output capacitor and clamping the output to ground. Note that immediately latching DL high can cause the output voltage to go slightly negative due to energy stored in the output LC at the instant the OVP occurs. If the load cannot tolerate a negative voltage, place a power Schottky diode across the output to act as a reversepolarity clamp. If the condition that caused the overvoltage persists (such as a shorted high-side MOSFET), the battery fuse blows. OVP is ignored when transitions are detected on GATE (MAX1993 only, FBLANK enabled). Toggle SHDN or cycle VCC power below 1V to clear the fault latch and restart the controller. OVP is disabled when OVP/UVP is connected to REF or GND (Table 6). ______________________________________________________________________________________ Quick-PWM Step-Down Controllers with Inductor Saturation Protection and Dynamic Output Voltages OVP/UVP SHDN DISCHARGE* OVP PROTECTION THERMAL PROTECTION Yes. Enabled. DL forced high when Discharge sequence activated; DL forced high when shut down. shut down. Enabled. DH pulled low and DL forced high. Enabled. Discharge sequence activated; DL forced high when shut down. Open Yes. DL forced high when shut down. Disabled. Enabled. DH pulled low and DL forced high. Enabled. Discharge sequence activated; DL forced high when shut down. REF No. DL forced low when shut down. Enabled. Discharge sequence activated; DL forced high when shut down. Disabled. Enabled. Discharge sequence activated; DL forced high when shut down. GND No. DL forced low when shut down. Disabled. Disabled. Enabled. Discharge sequence activated; DL forced high when shut down. VCC UVP PROTECTION *Discharge-mode state latched on power-up. Undervoltage Protection (UVP) When the output voltage drops below 70%, the nominal regulation voltage and the UVP are enabled (OVP/UVP = VCC or REF), and the controller sets the fault latch and begins the discharge mode (see the Shutdown and Output Discharge section). When the output voltage drops to 0.3V, the synchronous rectifiers turn on, clamping the outputs to GND. UVP is ignored for at least 10ms (min) after startup (SHDN rising edge) and when transitions are detected on GATE (MAX1993 only, FBLANK enabled). Toggle SHDN or cycle VCC power below 1V to clear the fault latch and restart the controller. UVP is disabled when OVP/UVP is left open or connected to GND (Table 6). Thermal Fault Protection The MAX1992/MAX1993 feature a thermal fault protection circuit. When the junction temperature rises above +160°C, a thermal sensor activates the fault latch, pulls PGOOD low, and shuts down using discharge mode regardless of the OVP/UVP setting. Toggle SHDN or cycle VCC power below 1V to reactivate the controller after the junction temperature cools by 15°C. Output Voltage Preset Output Voltages (MAX1992 Only) The MAX1992’s Dual Mode operation allows the selection of common voltages without requiring external components (Figure 7). Connect FB to AGND for a fixed 2.5V output, to VCC for a fixed 1.8V output, or connect FB directly to OUT for a fixed 0.7V output. Setting VOUT with a Resistive Voltage-Divider at FB The output voltage can be adjusted from 0.7V to 5.5V using a resistive voltage-divider (Figure 8). The MAX1992 regulates FB to a fixed reference voltage (0.7V). Alternatively, the MAX1993 regulates FB to the voltage set at REFIN, making the MAX1993 ideal for memory applications in which the termination supply must track the supply voltage. The adjusted output voltage is: ⎛ R ⎞ VOUT = VFB ⎜1 + C ⎟ ⎝ RD ⎠ where VFB is 0.7V for the MAX1992 and VFB = VREFIN for the MAX1993. MAX1992 OUT TO ERROR AMPLIFIER FB 1.8V (FIXED) REF (2.0V) 2.5V (FIXED) 0.1 x REF (0.2V) Figure 7. Dual-Mode Feedback Decoder (MAX1992) ______________________________________________________________________________________ 23 MAX1992/MAX1993 Table 6. Fault Protection and Shutdown Setting Truth Table MAX1992/MAX1993 Quick-PWM Step-Down Controllers with Inductor Saturation Protection and Dynamic Output Voltages L RSENSE LX MAX1992 MAX1993 COUT DL NL PGND AGND CSP CSN OUT RC FB RD Figure 8. Setting VOUT with a Resistive Voltage-Divider Dynamic Output Voltages (MAX1993 Only) The MAX1993 regulates FB to the voltage set at REFIN. By changing the voltage at REFIN, the MAX1993 can be used in applications that require dynamic output voltage changes between two set points. Figure 9 shows a dynamically adjustable resistive voltagedivider network at REFIN. Using the GATE signal and open-drain output (OD), a resistor can be switched in and out of the REFIN resistor-divider, changing the voltage at REFIN. A logic high on GATE turns on the internal N-channel MOSFET, forcing OD to a lowimpedance state. A logic low on GATE disables the Nchannel MOSFET, so OD is high impedance. The two output voltages (FB = OUT) are determined by the following equations: ⎛ R6 ⎞ VOUT(LOW) = VREF ⎜ ⎟ ⎝ R5 + R6 ⎠ ⎡ (R6 + R7) ⎤ VOUT(HIGH) = VREF ⎢ ⎥ ⎢⎣ R5 + (R6 + R7) ⎥⎦ 24 The MAX1993 automatically enters forced-PWM operation on the rising and falling edges of GATE and remains in forced-PWM mode for a minimum time selected by FBLANK (Table 5). Forced-PWM operation is required to ensure fast, accurate negative voltage transitions when REFIN is lowered. Because forcedPWM operation disables the zero-crossing comparator, the inductor current can reverse under light loads, quickly discharging the output capacitors. If fault blanking is enabled, the MAX1993 also disables the overvoltage and undervoltage fault protection and forces PGOOD to a high-impedance state for the period selected by FBLANK (Table 5). For a step voltage change at REFIN, the rate of change of the output voltage is limited by the inductor current ramp, the total output capacitance, the current limit, and the load during the transition. The inductor current ramp is limited by the voltage across the inductor and the inductance. The total output capacitance determines how much current is needed to change the output voltage. Additional load current slows the output voltage change during a positive REFIN voltage change, and speeds the output voltage change during a negative REFIN voltage change. Increasing the current-limit setting speeds a positive output voltage change. Adding a capacitor across REFIN and GND filters noise and controls the rate-of-change of the REFIN voltage during dynamic transitions. With the additional capacitance, the REFIN voltage slews between the two set points with a time constant determined by the equivalent parallel resistance seen by the slew capacitor (CREFIN). Referring to Figure 9, the time constant for a positive REFIN voltage transition is: ⎡ R5 × (R6 + R7) ⎤ τ POS = ⎢ ⎥CREFIN ⎢⎣ R5 + (R6 + R7) ⎥⎦ and the time constant for a negative REFIN voltage transition is: ⎛ R5 × R6 ⎞ τ NEG = ⎜ ⎟C ⎝ R5 + R6 ⎠ REFIN ______________________________________________________________________________________ Quick-PWM Step-Down Controllers with Inductor Saturation Protection and Dynamic Output Voltages R1 20Ω +5V BIAS SUPPLY C2 1μF VDD VCC R2 100kΩ LSAT OVP/UVP POWER GOOD DBST CMPSH-3 V+ PGOOD BST SHDN DH CIN 10μF INPUT (VIN)* 4.5V TO 5.5V NH ON OFF OUTPUT VOUT(HIGH) = 1.5V VOUT(LOW) = 1.0V RSENSE 15mΩ LX REF R3 100kΩ CILIM 470pF L1 1.4μH CBST 0.1μF CREF 0.22μF MAX1992/MAX1993 C1 1μF MAX1993 ILIM R4 49.9kΩ NL DL COUT 220μF DL GND CSP CSN CREFIN 470pF R5 75kΩ OUT REFIN R6 75kΩ FB SKIP OD TON R7 150kΩ FBLANK GATE GND (600kHz) FLOAT (90μs MIN, FAULT BLANKING) VOUT (LOW) = VREF (R5R6+ R6) VOUT (HIGH) = VREF [R5 +R6(R6+ R7+ R7)] VOUT (LOW) VOUT (HIGH) POWER GROUND ANALOG GROUND *LOWER INPUT VOLTAGES REQUIRE ADDITIONAL INPUT CAPACITANCE. SEE TABLE 1 FOR COMPONENT SPECIFICATIONS. BOLD LINES INDICATE HIGH CURRENT TRACES. Figure 9. MAX1993 Standard Application Circuit ______________________________________________________________________________________ 25 MAX1992/MAX1993 Quick-PWM Step-Down Controllers with Inductor Saturation Protection and Dynamic Output Voltages Design Procedure Firmly establish the input voltage range and maximum load current before choosing a switching frequency and inductor operating point (ripple-current ratio). The primary design trade-off lies in choosing a good switching frequency and inductor operating point, and the following four factors dictate the rest of the design: • Input Voltage Range. The maximum value (VIN(MAX)) must accommodate the worst-case, high AC-adapter voltage. The minimum value (VIN(MIN)) must account for the lowest battery voltage after drops due to connectors, fuses, and battery selector switches. If there is a choice, lower input voltages result in better efficiency. • Maximum Load Current. There are two values to consider. The peak load current (ILOAD(MAX)) determines the instantaneous component stresses and filtering requirements and thus drives output capacitor selection, inductor saturation rating, and the design of the current-limit circuit. The continuous load current (ILOAD) determines the thermal stresses and thus drives the selection of input capacitors, MOSFETs, and other critical heat-contributing components. • Switching Frequency. This choice determines the basic trade-off between size and efficiency. The optimal frequency is largely a function of maximum input voltage, due to MOSFET switching losses proportional to frequency and VIN2. The optimum frequency is also a moving target, due to rapid improvements in MOSFET technology that are making higher frequencies more practical. • Inductor Operating Point. This choice provides trade-offs: size vs. efficiency and transient response vs. output ripple. Low inductor values provide better transient response and smaller physical size but also result in lower efficiency and higher output ripple due to increased ripple currents. The minimum practical inductor value is one that causes the circuit to operate at the edge of critical conduction (where the inductor current just touches zero with every cycle at maximum load). Inductor values lower than this grant no further size-reduction benefit. The optimum operating point is usually found between 20% and 50% ripple current. When pulse skipping (SKIP low and light loads), the inductor value also determines the load-current value at which PFM/PWM switchover occurs. 26 Inductor Selection The switching frequency and inductor operating point determine the inductor value as follows: L= VOUT ( VIN − VOUT ) VINfSW ILOAD(MAX)LIR For example: I LOAD(MAX) = 5A, V IN = 12V, V OUT = 2.5V, fSW = 300kHz, 30% ripple current or LIR = 0.3 L= 2.5V(12V − 2.5) 12V × 300kHz × 5A × 0.3 = 4.40μH Find a low-loss inductor having the lowest possible DC resistance that fits in the allotted dimensions. Ferrite cores are often the best choice, although powdered iron is inexpensive and can work well at 200kHz. The core must be large enough not to saturate at the peak inductor current (IPEAK): ⎛ LIR ⎞ IPEAK = ILOAD (MAX) ⎜1 + ⎟ ⎝ 2 ⎠ Most inductor manufacturers provide inductors in standard values, such as 1.0µH, 1.5µH, 2.2µH, 3.3µH, etc. Also look for nonstandard values, which can provide a better compromise in LIR across the input voltage range. If using a swinging inductor (where the no-load inductance decreases linearly with increasing current), evaluate the LIR with properly scaled inductance values. Transient Response The inductor ripple current also affects transientresponse performance, especially at low VIN - VOUT differentials. Low inductor values allow the inductor current to slew faster, replenishing charge removed from the output filter capacitors by a sudden load step. The output sag is also a function of the maximum duty factor, which can be calculated from the on-time and minimum off-time: ( L ΔILOAD (MAX) VSAG = ) 2 ⎡⎛ VOUTK ⎞ ⎢⎜ ⎢⎣⎝ ⎤ + t OFF(MIN) ⎥ VIN ⎟⎠ ⎥⎦ ⎡⎛ ( VIN − VOUT )K ⎞ ⎤ 2COUT VOUT ⎢⎜ ⎟ + t OFF(MIN) ⎥ VIN ⎢⎝ ⎥ ⎠ ⎣ ⎦ where t OFF(MIN) is the minimum off-time (see the Electrical Characteristics) and K is from Table 3. ______________________________________________________________________________________ Quick-PWM Step-Down Controllers with Inductor Saturation Protection and Dynamic Output Voltages CURRENT-SENSE ACCURACY INDUCTOR SATURATION PROTECTION CURRENT-SENSE POWER LOSS (EFFICIENCY) A) Output Current-Sense Resistor High Allowed (highest accuracy) RSENSE x IOUT2 B) Low-Side Current-Sense Resistor High Not allowed (LSAT = GND) C) Low-Side MOSFET On-Resistance Low Not allowed (LSAT = GND) No additional loss D) Equivalent Inductor DC Resistance Low Allowed No additional loss METHOD The overshoot during a full-load to no-load transient due to stored inductor energy can be calculated as: VSOAR (ΔILOAD(MAX) ) ≈ 2 L 2COUT VOUT Setting the Current Limit The minimum current-limit threshold must be great enough to support the maximum load current when the current limit is at the minimum tolerance value. The valley of the inductor current occurs at ILOAD(MAX) minus half the ripple current; therefore: ⎛ ILOAD (MAX)LIR ⎞ ILIM (VAL) > ILOAD (MAX) − ⎜ ⎟ 2 ⎝ ⎠ where ILIM(VAL) equals the minimum valley current-limit threshold voltage divided by the current-sense resistance (RSENSE). For the 50mV default setting, the minimum valley current-limit threshold is 40mV. Connect ILIM to VCC for a default 50mV valley currentlimit threshold. In adjustable mode, the valley currentlimit threshold is precisely 1/10th the voltage seen at ILIM. For an adjustable threshold, connect a resistive divider from REF to analog ground (GND) with ILIM connected to the center tap. The external 250mV to 2V adjustment range corresponds to a 25mV to 200mV valley current-limit threshold. When adjusting the current limit, use 1% tolerance resistors and a divider current of approximately 10µA to prevent significant inaccuracy in the valley current-limit tolerance. The current-sense method (Figure 10) and magnitude determine the achievable current-limit accuracy and power loss (Table 7). Typically, higher current-sense voltage limits provide tighter accuracy but also dissipate more power. ⎛ VOUT ⎞ 2 ⎜1 − V ⎟ × RSENSE × IOUT ⎝ ⎠ IN Most applications employ a valley current-sense voltage (VLIM(VAL)) of 50mV to 100mV, so the sense resistor can be determined by: RSENSE = VLIM(VAL) / ILIM(VAL) For the best current-sense accuracy and overcurrent protection, use a 1% tolerance current-sense resistor between the inductor and output as shown in Figure 10a. This configuration constantly monitors the inductor current, allowing accurate valley current-limiting and inductor saturation protection. For low output voltage applications that require higher efficiency, the current-sense resistor can be connected between the source of the low-side MOSFET (NL) and power ground (Figure 10b) with CSN connected to the drain of NL and CSP connected to power ground. In this configuration, the additional current-sense resistance only dissipates power when NL is conducting current. Inductor saturation protection must be disabled with this configuration (LSAT = GND) because the inductor current is only properly sensed when the low-side MOSFET is turned on. For high-power applications that do not require highaccuracy current sensing or inductor saturation protection, the MAX1992/MAX1993 can use the low-side MOSFET’s on-resistance as the current-sense element (RSENSE = RDS(ON)) by connecting CSN to the drain of NL and CSP to the source of NL (Figure 10c). Use the worst-case maximum value for R DS(ON) from the MOSFET data sheet, and add some margin for the rise in RDS(ON) with temperature. A good general rule is to allow 0.5% additional resistance for each °C of temperature rise. Inductor saturation protection must be disabled with this configuration (LSAT = GND) because the inductor current is properly sensed only when the low-side MOSFET is turned on. ______________________________________________________________________________________ 27 MAX1992/MAX1993 Table 7. Current-Sense Configurations MAX1992/MAX1993 Quick-PWM Step-Down Controllers with Inductor Saturation Protection and Dynamic Output Voltages VIN DH CIN RSENSE L VOUT LX MAX1992 MAX1993 COUT DL GND CONNECT TO PREFERRED LSAT SETTING CSP LSAT CSN A) OUTPUT SERIES RESISTOR SENSING VIN CIN DH L VOUT LX MAX1992 MAX1993 COUT DL CSN RSENSE DISABLE LSAT CSP GND LSAT B) LOW-SIDE SERIES RESISTOR SENSING VIN DH CIN L VOUT LX COUT CSN MAX1992 MAX1993 DISABLE LSAT DL VIN CSP LSAT DH GND CIN INDUCTOR RL L VOUT LX C) LOW-SIDE MOSFET SENSING MAX1992 MAX1993 DL GND CONNECT TO PREFERRED LSAT SETTING COUT REQ CEQ CSP LSAT CSN D) LOSSLESS INDUCTOR SENSING RBIAS = REQ Figure 10. Current-Sense Configurations 28 ______________________________________________________________________________________ Quick-PWM Step-Down Controllers with Inductor Saturation Protection and Dynamic Output Voltages L = CEQ × REQ RL where RL is the inductor’s series DC resistance. In this configuration, the current-sense resistance is equivalent to the inductor’s DC resistance (RSENSE = RL). Use the worst-case inductance and RL values provided by the inductor manufacturer, adding some margin for the inductance drop over temperature and load. In all cases, ensure an acceptable valley current-limit threshold voltage and inductor saturation configurations despite inaccuracies in sense resistance values. When using low-capacity filter capacitors, such as ceramic capacitors, size is usually determined by the capacity needed to prevent V SAG and V SOAR from causing problems during load transients. Generally, once enough capacitance is added to meet the overshoot requirement, undershoot at the rising load edge is no longer a problem (see the VSAG and VSOAR equations in the Transient Response section). However, lowcapacity filter capacitors typically have high-ESR zeros that can affect the overall stability (see the Output Capacitor Stability Considerations section). Output Capacitor Stability Considerations For Quick-PWM controllers, stability is determined by the value of the ESR zero relative to the switching frequency. The boundary of instability is given by the following equation: f fESR ≤ SW π Output Capacitor Selection The output filter capacitor must have low enough equivalent series resistance (ESR) to meet output ripple and load-transient requirements, yet have high enough ESR to satisfy stability requirements. For processor core voltage converters and other applications in which the output is subject to violent load transients, the output capacitor’s size depends on how much ESR is needed to prevent the output from dipping too low under a load transient. Ignoring the sag due to finite capacitance: RESR ≤ VSTEP ΔILOAD(MAX) In applications without large and fast load transients, the output capacitor’s size often depends on how much ESR is needed to maintain an acceptable level of output voltage ripple. The output ripple voltage of a stepdown controller equals the total inductor ripple current multiplied by the output capacitor’s ESR. Therefore, the maximum ESR required to meet ripple specifications is: RESR ≤ VRIPPLE ΔILOAD(MAX)LIR The actual capacitance value required relates to the physical size needed to achieve low ESR, as well as to the chemistry of the capacitor technology. Thus, the capacitor is usually selected by ESR and voltage rating rather than by capacitance value (this is true of tantalums, OSCONs, polymers, and other electrolytics). where fESR = 1 2πRESR COUT For a typical 300kHz application, the ESR zero frequency must be well below 95kHz, preferably below 50kHz. Tantalum and OSCON capacitors in widespread use at the time of publication have typical ESR zero frequencies of 25kHz. In the design example used for inductor selection, the ESR needed to support 25mVP-P ripple is 25mV/1.5A = 16.7mΩ. One 220µF/4V Sanyo polymer (TPE) capacitor provides 15mΩ (max) ESR. This results in a zero at 48kHz, well within the bounds of stability. Do not put high-value ceramic capacitors directly across the feedback sense point without taking precautions to ensure stability. Large ceramic capacitors can have a high-ESR zero frequency and cause erratic, unstable operation. However, it is easy to add enough series resistance by placing the capacitors a couple of inches downstream from the feedback sense point, which should be as close as possible to the inductor. Unstable operation manifests itself in two related but distinctly different ways: double pulsing and fast-feedback loop instability. Double pulsing occurs due to noise on the output or because the ESR is so low that there is not enough voltage ramp in the output voltage signal. This “fools” the error comparator into triggering a new cycle immediately after the 400ns minimum offtime period has expired. ______________________________________________________________________________________ 29 MAX1992/MAX1993 Alternatively, high-power applications that require inductor saturation protection can constantly detect the inductor current by connecting a series RC circuit across the inductor (Figure 10d) with an equivalent time constant: MAX1992/MAX1993 Quick-PWM Step-Down Controllers with Inductor Saturation Protection and Dynamic Output Voltages Double pulsing is more annoying than harmful, resulting in nothing worse than increased output ripple. However, it can indicate the possible presence of loop instability due to insufficient ESR. Loop instability can result in oscillations at the output after line or load steps. Such perturbations are usually damped but can cause the output voltage to rise above or fall below the tolerance limits. The easiest method for checking stability is to apply a very fast zero-to-max load transient and carefully observe the output voltage ripple envelope for overshoot and ringing. It can help to simultaneously monitor the inductor current with an AC current probe. Do not allow more than one cycle of ringing after the initial step-response under/overshoot. Input Capacitor Selection The input capacitor must meet the ripple current requirement (IRMS) imposed by the switching currents: ⎛ V ⎞ OUT ( VIN − VOUT ) ⎟ IRMS = ILOAD ⎜ ⎜ ⎟ VIN ⎝ ⎠ For most applications, nontantalum chemistries (ceramic, aluminum, or OSCON) are preferred due to their resistance to power-up surge currents typical of systems with a mechanical switch or connector in series with the input. If the MAX1992/MAX1993 are operated as the second stage of a two-stage power conversion system, tantalum input capacitors are acceptable. In either configuration, choose a capacitor that has less than 10°C temperature rise at the RMS input current for optimal reliability and lifetime. Power MOSFET Selection Most of the following MOSFET guidelines focus on the challenge of obtaining high load-current capability when using high-voltage (>20V) AC adapters. Low-current applications usually require less attention. The high-side MOSFET (NH) must be able to dissipate the resistive losses plus the switching losses at both VIN(MIN) and VIN(MAX). Ideally, the losses at VIN(MIN) should be roughly equal to the losses at VIN(MAX), with lower losses in between. If the losses at VIN(MIN) are significantly higher, consider increasing the size of NH. Conversely, if the losses at VIN(MAX) are significantly higher, consider reducing the size of NH. If VIN does not vary over a wide range, maximum efficiency is achieved by selecting a high-side MOSFET (N H) that has conduction losses equal to the switching losses. 30 Choose a low-side MOSFET (NL) that has the lowest possible on-resistance (RDS(ON)), comes in a moderatesized package (i.e., 8-pin SO, DPAK, or D2PAK), and is reasonably priced. Ensure that the MAX1992/MAX1993 DL gate driver can supply sufficient current to support the gate charge and the current injected into the parasitic drain-to-gate capacitor caused by the high-side MOSFET turning on; otherwise, cross-conduction problems can occur. Switching losses are not an issue for the low-side MOSFET since it is a zero-voltage switched device when used in the step-down topology. Power MOSFET Dissipation Worst-case conduction losses occur at the duty factor extremes. For the high-side MOSFET (NH), the worstcase power dissipation due to resistance occurs at minimum input voltage: ⎛V ⎞ 2 PD(NH Re sistive) = ⎜ OUT ⎟ (ILOAD ) RDS(ON) ⎝ VIN ⎠ Generally, use a small high-side MOSFET to reduce switching losses at high-input voltages. However, the RDS(ON) required to stay within package power-dissipation limits often limits how small the MOSFET can be. The optimum efficiency occurs when the switching losses equal the conduction (RDS(ON)) losses. Highside switching losses do not become an issue until the input is greater than approximately 15V. Calculating the power dissipation in high-side MOSFETs (NH) due to switching losses is difficult, since it must allow for difficult-to-quantify factors that influence the turn-on and turn-off times. These factors include the internal gate resistance, gate charge, threshold voltage, source inductance, and PC board layout characteristics. The following switching loss calculation provides only a very rough estimate and is no substitute for breadboard evaluation, preferably including verification using a thermocouple mounted on NH: PD(NH (VIN(MAX) ) Switching) = 2 CRSSfSW ILOAD IGATE where CRSS is the reverse transfer capacitance of NH, and IGATE is the peak gate-drive source/sink current (1A typ). Switching losses in the high-side MOSFET can become a heat problem when maximum AC adapter voltages are applied, due to the squared term in the switchingloss equation (C x VIN2 x fSW). ______________________________________________________________________________________ Quick-PWM Step-Down Controllers with Inductor Saturation Protection and Dynamic Output Voltages ⎡ ⎛V ⎞⎤ 2 PD(NL Re sistive) = ⎢1 − ⎜ OUT ⎟ ⎥(ILOAD ) RDS(ON) V ⎢⎣ ⎝ IN ⎠ ⎥⎦ The absolute worst case for MOSFET power dissipation occurs under heavy overload conditions that are greater than ILOAD(MAX) but are not high enough to exceed the current limit and cause the fault latch to trip. To protect against this possibility, “overdesign” the circuit to tolerate: ⎛ ILOAD(MAX)LIR ⎞ ILOAD = IVALLEY(MAX) + ⎜ ⎟ 2 ⎝ ⎠ where I VALLEY(MAX) is the maximum valley current allowed by the current-limit circuit, including threshold tolerance and sense-resistance variation. The MOSFETs must have a relatively large heatsink to handle the overload power dissipation. Choose a Schottky diode (DL) with a forward voltage drop low enough to prevent the low-side MOSFET’s body diode from turning on during the dead time. As a general rule, select a diode with a DC current rating equal to 1/3 the load current. This diode is optional and can be removed if efficiency is not critical. Applications Information Dropout Performance The output voltage adjustable range for continuous-conduction operation is restricted by the nonadjustable minimum off-time one-shot. For best dropout performance, use the slower (200kHz) on-time setting. When working with low input voltages, the duty-factor limit must be calculated using worst-case values for on- and off-times. Manufacturing tolerances and internal propagation delays introduce an error to the TON K-factor. This error is greater at higher frequencies (Table 3). Also, keep in mind that transient response performance of buck regulators operated too close to dropout is poor, and bulk output capacitance must often be added (see the VSAG equation in the Design Procedure section). The absolute point of dropout is when the inductor current ramps down during the minimum off-time (ΔIDOWN) as much as it ramps up during the on-time (ΔIUP). The ratio h = ΔIUP/ΔIDOWN indicates the controller’s ability to slew the inductor current higher in response to increased load, and must always be greater than 1. As h approaches 1, the absolute minimum dropout point, the inductor current cannot increase as much during each switching cycle, and V SAG greatly increases, unless additional output capacitance is used. A reasonable minimum value for h is 1.5, but adjusting this up or down allows trade-offs between VSAG, output capacitance, and minimum operating voltage. For a given value of h, the minimum operating voltage can be calculated as: ⎡ ⎤ ⎢ ⎥ ⎢ VOUT + VDROP1 ⎥ VIN(MIN) = ⎢ ⎥ + VDROP2 − VDROP1 ⎢ ⎛ h × t OFF(MIN) ⎞ ⎥ ⎟⎥ ⎢1 − ⎜ K ⎠⎦ ⎣ ⎝ where VDROP1 and VDROP2 are the parasitic voltage drops in the discharge and charge paths (see the OnTime One-Shot (TON) section), tOFF(MIN) is from the Electrical Characteristics, and K is taken from Table 3. The absolute minimum input voltage is calculated with h = 1. If the calculated VIN(MIN) is greater than the required minimum input voltage, then operating frequency must be reduced or output capacitance added to obtain an acceptable VSAG. If operation near dropout is anticipated, calculate VSAG to be sure of adequate transient response. A dropout design example follows: VOUT = 2.5V fSW = 300kHz K = 3.3µs, worst-case KMIN = 3.0µs tOFF(MIN) = 500ns VDROP1 = VDROP2 = 100mV h = 1.5 ⎡ ⎤ ⎢ ⎥ 2.5V + 0.1V ⎥ ⎢ VIN(MIN) = ⎢ + 0.1V − 0.1V = 3.47V ⎛ ⎞⎥ ⎢ 1 − ⎜ 1.5 × 500ns ⎟ ⎥ ⎢⎣ ⎝ 3.0μs ⎠ ⎥⎦ ______________________________________________________________________________________ 31 MAX1992/MAX1993 If the high-side MOSFET chosen for adequate RDS(ON) at low battery voltages becomes extraordinarily hot when subjected to VIN(MAX), consider choosing another MOSFET with lower parasitic capacitance. For the low-side MOSFET (NL) the worst-case power dissipation always occurs at maximum battery voltage: MAX1992/MAX1993 Quick-PWM Step-Down Controllers with Inductor Saturation Protection and Dynamic Output Voltages REF R4 R1 REFIN B R3 C1 R2 MAX1993 A GND 1kΩ 1000pF GATE 1kΩ 1000pF Figure 11. Multiple Output Voltage Settings Calculating again with h = 1 and the typical K-factor value (K = 3.3µs) gives the absolute limit of dropout: ⎡ ⎤ ⎢ ⎥ 2.5V + 0.1V ⎥ ⎢ VIN(MIN) = ⎢ + 0.1V − 0.1V = 3.06V ⎛ ⎞⎥ ⎢ 1 − ⎜ 1.5 × 500ns ⎟ ⎥ ⎢⎣ ⎝ 3.3μs ⎠ ⎥⎦ Therefore, VIN must be greater than 3.06V, even with very large output capacitance, and a practical input voltage with reasonable output capacitance would be 3.47V. Multiple Output Voltage Settings (MAX1993 Only) While the MAX1993 is optimized to work with applications that require two dynamic output voltages, it can produce three or more output voltages if required by using discrete logic or a DAC. Figure 11 shows an application circuit providing four voltage levels using discrete logic. Switching resistors in and out of the resistor network changes the voltage at REFIN. An edge detection circuit is added to generate a 1µs pulse on GATE to trigger the fault-blanking and forced-PWM operation. When using PWM mode (SKIP = V CC ), the edge detection circuit is only required if fault blanking is enabled. Otherwise, leave OD unconnected. 32 Active Bus Termination (MAX1993 Only) Active bus termination power supplies generate a voltage rail that tracks a set reference. They are required to source and sink current. DDR memory architecture requires active bus termination. In DDR memory architecture, the termination voltage is set at exactly half the memory supply voltage. Configure the MAX1993 to generate the termination voltage using a resistordivider at REFIN. In such an application, the MAX1993 must be kept in PWM mode (SKIP = VCC) in order for it to source and sink current. Figure 12 shows the MAX1993 configured as a DDR termination regulator. Connect GATE and FBLANK to GND when unused. Voltage Positioning In applications where fast-load transients occur, the output voltage changes instantly by ESR COUT x ΔILOAD. Voltage positioning allows the use of fewer output capacitors for such applications, and maximizes the output voltage AC and DC tolerance window in tight tolerance applications. Figure 13 shows the connection of OUT and FB in a voltage-positioned circuit. In nonvoltage-positioned circuits, the MAX1992/MAX1993 regulate at the output capacitor. In voltage-positioned circuits, the MAX1992/ MAX1993 regulate on the inductor side of the currentsense resistor. VOUT is reduced to: VOUT(VPS) = VOUT(NO LOAD) - RSENSEILOAD ______________________________________________________________________________________ Quick-PWM Step-Down Controllers with Inductor Saturation Protection and Dynamic Output Voltages VCC VIN SKIP DH CIN L 1000pF REFIN 1000pF RSENSE V VTT = DDQ 2 LX 10kΩ COUT DL MAX1993 GND 10kΩ CSP OD CSN GATE OUT FBLANK FB VDDQ = DDR MEMORY SUPPLY VOLTAGE VTT = TERMINATION SUPPLY VOLTAGE Figure 12. Active Bus Termination PC Board Layout Guidelines Layout Procedure Careful PC board layout is critical to achieve low switching losses and clean, stable operation. The switching power stage requires particular attention (Figure 15). If possible, mount all of the power components on the topside of the board, with their ground terminals flush against one another. Follow these guidelines for good PC board layout: • Keep the high-current paths short, especially at the ground terminals. This practice is essential for stable, jitter-free operation. • Keep the power traces and load connections short. This practice is essential for high efficiency. Using thick copper PC boards (2oz vs. 1oz) can enhance full-load efficiency by 1% or more. Correctly routing PC board traces is a difficult task that must be approached in terms of fractions of centimeters, where a single milliohm of excess trace resistance causes a measurable efficiency penalty. • Minimize current-sensing errors by connecting CSP and CSN directly across the current-sense resistor (RSENSE). • When trade-offs in trace lengths must be made, it is preferable to allow the inductor-charging path to be made longer than the discharge path. For example, it is better to allow some extra distance between the input capacitors and the high-side MOSFET than to allow distance between the inductor and the lowside MOSFET or between the inductor and the output filter capacitor. • Route high-speed switching nodes (BST, LX, DH, and DL) away from sensitive analog areas (REF, FB, CSP, and CSN). 1) Place the power components first, with ground terminals adjacent (N L source, C IN , C OUT , and D L anode). If possible, make all these connections on the top layer with wide, copper-filled areas. 2) Mount the controller IC adjacent to the low-side MOSFET, preferably on the backside opposite NL and NH in order to keep LX, GND, DH, and the DL gate-drive lines short and wide. The DL and DH gate traces must be short and wide (50 mils to 100 mils wide if the MOSFET is 1in from the controller IC) to keep the driver impedance low and for proper adaptive dead-time sensing. 3) Group the gate-drive components (BST diode and capacitor, VDD bypass capacitor) together near the controller IC. 4) Make the DC-DC controller ground connections as shown in Figures 1 and 9. This diagram can be viewed as having two separate ground planes: power ground, where all the high-power components go; and an analog ground plane for sensitive analog components. The analog ground plane and power ground plane must meet only at a single point directly at the IC. 5) Connect the output power planes directly to the output filter capacitor positive and negative terminals with multiple vias. Place the entire DC-to-DC converter circuit as close to the load as is practical. ______________________________________________________________________________________ 33 MAX1992/MAX1993 VDDQ MAX1992/MAX1993 Quick-PWM Step-Down Controllers with Inductor Saturation Protection and Dynamic Output Voltages R1 +5V BIAS SUPPLY C2 VDD VCC DBST C1 V+ INPUT (VIN) CIN BST NH DH CBST MAX1992 L1 RSENSE LX NL COUT DL DL VOLTAGE-POSITIONED OUTPUT (VOUT(VPS)) PGND AGND CSP OUT CSN FB VOUT(VPS) = VOUT(NO LOAD) - RSENSEIOUT Figure 13. Voltage-Positioning Output CAPACITIVE SOAR (dV/dt = IOUT/COUT) VOLTAGE POSITIONING THE OUTPUT ESR VOLTAGE STEP (ISTEP x RESR) A B A. CONVENTIONAL CONVERTER B. VOLTAGE-POSITIONED OUTPUT VOUT CAPACITIVE SAG (dV/dt = IOUT/COUT) RECOVERY ILOAD Figure 14. Voltage-Positioning Transient Response 34 ______________________________________________________________________________________ Quick-PWM Step-Down Controllers with Inductor Saturation Protection and Dynamic Output Voltages MAX1992/MAX1993 KELVIN SENSE VIAS UNDER THE SENSE RESISTOR (SEE EVALUATION KIT) INDUCTOR VIA TO POWER GROUND VIA TO ANALOG GROUND COUT CONNECT GND AND PGND TO THE CONTROLLER AT ONE POINT ONLY, AS SHOWN COUT CIN OUTPUT INPUT GROUND CONNECT THE EXPOSED PAD TO ANALOG GND MAX1992 Figure 15. PC Board Layout LX DH V+ SKIP 14 13 BST 17 15 DL 18 TOP VIEW 16 Pin Configurations (continued) VDD 19 12 CSN GND 20 11 CSP GATE 21 VCC 22 4 5 6 ILIM REF REFIN PGOOD 7 3 OD 24 LSAT 23 2 FB 8 1 9 TON OVP/UVP 10 OUT MAX1993 FBLANK SHDN Chip Information TRANSISTOR COUNT: 2616 PROCESS: BiCMOS THIN QFN 4mm x 4mm A "+" SIGN WILL REPLACE THE FIRST PIN INDICATOR ON LEAD-FREE PACKAGES. ______________________________________________________________________________________ 35 Package Information (The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to www.maxim-ic.com/packages.) 24L QFN THIN.EPS MAX1992/MAX1993 Quick-PWM Step-Down Controllers with Inductor Saturation Protection and Dynamic Output Voltages PACKAGE OUTLINE, 12, 16, 20, 24, 28L THIN QFN, 4x4x0.8mm 21-0139 E 1 2 PACKAGE OUTLINE, 12, 16, 20, 24, 28L THIN QFN, 4x4x0.8mm 21-0139 E 2 2 Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. 36 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 © 2005 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products, Inc.