INTEGRATED CIRCUITS DATA SHEET SAA7167 YUV-to-RGB Digital-to-Analog Converter (DAC) Preliminary specification Supersedes data of 1995 Jun 13 File under Integrated Circuits, IC22 1995 Nov 03 Philips Semiconductors Preliminary specification YUV-to-RGB Digital-to-Analog Converter (DAC) SAA7167 FEATURES • On-chip mixing of digital video data and analog RGB signals • Supports video input format of YUV 4 : 2 : 2, 4 : 1 : 1, 2 : 1 : 1 andRGB 5 : 6 : 5 • Video input rate up to 50 MHz voltage output amplifier, capable of converting digital video data to analog RGB video, and then mixing video and external analog RGB inputs. • Allows for both binary and two’s complement video input data • Triple 8-bit DACs for video output The video data path contains a data re-formatter, YUV-to-RGB colour space matrix as well as triple DACs for video data processing. An analog mixer performs multiplexing between DAC outputs of the video path and external analog RGB inputs. • Built-in voltage output amplifier • Provide keying control with external key and internal 8-bit, 2 × 8-bit and 3 × 8-bit pixel colour key • Programmable via the I2C-bus • 5 V CMOS device; LQFP48 package. The final analog outputs are buffered with built-in voltage output amplifiers to provide the direct driving capability for a 150 Ω load. Figure 1 shows the overall block diagram. GENERAL DESCRIPTION The operation of SAA7167 is controlled via the I2C-bus. The SAA7167 is a mixed-mode designed IC containing a video data path, keying control block, analog mixer, and a QUICK REFERENCE DATA SYMBOL PARAMETER MIN. MAX. UNIT VDDD digital supply voltage 4.75 5.25 VDDA analog supply voltage 4.75 5.25 V Tamb operating ambient temperature 0 70 °C V ORDERING INFORMATION TYPE NUMBER SAA7167 1995 Nov 03 PACKAGE NAME LQFP48 DESCRIPTION plastic low profile quad flat package; 48 leads; body 7 × 7 × 1.4 mm 2 VERSION SOT313-2 Philips Semiconductors Preliminary specification YUV-to-RGB Digital-to-Analog Converter (DAC) SAA7167 BLOCK DIAGRAM Cref(h) handbook, full pagewidth Bin Gin Rin 36 29 31 33 MIXER Rout OPAMP 32 YUV7 to YUV0 UV7 to UV0 HREF 38 to 45 46 to 48, 1 to 5 REFORMATTER YUV TO RGB MATRIX 8-BIT DAC (3×) MUX MIXER 30 MIXER 9 Gout OPAMP Bout OPAMP 28 SDA SCL RES 22 23 24 I2C-BUS CONTROL SAA7167 CLOCK GENERATOR KEYING CONTROL 8 6 10 21 13 to 20 MGB743 VCLK PCLK Fig.1 Block diagram. 1995 Nov 03 3 EXTKEY P7 to P0 Philips Semiconductors Preliminary specification YUV-to-RGB Digital-to-Analog Converter (DAC) SAA7167 PINNING SYMBOL PIN DESCRIPTION I/O UV4 1 digital video UV (of YUV format 4 : 1 : 1 and 4 : 2 : 2) input data, or digital G and R input data I UV3 2 digital video UV (of YUV format 4 : 1 : 1 and 4 : 2 : 2) input data, or digital G and R input data I UV2 3 digital video UV (of YUV format 4 : 1 : 1 and 4 : 2 : 2) input data, or digital G and R input data I UV1 4 digital video UV (of YUV format 4 : 1 : 1 and 4 : 2 : 2) input data, or digital G and R input data I UV0 5 digital video UV (of YUV format 4 : 1 : 1 and 4 : 2 : 2) input data, or digital G and R input data I VCLK 6 video clock input I VDDD 7 digital supply voltage I/O VSSD 8 digital ground I/O HREF 9 horizontal reference input signal I PCLK 10 pixel clock input I AP 11 test pins, normally connected to ground I SP 12 test pins, normally connected to ground I P7 13 pixel bus input 7 (for keying control) I P6 14 pixel bus input 6 (for keying control) I P5 15 pixel bus input 5 (for keying control) I P4 16 pixel bus input 4 (for keying control) I P3 17 pixel bus input 3 (for keying control) I P2 18 pixel bus input 2 (for keying control) I P1 19 pixel bus input 1 (for keying control) I P0 20 pixel bus input 0 (for keying control) I EXTKEY 21 external key signal input I SDA 22 I2C-bus data line I/O SCL 23 I2C-bus RES 24 set to LOW to reset the I2C-bus I n.c. 25 not connected − VSSA2 26 analog ground 2 I/O VDDA2 27 analog supply voltage 2 I/O Bout 28 analog Blue signal output O Bin 29 analog Blue signal input I Gout 30 analog Green signal output O Gin 31 analog Green signal input I Rout 32 analog Red signal output O Rin 33 analog Red signal input I VSSA1 34 analog ground 1 I/O VDDA1 35 analog supply voltage 1 I/O Cref(h) 36 capacitor for reference high voltage output (2.25 V) I/O 1995 Nov 03 clock line I 4 Philips Semiconductors Preliminary specification YUV-to-RGB Digital-to-Analog Converter (DAC) SAA7167 YUV5 40 digital video Y or UV (of YUV format 2 : 1 : 1) input data, or digital G and B input data I YUV4 41 digital video Y or UV (of YUV format 2 : 1 : 1) input data, or digital G and B input data I YUV3 42 digital video Y or UV (of YUV format 2 : 1 : 1) input data, or digital G and B input data I YUV2 43 digital video Y or UV (of YUV format 2 : 1 : 1) input data, or digital G and B input data I YUV1 44 digital video Y or UV (of YUV format 2 : 1 : 1) input data, or digital G and B input data I YUV0 45 digital video Y or UV (of YUV format 2 : 1 : 1) input data, or digital G and B input data I UV7 46 digital video UV (of YUV format 4 : 1 : 1 and 4 : 2 : 2) input data, or digital G and R input data I UV6 47 digital video UV (of YUV format 4 : 1 : 1 and 4 : 2 : 2) input data, or digital G and R input data I UV5 48 digital video UV (of YUV format 4 : 1 : 1 and 4 : 2 : 2) input data, or digital G and R input data I UV4 1 36 Cref(h) UV3 2 35 VDDA1 UV2 3 34 VSSA1 UV1 4 33 Rin UV0 5 32 Rout VCLK 6 VDDD 7 30 Gout VSSD 8 29 Bin HREF 9 28 Bout 31 Gin SAA7167 5 RES 24 SCL 23 SDA 22 EXTKEY 21 P0 20 P1 19 P3 17 25 n.c. P2 18 SP 12 P4 16 26 VSSA2 P5 15 AP 11 P6 14 27 VDDA2 P7 13 PCLK 10 Fig.2 Pin configuration. 1995 Nov 03 37 n.c. I index corner I/O 38 YUV7 I digital video Y or UV (of YUV format 2 : 1 : 1) input data, or digital G and B input data 39 YUV6 digital video Y or UV (of YUV format 2 : 1 : 1) input data, or digital G and B input data 39 40 YUV5 38 YUV6 41 YUV4 YUV7 42 YUV3 − 43 YUV2 not connected 44 YUV1 37 45 YUV0 n.c. 46 UV7 DESCRIPTION 47 UV6 PIN 48 UV5 SYMBOL MGB744 Philips Semiconductors Preliminary specification YUV-to-RGB Digital-to-Analog Converter (DAC) SAA7167 FUNCTIONAL DESCRIPTION Table 2 The SAA7167 contains a video data path, 3 analog mixers and voltage output amplifiers for the RGB channels respectively, a keying control block as well as an I2C-bus control block. Pixel byte sequence of 4 : 1 : 1 INPUT PIXEL BYTE SEQUENCE OF 4 : 1 : 1 YUV0 Y0 Y0 Y0 Y0 Y0 Y0 Y0 Y0 YUV1 Y1 Y1 Y1 Y1 Y1 Y1 Y1 Y1 YUV2 Y2 Y2 Y2 Y2 Y2 Y2 Y2 Y2 Video data path YUV3 Y3 Y3 Y3 Y3 Y3 Y3 Y3 Y3 The video data path includes a video data re-formatter, a YUV-to-RGB colour space conversion matrix, and triple 8-bit DACs. YUV4 Y4 Y4 Y4 Y4 Y4 Y4 Y4 Y4 YUV5 Y5 Y5 Y5 Y5 Y5 Y5 Y5 Y5 YUV6 Y6 Y6 Y6 Y6 Y6 Y6 Y6 Y6 YUV7 Y7 Y7 Y7 Y7 Y7 Y7 Y7 Y7 UV0 X X X X X X X X UV1 X X X X X X X X UV2 X X X X X X X X UV3 X X X X X X X X UV4 V6 V4 V2 V0 V6 V4 V2 V0 UV5 V7 V5 V3 V1 V7 V5 V3 V1 UV6 U6 U4 U2 U0 U6 U4 U2 U0 UV7 U7 U5 U3 U1 U7 U5 U3 U1 0 1 2 3 4 5 6 7 RE-FORMATTER The re-formatter de-multiplexes the different video formats YUV 4 : 1 : 1, 4 : 2 : 2 or 2 : 1 : 1 to internal YUV 4 : 4 : 4, which can then be processed by the RGB matrix. The pixel byte sequences of those video input formats are shown in Tables 1 to 4. Table 1 Pixel byte sequence of 4 : 2 : 2 PIXEL BYTE SEQUENCE OF 4:2:2 INPUT YUV0 (LSB) Y0 Y0 Y0 Y0 Y0 Y0 YUV1 Y1 Y1 Y1 Y1 Y1 Y1 YUV2 Y2 Y2 Y2 Y2 Y2 Y2 YUV3 Y3 Y3 Y3 Y3 Y3 Y3 YUV4 Y4 Y4 Y4 Y4 Y4 Y4 YUV5 Y5 Y5 Y5 Y5 Y5 Y5 YUV6 Y6 Y6 Y6 Y6 Y6 Y6 Y7 Y7 Y7 Y7 Y7 Y7 UV0 (LSB) U0 V0 U0 V0 U0 V0 UV1 U1 V1 U1 V1 U1 V1 U2 V2 U2 V2 U2 V2 UV3 U3 V3 U3 V3 U3 V3 UV4 U4 V4 U4 V4 U4 V4 UV5 U5 V5 U5 V5 U5 V5 UV6 U6 V6 U6 V6 U6 V6 UV7 (MSB) U7 V7 U7 V7 U7 V7 0 1 2 3 4 5 YUV7 (MSB) UV2 Y data UV data 1995 Nov 03 0 2 Y data 0 UV data Table 3 Pixel byte sequence of 2 : 1 : 1 INPUT 4 6 4 PIXEL BYTE SEQUENCE OF 2 : 1 : 1 YUV0 U0 Y0 V0 Y0 U0 Y0 V0 Y0 YUV1 U1 Y1 V1 Y1 U1 Y1 V1 Y1 YUV2 U2 Y2 V2 Y2 U2 Y2 V2 Y2 YUV3 U3 Y3 V3 Y3 U3 Y3 V3 Y3 YUV4 U4 Y4 V4 Y4 U4 Y4 V4 Y4 YUV5 U5 Y5 V5 Y5 U5 Y5 V5 Y5 YUV6 U6 Y6 V6 Y6 U6 Y6 V6 Y6 YUV7 U7 Y7 V7 Y7 U7 Y7 V7 Y7 Y data X 0 X 2 X 4 X 6 UV data 0 X 0 X 4 X 4 X Philips Semiconductors Preliminary specification YUV-to-RGB Digital-to-Analog Converter (DAC) Table 4 SAA7167 Pixel byte sequence of 5 : 6 : 5 INPUT Analog mixers and keying control The analog mixers are controlled to switch between the outputs from the video DACs and analog RGB inputs by a keying signal. The analog RGB inputs need to interface with analog mixers in the way of DC-coupling, also these RGB inputs are limited to RGB signals without a sync level pedestal. The keying control can be enabled by setting I2C bit KEN = 1. Two kinds of keying are possible to generate: one is external key (from EXTKEY pin when KMOD2 to KMOD0 are logic 0), and the other is the internal pixel colour key (when KMOD2 to KMOD0 are not logic 0) generated by comparing the input pixel data with the internal I2C-bus register value KD7 to KD0. Controlled by KMOD2 to KMOD0 bits, there are 4 ways to compare the pixel data (see Table 5). PIXEL BYTE SEQUENCE OF RGB 5:6:5 UV7 G0 G0 G0 G0 UV6 R4 R4 R4 R4 UV5 R3 R3 R3 R3 UV4 R2 R2 R2 R2 UV3 R1 R1 R1 R1 UV2 R0 R0 R0 R0 UV1 G5 G5 G5 G5 UV0 G4 G4 G4 G4 YUV7 G3 G3 G3 G3 YUV6 G2 G2 G2 G2 YUV5 G1 G1 G1 G1 YUV4 B4 B4 B4 B4 YUV3 B3 B3 B3 B3 YUV2 B2 B2 B2 B2 KMOD2 to KMOD0 YUV1 B1 B1 B1 B1 100 8-bit pixel pseudo colour mode YUV0 B0 B0 B0 B0 101 2 × 8-bit pixel 0 1 2 3 high colour mode 1 with pixels given at both rising and falling edges of PCLK 110 2 × 8-bit pixel high colour mode 2 with pixels given only at rising edges of PCLK 111 3 × 8-bit pixel true colour mode RGB data Table 5 For RGB 5 : 6 : 5 video inputs, the video data are just directly bypassed to triple DACs. The input video data can be selected to either two’s complement (I2C-bus DRP-bit = 0) or binary offset (DRP-bit = 1). The video input format is selected by I2C-bus bits FMTC1 and FMTC0. KMOD2 to KMOD0 PIXEL TYPE REMARK Since only one control register KD7 to KD0 provides the data value for pixel data comparison, when at 2 × 8-bit or 3 × 8-bit pixel input modes, it is presumed that all input bytes (lower, middle, or higher) of each pixel must be same as KD7 to KD0 in order to make graphics colour key active. The rising edge of HREF input defines the start of active video data. When HREF is inactive, the video output will be blanked. YUV-TO-RGB MATRIX The polarity of EXTKEY can be selected with KINV. With KINV = 0, EXTKEY = HIGH switches analog mixers to select DAC outputs. Before the internal keying signal switches the analog multiplexers, it can be further delayed up to 7 PCLK cycles with the control bits KDLY2 to KDLY0. The matrix converts YUV data, in accordance with CCIR-601, to RGB data with approximately 1.5 LSB deviation to the theoretical values for 8-bit resolution. TRIPLE 8-BIT DACS Three identical DACs for R, G and B video outputs are designed with voltage-drive architecture to provide high-speed operation of up to 50 MHz conversion data rate. A Cref(h) pin is provided to allow for one external de-coupling capacitor to be connected between the internal reference voltage source and ground. 1995 Nov 03 7 Philips Semiconductors Preliminary specification YUV-to-RGB Digital-to-Analog Converter (DAC) SAA7167 With the digital input YUV video data in accordance with CCIR-601, the RGB output of 8-bit DAC actually ranges from the 16th step (black) to the 235th step (white). Therefore, after the voltage divider with external serial resistor and monitor load resistor, the output voltage range to monitor is approximately 0.7 V (peak-to-peak). Voltage output amplifiers Before the analog input enters the analog mixers, it passes through voltage output amplifiers. Level shifters are used internally to provide an offset of 0.2 V and an amplifier gain of 2 for analog inputs to match with the output levels from DACs. After buffering with voltage output amplifiers, the final RGB outputs can drive a 150 Ω load directly (25 Ω internal resistor, 50 Ω external serial resistor, and 75 Ω load resistor at monitor side (see Fig.9). I2C-bus control Only one control byte is needed for the SAA7167. The I2C-bus format is shown in Table 6. The output voltage level of DAC ranges from the lowest level 0.2 V (zero code) to the highest level 1.82 V (all one code). Table 6 S I2C-bus format slave address A subaddress A data A P Notes 1. S = START condition. 2. Slave address = 1011 111X; this slave address is identical to the one for the SAA9065; X = R/W control bit: a) X = 0; order to write. b) X = 1; order to read (not used for SAA7167). 3. A = acknowledge; generated by the slave. 4. Subaddress = subaddress byte. 5. Data = data byte. 6. P = STOP condition. Table 7 Control data byte SUBADDRESS D7 D6 D5 D4 D3 00 KMOD2 KMOD1 KMOD0 DRP 01 0 0 0 0 02 KD7 KD6 KD5 KD4 1995 Nov 03 8 D2 D1 D0 KEN KINV FMTC1 FMTC0 0 KDLY2 KDLY1 KDLY0 KD3 KD2 KD1 KD0 Philips Semiconductors Preliminary specification YUV-to-RGB Digital-to-Analog Converter (DAC) Table 8 SAA7167 Bit functions in data byte; notes 1 and 2 BIT DESCRIPTION FMTC1 and FMTC0 video format control: 00; YUV 4 : 2 : 2 01; YUV 4 : 1 : 1 10; YUV 2:1:1/CCIR 656 11; RGB 5 : 6 : 5 KINV key polarity: KINV = 0: EXTKEY = HIGH for analog mixer to select DAC outputs KINV = 1: EXTKEY = HIGH for analog mixer to select analog RGB inputs KEN key enable: 0 = disable 1 = enable DRP UV input data code: 0 = two’s complement; 1 = binary offset KMOD2 to KMOD0 keying mode: 000; external key 100; 8-bit pixel colour key 101; 2 × 8-bit pixel colour key (with two-edge clock latching for pixel input) 110; 2 × 8-bit pixel colour key (with one-edge clock latching for pixel input) 111; 3 × 8-bit pixel colour key (with one-edge clock latching for pixel input) all other combinations are reserved KDLY2 to KDLY0 added keying delay cycles (from 0 to 7 PCLK) KD7 to KD0 the data value compared for 8, 16 or 24-bit pixel colour key Notes 1. All I2C-bus control bits are initialized to logic 0 after RES is activated. 2. PCLK should be active in any event to allow for correct operation of I2C-bus programming. DC CHARACTERISTICS Tamb = 0 to 70 °C. SYMBOL PARAMETER MIN. TYP. MAX. UNIT VDDD digital supply voltage 4.75 5.0 5.25 V VDDA analog supply voltage 4.75 5.0 5.25 V IDDtot total supply current (fclk = 50 MHz) − 100 − mA VIH HIGH level input voltage (pin SDA) 3 − VDDD + 0.5 V VIL LOW level input voltage (pin SDA) −0.5 − +1.5 V VIH HIGH level digital input voltage 2 − − V VIL LOW level digital input voltage − − 0.8 V Vin full-scale analog RGB inputs − 0.7 − V Vout full scale analog RGB outputs (for 150 Ω load) − 1.4 − V DNL differential non-linearity error of video output − − 1 LSB INL integral non-linearity error of video output − − 1 LSB 1995 Nov 03 9 Philips Semiconductors Preliminary specification YUV-to-RGB Digital-to-Analog Converter (DAC) SAA7167 AC CHARACTERISTICS Tamb = 0 to 70 °C. SYMBOL PARAMETER MIN. − TYP. − MAX. UNIT fclk video clock rate δ duty factor of VCLK − 50 − % PCLK pixel clock rate (8-bit pixel colour key); see Fig.4 − − 50 MHz pixel clock rate (2 × 8-bit pixel colour key; mode 1); see Fig.5 − − 40 MHz pixel clock rate (2 × 8-bit pixel colour key; mode 2); see Fig.6 − − 80 MHz pixel clock rate (3 × 8-bit pixel colour key); see Fig.7 − − 75 MHz duty factor of PCLK 40 50 60 % 50 MHz tsu1 digital input set-up time to VCLK rising edge 3 − − ns th1 digital input hold time to VCLK rising edge 3 − − ns tsu2 digital input set-up time to PCLK rising edge 3 − − ns th2 digital input hold time to PCLK rising edge 3 − − ns tsu3 digital input set-up time to PCLK falling edge 3 − − ns th3 digital input hold time to PCLK falling edge 3 − − ns tsw switching time between video DAC/analog inputs; note 1 − − 15 ns Tgroup overall group delay from digital video inputs to analog outputs (see Fig.8): YUV video input mode − 20TVCLK + tPD − ns RGB video input mode − 12TVCLK + tPD − ns tr DAC analog output rise time (see Fig.8); note 2 − 5 − ns tf DAC analog output fall time (see Fig.8); note 2 − 5 − ns ts DAC analog output settling time (see Fig.8); note 3 − − 15 ns tPD DAC analog output propagation delay (see Fig.8); note 4 − 15 − ns Analog outputs from analog inputs Gv voltage gain − 2.0 − B bandwidth (−3 dB) − 75 − MHz SR slew rate − 90 − V/µs Notes 1. Switching time measured from the 50% point of the EXTKEY transition edge to the 50% point of the selected analog output transition. 2. DAC output rise/fall time measured between the 10% and 90% points of full scale transition. 3. DAC settling time measured from the 50% point of full-scale transition to the output remaining within ±1 LSB. 4. DAC analog output propagation delay measured from the 50% point of the rising edge of VCLK to the 50% point of full-scale transition. 1995 Nov 03 10 Philips Semiconductors Preliminary specification YUV-to-RGB Digital-to-Analog Converter (DAC) SAA7167 handbook, full pagewidth VCLK tsu1 HREF th1 YUV tsu1 UV MGB745 Fig.3 Video data input timing. handbook, full pagewidth PCLK tsu2 th2 P7 to P0 pixel 1 pixel 2 pixel 3 pixel 4 pixel 5 pixel 6 pixel 7 MGB746 Fig.4 Pixel data timing; 8-bit pixel colour key. 1995 Nov 03 11 Philips Semiconductors Preliminary specification YUV-to-RGB Digital-to-Analog Converter (DAC) SAA7167 handbook, full pagewidth PCLK tsu2 tsu3 th2 th3 P7 to P0 pixel 1 pixel 2 pixel 3 MGB747 Fig.5 Pixel data input timing; 2 × 8-bit pixel colour key; mode 1. handbook, full pagewidth PCLK tsu2 th2 P7 to P0 pixel 1 pixel 2 pixel 3 Fig.6 Pixel data input timing; 2 × 8-bit pixel colour key; mode 2. 1995 Nov 03 12 MGB748 Philips Semiconductors Preliminary specification YUV-to-RGB Digital-to-Analog Converter (DAC) SAA7167 handbook, full pagewidth PCLK tsu2 th2 P7 to P0 pixel 1 pixel 2 MGB749 Fig.7 Pixel data input timing; 3 × 8-bit pixel colour key. handbook, full pagewidth VCLK Tgroup YUV and UV (full-scale transition) ts tPD Rout, Bout and Gout tr; tf Fig.8 DAC output timing. 1995 Nov 03 13 MGB750 Philips Semiconductors Preliminary specification YUV-to-RGB Digital-to-Analog Converter (DAC) SAA7167 APPLICATION INFORMATION handbook, full pagewidth digital YUV video data inputs 8 38 to 45 36 YUV7 to YUV0 8 Cref(h) 0.1 µF 46 to 48, 1 to 5 UV7 to UV0 to PC monitor analog inputs from VGA Rin 47 Ω 32 33 Rout 75 Ω 75 Ω SAA7167 Gin 47 Ω 30 31 Gout 75 Ω Bin 75 Ω 47 Ω 29 28 Bout 75 Ω MGB751 75 Ω cable Fig.9 Typical application diagram for analog circuits. 1995 Nov 03 14 monitor side Philips Semiconductors Preliminary specification YUV-to-RGB Digital-to-Analog Converter (DAC) SAA7167 PACKAGE OUTLINE LQFP48: plastic low profile quad flat package; 48 leads; body 7 x 7 x 1.4 mm SOT313-2 c y X 36 25 A 37 24 ZE Q e E HE A A2 (A 3) A1 w M pin 1 index θ bp Lp L 13 48 detail X 12 1 ZD e v M A w M bp D B HD v M B 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (1) e HD HE L Lp Q v w y mm 1.60 0.20 0.05 1.45 1.35 0.25 0.27 0.17 0.18 0.12 7.1 6.9 7.1 6.9 0.5 9.15 8.85 9.15 8.85 1.0 0.75 0.45 0.69 0.59 0.2 0.12 0.1 Z D (1) Z E (1) θ 0.95 0.55 7 0o 0.95 0.55 Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION REFERENCES IEC JEDEC EIAJ ISSUE DATE 93-06-15 94-12-19 SOT313-2 1995 Nov 03 EUROPEAN PROJECTION 15 o Philips Semiconductors Preliminary specification YUV-to-RGB Digital-to-Analog Converter (DAC) SAA7167 If wave soldering cannot be avoided, the following conditions must be observed: SOLDERING Introduction • A double-wave (a turbulent wave with high upward pressure followed by a smooth laminar wave) soldering technique should be used. There is no soldering method that is ideal for all IC packages. Wave soldering is often preferred when through-hole and surface mounted components are mixed on one printed-circuit board. However, wave soldering is not always suitable for surface mounted ICs, or for printed-circuits with high population densities. In these situations reflow soldering is often used. • The footprint must be at an angle of 45° to the board direction and must incorporate solder thieves downstream and at the side corners. Even with these conditions, do not consider wave soldering LQFP packages LQFP48 (SOT313-2), LQFP64 (SOT314-2) or LQFP80 (SOT315-1). This text gives a very brief insight to a complex technology. A more in-depth account of soldering ICs can be found in our “IC Package Databook” (order code 9398 652 90011). During placement and before soldering, the package must be fixed with a droplet of adhesive. The adhesive can be applied by screen printing, pin transfer or syringe dispensing. The package can be soldered after the adhesive is cured. Reflow soldering Reflow soldering techniques are suitable for all LQFP packages. Maximum permissible solder temperature is 260 °C, and maximum duration of package immersion in solder is 10 seconds, if cooled to less than 150 °C within 6 seconds. Typical dwell time is 4 seconds at 250 °C. Reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. A mildly-activated flux will eliminate the need for removal of corrosive residues in most applications. Several techniques exist for reflowing; for example, thermal conduction by heated belt. Dwell times vary between 50 and 300 seconds depending on heating method. Typical reflow temperatures range from 215 to 250 °C. Repairing soldered joints Fix the component by first soldering two diagonallyopposite end leads. Use only a low voltage soldering iron (less than 24 V) applied to the flat part of the lead. Contact time must be limited to 10 seconds at up to 300 °C. When using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 °C. Preheating is necessary to dry the paste and evaporate the binding agent. Preheating duration: 45 minutes at 45 °C. Wave soldering Wave soldering is not recommended for LQFP packages. This is because of the likelihood of solder bridging due to closely-spaced leads and the possibility of incomplete solder penetration in multi-lead devices. 1995 Nov 03 16 Philips Semiconductors Preliminary specification YUV-to-RGB Digital-to-Analog Converter (DAC) SAA7167 DEFINITIONS Data sheet status Objective specification This data sheet contains target or goal specifications for product development. Preliminary specification This data sheet contains preliminary data; supplementary data may be published later. Product specification This data sheet contains final product specifications. Limiting values Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Where application information is given, it is advisory and does not form part of the specification. LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale. PURCHASE OF PHILIPS I2C COMPONENTS Purchase of Philips I2C components conveys a license under the Philips’ I2C patent to use the components in the I2C system provided the system conforms to the I2C specification defined by Philips. This specification can be ordered using the code 9398 393 40011. 1995 Nov 03 17 Philips Semiconductors Preliminary specification YUV-to-RGB Digital-to-Analog Converter (DAC) SAA7167 NOTES 1995 Nov 03 18 Philips Semiconductors Preliminary specification YUV-to-RGB Digital-to-Analog Converter (DAC) SAA7167 NOTES 1995 Nov 03 19 Philips Semiconductors – a worldwide company Argentina: IEROD, Av. Juramento 1992 - 14.b, (1428) BUENOS AIRES, Tel. (541)786 7633, Fax. (541)786 9367 Australia: 34 Waterloo Road, NORTH RYDE, NSW 2113, Tel. (02)805 4455, Fax. (02)805 4466 Austria: Triester Str. 64, A-1101 WIEN, P.O. Box 213, Tel. (01)60 101-1236, Fax. (01)60 101-1211 Belgium: Postbus 90050, 5600 PB EINDHOVEN, The Netherlands, Tel. (31)40-2783749, Fax. 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Printed in The Netherlands 483061/1100/01/pp20 Document order number: Date of release: 1995 Nov 03 9397 750 00416