Revised April 1999 74VHC139 Dual 2-to-4 Decoder/Demultiplexer General Description The VHC139 is an advanced high speed CMOS Dual 2-to4 Decoder/Demultiplexer fabricated with silicon gate CMOS technology. It achieves the high speed operation similar to equivalent Bipolar Schottky TTL while maintaining the CMOS low power dissipation. The active LOW enable input can be used for gating or it can be used as a data input for demultiplexing applications. When the enable input is held HIGH, all four outputs are fixed at a HIGH logic level independent of the other inputs. An input protection circuit ensures that 0V to 7V can be applied to the input pins without regard to the supply volt- age. This device can be used to interface 5V to 3V systems and two supply systems such as battery back up. This circuit prevents device destruction due to mismatched supply and input voltages. Features ■ High Speed: tPD = 5.0 ns (typ) at TA = 25°C ■ Low power dissipation: ICC = 4 µA (Max.) at TA = 25°C ■ High noise immunity: VNIH = VNIL = 28% VCC (Min.) ■ Power down protection is provided on all inputs ■ Pin and function compatible with 74HC139 Ordering Code: Order Number 74VHC139M 74VHC139SJ 74VHC139MTC 74VHC139N Package Number Package Description M16A 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150” Narrow M16D 16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide MTC16 N16E 16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide Surface mount packages are also available on Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Connection Diagram Pin Description Pin Names Description A0 , A1 Address Inputs E Enable Inputs O0–O3 Outputs Truth Table Inputs Outputs E A0 A1 O0 O1 O2 O3 H X X H H H H L L L L H H H L H L H L H H L L H H H L H L H H H H H L H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial © 1999 Fairchild Semiconductor Corporation DS011521.prf www.fairchildsemi.com 74VHC139 Dual 2-to-4 Decoder/Demultiplexer November 1992 74VHC139 Logic Symbols Functional Description The VHC139 is a high-speed dual 2-to-4 decoder/demultiplexer. The device has two independent decoders, each of which accepts two binary weighted inputs (A0–A1) and provides four mutually exclusive active-LOW outputs (O0–O3). Each decoder has an active-LOW enable (E). When E is HIGH all outputs are forced HIGH. The enable can be used as the data input for a 4-output demultiplexer application. Each half of the VHC139 generates all four minterms of two variables. These four minterms are useful in some applications, replacing multiple gate functions as shown in Figure 1, and thereby reducing the number of packages required in a logic network. IEEE/IEC FIGURE 1. Gate Functions (Each Half) Logic Diagram Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays. www.fairchildsemi.com 2 Supply Voltage (VCC) −0.5V to +7.0V DC Input Voltage (VIN) −0.5V to +7.0V Recommended Operating Conditions (Note 2) 2.0V to +5.5V Supply Voltage (VCC) −0.5V to VCC + 0.5V DC Output Voltage (VOUT) 0V to +5.5V Input Voltage (VIN) Input Diode Current (IIK) −20 mA Output Voltage (VOUT) Output Diode Current (IOK) ±20 mA Operating Temperature (TOPR) DC Output Current (IOUT) ±25 mA Input Rise and Fall Time (tr, tf) DC VCC/GND Current (ICC) ±75 mA VCC = 3.3V ± 0.3V 0 ∼ 100 ns/V −65°C to +150°C VCC = 5.0V ± 0.5V 0 ∼ 20 ns/V Storage Temperature (TSTG) Lead Temperature (TL) (Soldering, 10 seconds) 0V to VCC −40°C to +85°C Note 1: Absolute Maximum Ratings are values beyond which the device may be damaged or have its useful life impaired. The databook specifications should be met, without exception, to ensure that the system design is reliable over its power supply, temperature, and output/input loading variables. Fairchild does not recommend operation outside databook specifications. 260°C Note 2: Unused inputs must be held HIGH or LOW. They may not float. DC Electrical Characteristics Symbol VIH Parameter HIGH Level Input Voltage VIL LOW Level Input Voltage VOH VOL TA = 25°C VCC (V) Min Typ TA = −40°C to +85°C Max Min Max 2.0 1.50 1.50 3.0 − 5.5 0.7 VCC 0.7 VCC 2.0 0.50 0.50 0.3 VCC 0.3 VCC HIGH Level 2.0 1.9 2.0 1.9 3.0 2.9 3.0 2.9 4.5 4.4 4.5 4.4 3.0 2.58 2.48 4.5 3.94 3.80 Conditions V 3.0 − 5.5 Output Voltage Units V VIN = VIH IOH = −50 µA V or VIL IOH = −4 mA V IOH = −8 mA VIN = VIH IOL = 50 µA LOW Level 2.0 0.0 0.1 0.1 Output Voltage 3.0 0.0 0.1 0.1 4.5 0.0 0.1 0.1 3.0 0.36 0.44 4.5 0.36 0.44 0 − 5.5 ±0.1 ±1.0 µA VIN = 5.5V or GND 5.5 4.0 40.0 µA VIN = VCC or GND IIN Input Leakage Current ICC Quiescent Supply Current V or VIL IOL = 4 mA V IOL = 8 mA AC Electrical Characteristics Symbol Parameter tPLH Propagation Delay tPHL An to On VCC (V) 3.3 ± 0.3 5.0 ± 0.5 tPLH Propagation Delay tPHL En to On 3.3 ± 0.3 5.0 ± 0.5 TA = 25°C Min Typ TA = −40°C to +85°C Max Min Max 7.2 11.0 1.0 13.0 9.7 14.5 1.0 16.5 5.0 7.2 1.0 8.5 6.5 9.2 1.0 10.5 6.4 9.2 1.0 11.0 8.9 12.7 1.0 14.5 4.4 6.3 1.0 7.5 5.9 8.3 1.0 9.5 10 CIN Input Capacitance 4 CPD Power Dissipation Capacitance 26 10 Units ns ns ns ns Conditions CL = 15 pF CL = 50 pF CL = 15 pF CL = 50 pF CL = 15 pF CL = 50 pF CL = 15 pF CL = 50 pF pF VCC = Open pF (Note 3) Note 3: CPD is defined as the value of the internal equivalent capacitance which is calculated from the operating current consumption without load. Average operating current can be obtained by the equation: ICC (opr.) = CPD * VCC * fIN + ICC/2 (per decoder). 3 www.fairchildsemi.com 74VHC139 Absolute Maximum Ratings(Note 1) 74VHC139 Physical Dimensions inches (millimeters) unless otherwise noted 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150” Narrow Package Number M16A 16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide Package Number M16D www.fairchildsemi.com 4 74VHC139 Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide Package Number MTC16 5 www.fairchildsemi.com 74VHC139 Dual 2-to-4 Decoder/Demultiplexer Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide Package Number N16E LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 2. A critical component in any component of a life support 1. Life support devices or systems are devices or systems device or system whose failure to perform can be reawhich, (a) are intended for surgical implant into the sonably expected to cause the failure of the life support body, or (b) support or sustain life, and (c) whose failure device or system, or to affect its safety or effectiveness. to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the www.fairchildsemi.com user. Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications.