Revised August 2000 100370 Low Power Universal Demultiplexer/Decoder General Description Features The 100370 universal demultiplexer/decoder functions as either a dual 1-of-4 decoder or as a single 1-of-8 decoder, depending on the signal applied to the Mode Control (M) input. In the dual mode, each half has a pair of active-LOW Enable (E) inputs. Pin assignments for the E inputs are such that in the 1-of-8 mode they can easily be tied together in pairs to provide two active-LOW enables (E1a to E1b, E2a to E2b). Signals applied to auxiliary inputs Ha, Hb and Hc determine whether the outputs are active HIGH or active LOW. In the dual 1-of-4 mode the Address inputs are A0a, A1a and A0b, A1b with A2a unused (i.e., left open, tied to VEE or with LOW signal applied). In the 1-of-8 mode, the Address inputs are A0a, A1a, A2a with A0b and A1b LOW or OPEN. All inputs have 50 kΩ pull-down resistors. ■ 35% power reduction of the 100170 ■ 2000V ESD protection ■ Pin/function compatible with 100170 ■ Voltage compensated operating range = −4.2V to −5.7V Ordering Code: Order Number 100370PC Package Number N24E Package Description 24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-010, 0.400 Wide 100370QC V28A 28-Lead Plastic Lead Chip Carrier (PLCC), JEDEC MO-047, 0.450 Square 100370QI V28A 28-Lead Plastic Lead Chip Carrier (PLCC), JEDEC MO-047, 0.450 Square Industrial Temperature Range (−40°C to +85°C) Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Connection Diagrams 24-Pin DIP © 2000 Fairchild Semiconductor Corporation Powered by ICminer.com Electronic-Library Service CopyRight 2003 28-Pin PLCC DS010649 www.fairchildsemi.com 100370 Low Power Universal Demultiplexer/Decoder February 1990 100370 Logic Symbols Pin Descriptions Pin Names Single 1-of 8 Application Description Ana, Anb Address Inputs Ena, Enb Enable Inputs M Mode Control Input Ha Z0–Z3 (Z0a–Z3a) Polarity Select Input Hb Z4–Z7 (Z0b–Z3b) Polarity Select Input Hc Common Polarity Select Input Z0–Z7 Single 1-of-8 Data Outputs Zna, Znb Dual 1-of-4 Data Outputs Dual 1-of-4 Application- Truth Tables Dual 1-of-4 Mode (M = A2a = Hc = LOW) Inputs Active HIGH Outputs Active LOW Outputs (Ha and Hb Inputs HIGH) (Ha and Hb Inputs LOW) E1a E2a A1a A0a Z0a Z1a Z2a Z3a Z0a Z1a Z2a Z3a E1b E2b A1b A0b Z0b Z1b Z2b Z3b Z0b Z1b Z2b Z3b H X X X L L L L H H H H X H X X L L L L H H H H L L L L H L L L L H H H L L L H L H L L H L H H L L H L L L H L H H L H L H H L L L H H H H L L Single 1-of-8 Mode (M = HIGH; A0b = A1b = Ha = Hb = LOW) Inputs Active HIGH Outputs (Note 1) (Hc Input HIGH) H = HIGH Voltage Level E1 E2 A2a A1a A0a Z0 Z1 Z2 Z3 Z4 Z5 Z6 H X X X X L L L L L L L L X H X X X L L L L L L L L L L L L L H L L L L L L L L L L L H L H L L L L L L L L L H L L L H L L L L L L L L H H L L L H L L L L L L H L L L L L L H L L L L L H L H L L L L L H L L L L H H L L L L L L L H L L L H H H L L L L L L L H L = LOW Voltage Level X = Don’t Care E1 = E1a and E1b wired; E2 = E22a and E2b wired Note 1: for Hc = LOW, output states are complemented www.fairchildsemi.com Powered by ICminer.com Electronic-Library Service CopyRight 2003 Z7 2 100370 Logic Diagram (Zn) for 1-of-4 applications. 3 Powered by ICminer.com Electronic-Library Service CopyRight 2003 www.fairchildsemi.com 100370 Absolute Maximum Ratings(Note 2) Storage Temperature (TSTG) −65°C to +150 °C +150 °C Maximum Junction Temperature (TJ) VEE Pin Potential to Ground Pin Recommended Operating Conditions Case Temperature (TC) −7.0V to +0.5V Output Current (DC Output HIGH) −50 mA ESD (Note 3) ≥2000V 0°C to +85°C Commercial VEE to +0.5V Input Voltage (DC) −40°C to +85°C Industrial −5.7V to −4.2V Supply Voltage (VEE) Note 2: The “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The parametric values defined in the Electrical Characteristics tables are not guaranteed at the absolute maximum rating. The “Recommended Operating Conditions” table will define the conditions for actual device operation. Note 3: ESD testing conforms to MIL-STD-883, Method 3015. Commercial Version DC Electrical Characteristics (Note 4) VEE = −4.2V to −5.7V, VCC = VCCA = GND, TC = 0°C to +85°C Symbol Parameter Min Typ Max Units VOH Output HIGH Voltage −1025 −955 −870 mV VIN = VIH (Max) Loading with VOL Output LOW Voltage −1830 −1705 −1620 mV or VIL (Min) 50Ω to −2.0V VOHC Output HIGH Voltage −1035 mV VIN = VIH (Min) Loading with VOLC Output LOW Voltage −1610 mV or VIL (Max) 50Ω to −2.0V VIH Input HIGH Voltage −1165 −870 mV Guaranteed HIGH Signal for All Inputs VIL Input LOW Voltage −1830 −1475 mV Guaranteed LOW Signal for All Inputs IIL Input LOW Current 0.50 µA VIN = VIL (Min) IIH Input HIGH Current IEE Power Supply Current −95 Conditions 240 µA VIN = VIH (Max) −50 mA Inputs OPEN Note 4: The specified limits represent the “worst case” value for the parameter. Since these values normally occur at the temperature extremes, additional noise immunity and guardbanding can be achieved by decreasing the allowable system operating ranges. Conditions for testing shown in the tables are chosen to guarantee operation under “worst case” conditions. AC Electrical Characteristics VEE = −4.2V to −5.7V, VCC = VCCA = GND Symbol Parameter tPLH Propagation Delay tPHL Ena, Enb to Output tPLH Propagation Delay tPHL Ana, Anb to Output tPLH Propagation Delay tPHL Ha, Hb, Hc to Output tPLH Propagation Delay tPHL M to Output tTLH Transition Time tTHL 20% to 80%, 80% to 20% www.fairchildsemi.com Powered by ICminer.com Electronic-Library Service CopyRight 2003 TC = 0°C TC = +25°C TC = +85°C Units Min Max Min Max Min Max 0.75 1.85 0.75 1.85 0.85 2.05 ns 0.75 2.20 0.75 2.20 0.75 2.30 ns 0.75 2.20 0.75 2.20 0.75 2.20 ns 1.10 2.70 1.10 2.70 1.10 3.00 ns 0.40 1.30 0.40 1.30 0.40 1.30 ns 4 Conditions Figures 1, 2 100370 Commercial Version (Continued) PLCC AC Electrical Characteristics VEE = −4.2V to −5.7V, VCC = VCCA = GND Symbol Parameter tPLH Propagation Delay tPHL Ena, Enb to Output tPLH Propagation Delay tPHL Ana, Anb to Output tPLH Propagation Delay tPHL Ha, Hb, Hc to Output tPLH Propagation Delay tPHL M to Output tTLH Transition Time tTHL 20% to 80%, 80% to 20% TC = 0°C TC = +25°C TC = +85°C Units Min Max Min Max Min Max 0.75 1.65 0.75 1.65 0.85 1.85 ns 0.75 2.00 0.75 2.00 0.75 2.10 ns 0.75 2.00 0.75 2.00 0.75 2.00 ns 1.10 2.50 1.10 2.50 1.10 2.80 ns 0.40 1.20 0.40 1.20 0.40 1.20 ns Conditions Figures 1, 2 Industrial Version PLCC DC Electrical Characteristics (Note 5) VEE = −4.2V to −5.7V, VCC = VCCA = GND, TC = −40°C to +85°C TC = −40°C Symbol Parameter Min Typ TC = 0°C to +85°C Min Max Units Conditions VOH Output HIGH Voltage −1085 −870 −1025 −870 mV VIN = VIH (Max) VOL Output LOW Voltage −1830 −1575 −1830 −1620 mV or VIL (Min) 50Ω to −2.0V VOHC Output HIGH Voltage −1095 mV VIN = VIH (Min) Loading with VOLC Output LOW Voltage −1610 mV or VIL (Max) 50Ω to −2.0V VIH Input HIGH Voltage −1170 −870 −1165 −870 mV Guaranteed HIGH Signal VIL Input LOW Voltage −1830 −1480 −1830 −1475 mV Guaranteed LOW Signal IIL Input LOW Current 0.50 IIH Input HIGH Current IEE Power Supply Current −1035 −1565 Loading with for All Inputs for All Inputs 300 −95 µA 0.50 −50 −95 VIN = VIL (Min) 240 µA VIN = VIH (Max) −50 mA Inputs OPEN Note 5: The specified limits represent the “worst case” value for the parameter. Since these values normally occur at the temperature extremes, additional noise immunity and guardbanding can be achieved by decreasing the allowable system operating ranges. Conditions for testing shown in the tables are chosen to guarantee operation under “worst case” conditions. PLCC AC Electrical Characteristics VEE = −4.2V to −5.7V, VCC = VCCA = GND Symbol Parameter tPLH Propagation Delay tPHL Ena, Enb to Output tPLH Propagation Delay tPHL Ana, Anb to Output tPLH Propagation Delay tPHL Ha, Hb, Hc to Output tPLH Propagation Delay tPHL M to Output tTLH Transition Time tTHL 20% to 80%, 80% to 20% TC = −40°C TC = +25°C Units Max Min Max Min Max 0.75 1.65 0.75 1.65 0.85 1.85 ns 0.65 2.00 0.75 2.00 0.75 2.10 ns 0.70 2.00 0.75 2.00 0.75 2.00 ns 1.10 2.50 1.10 2.50 1.10 2.80 ns 0.40 1.30 0.40 1.20 0.40 1.20 ns 5 Powered by ICminer.com Electronic-Library Service CopyRight 2003 TC = +85°C Min Conditions Figures 1, 2 www.fairchildsemi.com 100370 Test Circuit Notes: VCC, VCCA = +2V, VEE = −2.5V L1 and L2 = equal length 50Ω impedance lines RT = 50Ω terminator internal to scope Decoupling 0.1 µF from GND to VCC and VEE All unused outputs are loaded with 50Ω to GND CL = Fixture and stray capacitance ≤ 3 pF FIGURE 1. AC Test Circuit Switching Waveforms FIGURE 2. Propagation Delay and Transition Times www.fairchildsemi.com Powered by ICminer.com Electronic-Library Service CopyRight 2003 6 100370 Physical Dimensions inches (millimeters) unless otherwise noted 24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-010, 0.400 Wide Package Number N24E 7 Powered by ICminer.com Electronic-Library Service CopyRight 2003 www.fairchildsemi.com 100370 Low Power Universal Demultiplexer/Decoder Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 28-Lead Plastic Lead Chip Carrier (PLCC), JEDEC MO-047, 0.450 Square Package Number V28A Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. www.fairchildsemi.com Powered by ICminer.com Electronic-Library Service CopyRight 2003 www.fairchildsemi.com 8