UC1625-SP SLUSAG8A – SEPTEMBER 2011 – REVISED SEPTEMBER 2011 www.ti.com RAD-TOLERANT CLASS V, BRUSHLESS DC MOTOR CONTROLLER Check for Samples: UC1625-SP FEATURES • 1 • • • • • (1) QML-V Qualified, SMD 5962-91689 Rad-Tolerant: 40 kRad (Si) TID (1) Drives Power MOSFETs or Power Darlingtons Directly 50-V Open Collector High-Side Drivers Latched Soft Start Radiation tolerance is a typical value based upon initial device qualification with dose rate = 10 mrad/sec. Radiation Lot Acceptance Testing is available - contact factory for detials. • • • • • • • High-speed Current-Sense Amplifier with Ideal Diode Pulse-by-Pulse and Average Current Sensing Over-Voltage and Under-Voltage Protection Direction Latch for Safe Direction Reversal Tachometer Trimmed Reference Sources 30 mA Programmable Cross-Conduction Protection Two-Quadrant and Four-Quadrant Operation DESCRIPTION/ORDERING INFORMATION The UC1625 motor controller integrates most of the functions required for high-performance brushless dc motor control into one package. When coupled with external power MOSFETs or Darlingtons, this device performs fixed-frequency PWM motor control in either voltage or current mode while implementing closed loop speed control and braking with smart noise rejection, safe direction reversal, and cross-conduction protection. Although specified for operation from power supplies between 10 V and 18 V, the UC1625 can control higher voltage power devices with external level-shifting components. The UC1625 contains fast, high-current push-pull drivers for low-side power devices and 50-V open-collector outputs for high-side power devices or level shifting circuitry. The UC1625 is characterized for operation over the military temperature range of –55°C to 125°C. ORDERING INFORMATION (1) (1) (2) TA PACKAGE (2) ORDERABLE PART NUMBER TOP-SIDE MARKING –55°C to 125°C CDIP – JT 5962-9168902VYA 5962-9168902VYA UC1625-SP For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI website at www.ti.com. Package drawings, thermal data, and symbolization are available at www.ti.com/packaging. 1 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2011, Texas Instruments Incorporated UC1625-SP SLUSAG8A – SEPTEMBER 2011 – REVISED SEPTEMBER 2011 www.ti.com Typical Application +15 V +5 V TO HALL SENSORS VREF 100 nF 100 nF 20 mF QUAD 3 kW ROSC 33 kW 2 2N3904 10 W 19 11 22 DIR 3 kW 1k 17 1 18 UC3625 UC1625 28 4 kW 14 27 13 25 2200 pF COSC TO MOTOR TO OTHER CHANNELS 10 W 15 IRF532 20 21 26 3 24 23 8 9 10 4 5 7 68 kW RT 10 kW 100 nF 5 nF 3 nF CT REQUIRED FOR BRAKE AND FAST REVERSE TO OTHER CHANNELS 12 BRAKE 2N3906 IRF9350 16 6 100 nF + 100 mF 3 kW + 20 mF 10 kW 10 kW VMOTOR FROM HALL SENSORS 100 nF 2 nF 51 kW 5 nF 2 nF REQUIRED FOR AVERAGE CURRENT SENSING 240 W 240 W 0.02 W RS 0.02 W RD 2 nF VREF ABSOLUTE MAXIMUM RATINGS (1) (2) over operating free-air temperature range (unless otherwise noted) VALUE VCC PWR VCC UNIT 20 Supply voltage 20 –0.3 to 6 PWM IN E/A IN(+), E/A IN(–) –0.3 to 12 ISENSE1, ISENSE2 –1.3 to 6 OV-COAST, DIR, SPEED-IN, SSTART, QUAD SEL –0.3 to 8 H1, H2, H3 –0.3 to 12 PU Output Voltage –0.3 to 50 PU +200 continuous PD ±200 continuous E/A ±10 Output current ISENSE –10 –50 continuous VREF (1) (2) 2 mA ±10 TACH OUT TJ V Maximum Junction Temperature 150 °C Currents are positive into and negative out of the specified terminal. Stresses above these ratings may cause permanent damage. Exposure to absolute maximum conditions for extended periods may degrade device reliability. These are stress ratings only and functional operation of the device at these or any other conditions beyond those specified is not implied. Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated Product Folder Link(s) :UC1625-SP UC1625-SP SLUSAG8A – SEPTEMBER 2011 – REVISED SEPTEMBER 2011 www.ti.com RECOMMENDED OPERATING CONDITIONS over operating temperature range (unless otherwise noted) MIN VCC Supply Voltage PU Output Current NOM 10 Operating temperature range UNIT 18 PD TA MAX -55 V +85 continuous mA ±85 continuous mA 125 °C Table 1. THERMAL RATINGS TABLE PACKAGE RθJA(°C/W) (Junction-to-ambient thermal resistance) RθJC(°C/W) (Junction-to-case thermal resistance) DIL-28 (JT) 43.1 4.95 Figure 1. CONNECTION DIAGRAM E/A IN(+) 1 28 E/A IN(-) VREF 2 27 E/A OUT ISENSE 3 26 PWM IN ISENSE1 4 25 RC-OSC ISENSE2 5 24 SSTART DIR 6 23 OV-COAST SPEED-IN 7 22 QUAD SEL H1 8 21 RC-BRAKE H2 9 20 TACH-OUT H3 10 19 VCC PWR VCC 11 18 PUA PDC 12 17 PUB PDB 13 16 PUC PDA 14 15 GND Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated Product Folder Link(s) :UC1625-SP 3 UC1625-SP SLUSAG8A – SEPTEMBER 2011 – REVISED SEPTEMBER 2011 www.ti.com ELECTRICAL CHARACTERISTICS Unless otherwise stated, these specifications apply over the full temperature range, typical values at TA = 25°C; Pwr VCC = VCC = 12 V; ROSC = 20 kΩ to VREF; COSC = 2 nF; RTACH = 33 kΩ; CTACH = 10 nF; and all outputs unloaded. TA = TJ. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT mA Overall Supply current 14.5 30.0 8.65 8.95 9.55 7.75 8.05 8.55 OV-COAST inhibit threshold 1.65 1.75 1.85 OV-COAST restart threshold 1.535 1.65 1.75 0.05 0.10 0.155 –10 –1 10 0.8 1.0 1.25 1.6 1.9 2.0 –400 –250 –120 0.8 1.4 3.0 V 70 130 mV V VCC turn-on threshold -55°C to 125°C VCC turn-off threshold V Overvoltage/Coast OV-COAST hysteresis -55°C to 125°C OV-COAST input current V μA Logic Inputs H1, H2, H3 low threshold H1, H2, H3 high threshold H1, H2, H3 input current -55°C to 125°C -55°C to 125°C, to 0 V QUAD SEL, dir thresholds QUAD SEL hysteresis DIR hysteresis 0.4 0.6 0.9 QUAD SEL input current -55°C to 125°C –30 50 150 DIR input current –30 –1 30 V μA μA PWM Amp/Comparator E/A IN(+), E/A IN(–) input current To 2.5 V –5.0 –0.1 5.0 PWM IN input current To 2.5 V 0 3 30 Error amp input offset 0 V < VCOMMON-MODE < 3 V Error amp voltage gain E/A OUT range Pullup current SSTART 70 10 90 0.25 3.50 -55°C 0.25 4.2 To 0 V, 25°C To 2.5 V Restart threshold -16 –10 –17.5 mV dB 25°C to 125°C To 0 V , -55°C to 125°C Discharge current –10 μA –5 -5 V μA 0.1 0.4 3.0 mA 0.1 0.2 0.3 V 1.75 1.95 2.15 V/V Current Amp Gain ISENSE1 = 0.3 V, ISENSE2 = 0.5 V to 0.7 V Level shift ISENSE1 = 0.3 V, ISENSE2 = 0.3 V Peak current threshold Over current threshold ISENSE1, ISENSE2 input current ISENSE1, ISENSE2 offset current ISENSE1 = 0 V, force ISENSE2 To 0 V 2.4 2.5 2.65 0.14 0.20 0.26 0.26 0.30 0.36 –850 –320 0 -12 ±2 12 –1 Range ISENSE1, ISENSE2 2 V μA V Tachometer/Brake TACH-OUT high level TACH-OUT low level -55°C to 125°C, 10 kΩ to 2.5 V On time 4 4.7 -55°C to 125°C RC-BRAKE input current To 0 V Submit Documentation Feedback 5.3 0.2 170 On time change with temp 5 220 280 V μs 0.1% –4.0 –1.9 mA Copyright © 2011, Texas Instruments Incorporated Product Folder Link(s) :UC1625-SP UC1625-SP SLUSAG8A – SEPTEMBER 2011 – REVISED SEPTEMBER 2011 www.ti.com ELECTRICAL CHARACTERISTICS (continued) Unless otherwise stated, these specifications apply over the full temperature range, typical values at TA = 25°C; Pwr VCC = VCC = 12 V; ROSC = 20 kΩ to VREF; COSC = 2 nF; RTACH = 33 kΩ; CTACH = 10 nF; and all outputs unloaded. TA = TJ. PARAMETER TEST CONDITIONS MIN TYP MAX 0.8 1.0 1.2 0.09 0.4 220 257 290 mV –30 –5 30 μA Voh, –1 mA, down from VCC 1.60 2.50 Voh, –50 mA, down from VCC 1.75 2.45 0.05 0.4 Threshold to brake, RC-brake Brake hysteresis, RC-brake SPEED-IN threshold -55°C to 125°C SPEED-IN input current UNIT V Low-Side Drivers (1) Vol, 1 mA -55°C to 125°C Vol, 50 mA Rise/fall time 10% to 90% slew time, into 1 nF 0.36 0.9 50 500 0.1 0.4 1.0 1.8 V ns High-Side Drivers Vol, 1 mA Vol, 50 mA -55°C to 125°C Leakage current Output voltage = 50 V Fall time 10% to 90% slew time, 50 mA load Frequency -55°C to 125°C 30 50 V μA ns Oscillator 30 80 kHz Reference 4.85 5.0 5.15 -55°C to 125°C 4.7 5.0 5.3 Load regulation 0 mA to –20 mA load –40 –5 Line regulation 10 V to 18 V VCC –10 –1 10 Short circuit current -55°C to 125°C 20 100 150 Output voltage Iref = 0 mA, 25°C V mV mA Miscellaneous (1) Output turn-on delay 1 Output turn-off delay 1 μs Current available from these pins can peak as high as 0.5 A. Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated Product Folder Link(s) :UC1625-SP 5 UC1625-SP SLUSAG8A – SEPTEMBER 2011 – REVISED SEPTEMBER 2011 www.ti.com Block Diagram QUAD SEL 22 RC-OSC 25 PWM IN 26 E/A OUT 27 E/A IN(+) 1 E/A IN (–) 28 SSTART 24 ISENSE 3 S OSC VCC 19 OV-COAST 23 R 0.2 V 2.5 V 250 Ω PUB 16 PUC 11 PWR VCC 14 PDA 13 PDB 12 PDC 15 GND 20 TACH-OUT S 3.1 V 9V PWM CLOCK 6 DIRECTION LATCH 7 0.25 V +5 V PWM CLOCK DIR 8 D +5 V Q H1 Q H2 COAST CHOP QUAD CROSS CONDUCTION PROTECTION LATCHES L 9 D +5 V H3 17 Q1 Q 1.75 V H2 PUA 10µA 4 5 H1 18 2.9 V ISENSE2 SPEED-IN VREF R 2X DIR 2 PWM CLOCK ABS VALUE ISENSE1 5V REFERENCE Q DECODER L 10 D L Q H3 BRAKE EDGE DETECT +5 V 2k RC-BRAKE 21 ONE SHOT 1V 6 Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated Product Folder Link(s) :UC1625-SP UC1625-SP SLUSAG8A – SEPTEMBER 2011 – REVISED SEPTEMBER 2011 www.ti.com DEVICE INFORMATION Terminal Functions TERMINAL NAME DIR, SPEED-IN E/A IN(+), E/A IN(–), E/A OUT, PWM IN GND H1, H2, H3 ISENSE1, ISENSE2, ISENSE OV-COAST NO. DESCRIPTION 6, 7 The position decoder logic translates the Hall signals and the DIR signal to the correct driver signals (PUs and PDs). To prevent output stage damage, the signal on DIR is first loaded into a direction latch, then shifted through a two-bit register. As long as SPEED-IN is less than 250 mV, the direction latch is transparent. When SPEED-IN is higher than 250 mV, the direction latch inhibits all changes indirection. SPEED-IN can be connected to TACH-OUT through a filter, so that the direction latch is only transparent when the motor is spinning slowly, and has too little stored energy to damage power devices. Additional circuitry detects when the input and output of the direction latch are different, or when the input and output of the shift register are different, and inhibits all output drives during that time. This can be used to allow the motor to coast to a safe speed before reversing. The shift register ensures that direction can not be changed instantaneously. The register is clocked by the PWM oscillator, so the delay between direction changes is always going to be between one and two oscillator periods. At 40 kHz, this corresponds to a delay of between 25 μs and 50 μs. Regardless of output stage, 25 μs deadtime should be adequate to ensure no overlap cross-conduction. Toggling DIR causes an output pulse on TACH-OUT regardless of motor speed. 1, 28, 27, 26 E/A IN(+) and E/A IN(–) are not internally committed to allow for a wide variety of uses. They can be connected to the ISENSE, to TACH-OUT through a filter, to an external command voltage, to a D/A converter for computer control, or to another op amp for more elegant feedback loops. The error amplifier is compensated for unity gain stability, so E/A OUT can be tied to E/A IN(–) for feedback and major loop compensation. E/A OUT and PWM In drive the PWM comparator. For voltage-mode PWM systems, PWM In can be connected to RC-OSC. The PWM comparator clears the PWM latch, commanding the outputs to chop. The error amplifier can be biased off by connecting E/A IN(–) to a higher voltage than /EA IN(+). When biased off, E/A OUT appears to the application as a resistor to ground. E/A OUT can then be driven by an external amplifier. 15 All thresholds and outputs are referred to the GND pin except for the PD and PU outputs. 8, 9, 10 The three shaft position sensor inputs consist of hysteresis comparators with input pullup resistors. Logic thresholds meet TTL specifications and can be driven by 5-V CMOS, 12-V CMOS, NMOS, or open-collectors. Connect these inputs to motor shaft position sensors that are positioned 120 electrical degrees apart. If noisy signals are expected, zener clamp and filter these inputs with 6-V zeners and an RC filter. Suggested filtering components are 1 kΩ and 2 nF. Edge skew in the filter is not a problem, because sensors normally generate modified gray code with only one output changing at a time, but rise and fall times must be shorter than 20 μs for correct tachometer operation. Motors with 60 electrical degree position sensor coding can be used if one or two of the position sensor signals is inverted. 3, 4, 5 The current sense amplifier has a fixed gain of approximately two. It also has a built-in level shift of approximately 2.5 V. The signal appearing on ISENSE is: ISENSE = 2.5 V + (2 × ABS ( ISENSE1 – ISENSE2) ) ISENSE1 and ISENSE2 are interchangeable and can be used as differential inputs. The differential signal applied can be as high as ±0.5 V before saturation. If spikes are expected on ISENSE1 or ISENSE2, they are best filtered by a capacitor from ISENSE to ground. Filtering this way allows fast signal inversions to be correctly processed by the absolute value circuit. The peak-current comparator allows the PWM to enter a current-limit mode with current in the windings never exceeding approximately 0.2 V / RSENSE. The overcurrent comparator provides a fail-safe shutdown in the unlikely case of current exceeding 0.3 V / RSENSE. Then, softstart is commanded, and all outputs are turned off until the high current condition is removed. It is often essential to use some filter driving ISENSE1 and ISENSE2 to reject extreme spikes and to control slew rate. Reasonable starting values for filter components might be 250-Ω series resistors and a 5-nF capacitor between ISENSE1 and ISENSE2. Input resistors should be kept small and matched to maintain gain accuracy. 23 This input can be used as an over-voltage shut-down input, as a coast input, or both. This input can be driven by TTL, 5-V CMOS, or 12-V CMOS. Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated Product Folder Link(s) :UC1625-SP 7 UC1625-SP SLUSAG8A – SEPTEMBER 2011 – REVISED SEPTEMBER 2011 www.ti.com Terminal Functions (continued) TERMINAL NAME PDA, PDB, PDC PUA, PUB, PUC PWR VCC QUAD SEL RC-BRAKE RC-OSC 8 NO. DESCRIPTION 12, 13, 14 These outputs can drive the gates of N-channel power MOSFETs directly or they can drive the bases of power Darlingtons if some form of current limiting is used. They are meant to drive low-side power devices in high-current output stages. Current available from these pins can peak as high as 0.5 A. These outputs feature a true totem-pole output stage. Beware of exceeding device power dissipation limits when using these outputs for high continuous currents. These outputs pull high to turn a “low-side” device on (active high). 16, 17, 18 These outputs are open-collector, high-voltage drivers that are meant to drive high-side power devices in high-current output stages. These are active low outputs, meaning that these outputs pull low to command a high-side device on. These outputs can drive low-voltage PNP Darlingtons and P-channel MOSFETs directly, and can drive any high-voltage device using external charge pump techniques, transformer signal coupling, cascode level-shift transistors, or opto-isolated drive (high-speed opto devices are recommended). (See applications). 11 This supply pin carries the current sourced by the PD outputs. When connecting PD outputs directly to the bases of power Darlingtons, the PWR VCC pin can be current limited with a resistor. Darlington outputs can also be "Baker Clamped" with diodes from collectors back to PWR VCC. (See Applications) 22 The device can chop power devices in either of two modes, referred to as “two-quadrant” (Quad Sellow) and “four quadrant” (Quad Sel high). When two-quadrant chopping, the pulldown power devices are chopped by the output of the PWM latch while the pullup drivers remain on. The load chops into one commutation diode, and except for back-EMF, will exhibit slow discharge current and faster charge current. Two-quadrant chopping can be more efficient than four-quadrant. When four-quadrant chopping, all power drivers are chopped by the PWM latch, causing the load current to flow into two diodes during chopping. This mode exhibits better control of load current when current is low, and is preferred in servo systems for equal control over acceleration and deceleration. The QUAD SEL input has no effect on operation during braking. 21 Each time the TACH-OUT pulses, the capacitor tied to RC-BRAKE discharges from approximately 3.33 V down to 1.67 V through a resistor. The tachometer pulse width is approximately T = 0.67 RT CT, where RT and CT are a resistor and capacitor from RC-BRAKE to ground. Recommended values for RT are 10 kΩ to 500 kΩ, and recommended values for CT are 1 nF to 100 nF, allowing times between 5 μs and 10 ms. Best accuracy and stability are achieved with values in the centers of those ranges. RC-BRAKE also has another function. If RC-BRAKE pin is pulled below the brake threshold, the device enters brake mode. This mode consists of turning off all three high-side devices, enabling all three low-side devices, and disabling the tachometer. The only things that inhibit low-side device operation in braking are low-supply, exceeding peak current, OV-COAST command, and the PWM comparator signal. The last of these means that if current sense is implemented such that the signal in the current sense amplifier is proportional to braking current, the low-side devices will brake the motor with current control. (See applications) Simpler current sense connections results in uncontrolled braking and potential damage to the power devices. 25 The UC1625 can regulate motor current using fixed-frequency pulse width modulation (PWM). The RC-OSC pin sets oscillator frequency by means of timing resistor ROSC from the RC-OSC pin to VREF and capacitor COSC from RC-OSC to Gnd. Resistors 10 kΩ to 100 kΩ and capacitors 1 nF to 100 nF works the best, but frequency should always be below 500 kHz. Oscillator frequency is approximately: F = 2/(ROSC x COSC ) Additional components can be added to this device to cause it to operate as a fixed off-time PWM rather than a fixed frequency PWM, using the RC-OSC pin to select the monostable time constant. The voltage on the RC-OSC pin is normally a ramp of about 1.2 V peak-to-peak, centered at approximately 1.6 V. This ramp can be used for voltage-mode PWM control, or can be used for slope compensation in current-mode control. Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated Product Folder Link(s) :UC1625-SP UC1625-SP SLUSAG8A – SEPTEMBER 2011 – REVISED SEPTEMBER 2011 www.ti.com Terminal Functions (continued) TERMINAL NAME DESCRIPTION NO. 24 Any time that VCC drops below threshold or the sensed current exceeds the over-current threshold, the soft-start latch is set. When set, it turns on a transistor that pulls down on SSTART. Normally, a capacitor is connected to this pin, and the transistor will completely discharge the capacitor. A comparator senses when the NPN transistor has completely discharged the capacitor, and allows the soft-start latch to clear when the fault is removed. When the fault is removed, the soft-start capacitor charges from the on-chip current source. SSTART clamps the output of the error amplifier, not allowing the error amplifier output voltage to exceed SSTART regardless of input. The ramp on RC-OSC can be applied to PWM In and compared to E/A OUT. With SSTART discharged below 0.2 V and the ramp minimum being approximately 1.0 V, the PWM comparator keeps the PWM latch cleared and the outputs off. As SSTART rises, the PWM comparator begins to duty-cycle modulate the PWM latch until the error amplifier inputs overcome the clamp. This provides for a safe and orderly motor start-up from an off or fault condition. A 51-kΩ resister is added between VREF and SSTART to ensure switching. 20 Any change in the H1, H2, or H3 inputs loads data from these inputs into the position sensor latches. At the same time data is loaded, a fixed-width 5-V pulse is triggered on TACH-OUT. The average value of the voltage on TACH-OUT is directly proportional to speed, so this output can be used as a true tachometer for speed feedback with an external filter or averaging circuit which usually consists of a resistor and capacitor. Whenever TACH-OUT is high, the position latches are inhibited, such that during the noisiest part of the commutation cycle, additional commutations are not possible. Although this effectively sets a maximum rotational speed, the maximum speed can be set above the highest expected speed, preventing false commutation and chatter. VCC 19 This device operates with supplies between 10 V and 18 V. Under-voltage lockout keeps all outputs off below 7.5 V, insuring that the output transistors never turn on until full drive capability is available. Bypass VCC to ground with an 0.1-μF ceramic capacitor. Using a 10-μF electrolytic bypass capacitor as well can be beneficial in applications with high supply impedance. VREF 2 This pin provides regulated 5 V for driving Hall-effect devices and speed control circuitry. VREF reaches 5 V before VCC enables, ensuring that Hall-effect devices powered from VREF becomes active before the UC1625 drives any output. For proper performance VREF should be bypassed with at least a 0.1-μF capacitor to ground. SSTART TACH-OUT TYPICAL CHARACTERISTICS Oscillator Frequency vs COSC and ROSC Tachometer on Time vs RT and CT 100 ms 1 MHz RT – 500 k RT – 100 k ROSC – 10 k 1 ms On Time Oscillator Frequency 10 ms ROSC – 10 k 100 kHz ROSC – 100 k 10 kHz 1 kHz 100 ms 10 ms 1 ms 0.001 100 Hz 0.001 0.01 0.1 RT – 30 k RT – 10 k 0.01 0.1 CT – mF COSC (mF) Figure 2. Figure 3. Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated Product Folder Link(s) :UC1625-SP 9 UC1625-SP SLUSAG8A – SEPTEMBER 2011 – REVISED SEPTEMBER 2011 www.ti.com TYPICAL CHARACTERISTICS (continued) Soft-Start Pullup Current vs Temperature 20 -5 18 -6 16 -7 14 -8 Soft Start Current – mA Supply Current – mA Supply Current vs Temperature 12 10 8 6 -9 -10 -11 -12 4 -13 2 -14 0 -75 -50 -25 0 25 50 75 100 -15 -75 125 -50 Temperature – C -25 0 25 50 75 100 125 Temperature – C Figure 4. Figure 5. Soft-Start Discharge Current vs Temperature Current Sense Amplifier Transfer Function vs ISENSE2 – ISENSE1 1.25 3.5 .75 ISENSE – V Soft Start Current – mA 1.00 3 .50 .25 0 -75 -50 -25 0 25 50 75 100 125 2.5 -0.5 Temperature – C 0.5 ISENSE2 – ISENSE1 – V Figure 6. 10 0.0 Figure 7. Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated Product Folder Link(s) :UC1625-SP UC1625-SP SLUSAG8A – SEPTEMBER 2011 – REVISED SEPTEMBER 2011 www.ti.com APPLICATION INFORMATION Cross Conduction Prevention The UC1625 inserts delays to prevent cross conduction due to overlapping drive signals. However, some thought must always be given to cross conduction in output stage design because no amount of dead time can prevent fast slewing signals from coupling drive to a power device through a parasitic capacitance. The UC1625 contains input latches that serve as noise blanking filters. These latches remain transparent through any phase of a motor rotation and latch immediately after an input transition is detected. They remain latched for two cycles of the PWM oscillator. At a PWM oscillator speed of 20 kHz, this corresponds to 50 μs to 100 μs of blank time which limits maximum rotational speed to 100 kRPM for a motor with six transitions per rotation or 50 kRPM for a motor with 12 transitions per rotation. This prevents noise generated in the first 50 μs of a transition from propagating to the output transistors and causing cross-conduction or chatter. The UC1625 also contains six flip flops corresponding to the six output drive signals. One of these flip flops is set every time that an output drive signal is turned on, and cleared two PWM oscillator cycles after that drive signal is turned off. The output of each flip flop is used to inhibit drive to the opposing output (Figure 8). In this way, it is impossible to turn on driver PUA and PDA at the same time. It is also impossible for one of these drivers to turn on without the other driver having been off for at least two PWM oscillator clocks. EDGE FINDER SHIFT REG PWM CLK S Q R Q S Q R Q PUA PULL UP FROM DECODER PULL DOWN PDA Figure 8. Cross Conduction Prevention Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated Product Folder Link(s) :UC1625-SP 11 UC1625-SP SLUSAG8A – SEPTEMBER 2011 – REVISED SEPTEMBER 2011 www.ti.com Power Stage Design The UC1625 is useful in a wide variety of applications, including high-power in robotics and machinery. The power output stages used in such equipment can take a number of forms, according to the intended performance and purpose of the system. Figure 9 show four different power stages with the advantages and disadvantages of each. For high-frequency chopping, fast recovery circulating diodes are essential. Six are required to clamp the windings. These diodes should have a continuous current rating at least equal to the operating motor current, since diode conduction duty-cycle can be high. For low-voltage systems, Schottky diodes are preferred. In higher voltage systems, diodes such as Microsemi UHVP high voltage platinum rectifiers are recommended. In a pulse-by-pulse current control arrangement, current sensing is done by resistor RS, through which the transistor's currents are passed (Fig. A, B, and C). In these cases, RD is not needed. The low-side circulating diodes go to ground and the current sense terminals of the UC1625 (ISENSE1 and ISENSE2) are connected to RS through a differential RC filter. The input bias current of the current sense amplifier causes a common mode offset voltage to appear at both inputs, so for best accuracy, keep the filter resistors below 2 kΩ and matched. The current that flows through RS is discontinuous because of chopping. It flows during the on time of the power stage and is zero during the off time. Consequently, the voltage across RS consists of a series of pulses, occurring at the PWM frequency, with a peak value indicative of the peak motor current. To sense average motor current instead of peak current, add another current sense resistor (RD in Fig. D) to measure current in the low-side circulating diodes, and operate in four quadrant mode (pin 22 high). The negative voltage across RD is corrected by the absolute value current sense amplifier. Within the limitations imposed by Table 2, the circuit of Fig. B can also sense average current. 12 Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated Product Folder Link(s) :UC1625-SP UC1625-SP SLUSAG8A – SEPTEMBER 2011 – REVISED SEPTEMBER 2011 www.ti.com FIGURE A FIGURE B TO MOTOR TO MOTOR RS RS FIGURE C FIGURE D TO MOTOR TO MOTOR RS RD RS Figure 9. Four Power Stage Designs Table 2. Imposed Limitations for Figure 9 2 QUADRANT 4 QUADRANT SAFE BRAKING POWER REVERSE Figure A Yes No No CURRENT SENSE Pulse-by-Pulse Average N0 Yes No Yes Figure B Yes Yes No In 4-quad mode only Yes Figure C Yes Yes Yes In 4-quad mode only Yes No Figure D Yes Yes Yes In 4-quad mode only Yes Yes Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated Product Folder Link(s) :UC1625-SP 13 UC1625-SP SLUSAG8A – SEPTEMBER 2011 – REVISED SEPTEMBER 2011 www.ti.com For drives where speed is critical, P-channel MOSFETs can be driven by emitter followers as shown in Figure 10. Here, both the level shift NPN and the PNP must withstand high voltages. A zener diode is used to limit gate-source voltage on the MOSFET. A series gate resistor is not necessary, but always advisable to control overshoot and ringing. High-voltage optocouplers can quickly drive high-voltage MOSFETs if a boost supply of at least 10 V greater than the motor supply is provided (See Figure 11) To protect the MOSFET, the boost supply should not be higher than 18 V above the motor supply. For under 200-V 2-quadrant applications, a power NPN driven by a small P-Channel MOSFET performs well as a high-side driver as in Figure 12. A high voltage small-signal NPN is used as a level shift and a high voltage low-current MOSFET provides drive. Although the NPN does not saturate if used within its limitations, the base-emitter resistor on the NPN is still the speed-limiting component. Figure 13 shows a power NPN Darlington drive technique using a clamp to prevent deep saturation. By limiting saturation of the power device, excessive base drive is minimized and turn-off time is kept fairly short. Lack of base series resistance also adds to the speed of this approach. Figure 10. Fast High-Side P-Channel Driver 14 Figure 11. Optocoupled N-Channel High-Side Driver Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated Product Folder Link(s) :UC1625-SP UC1625-SP SLUSAG8A – SEPTEMBER 2011 – REVISED SEPTEMBER 2011 www.ti.com Figure 12. Power NPN High-Side Driver Figure 13. Power NPN Low-Side Driver Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated Product Folder Link(s) :UC1625-SP 15 UC1625-SP SLUSAG8A – SEPTEMBER 2011 – REVISED SEPTEMBER 2011 www.ti.com Fast High-Side N-Channel Driver with Transformer Isolation A small pulse transformer can provide excellent isolation between the UC1625 and a high-voltage N-Channel MOSFET while also coupling gate drive power. In this circuit (shown in Figure 14), a UC3724 is used as a transformer driver/encoder that duty-cycle modulates the transformer with a 150-kHz pulse train. The UC3725 rectifies this pulse train for gate drive power, demodulates the signal, and drives the gate with over 2-A peak current. +12V VMOTOR 3 33kW 6 7 PUA 2 7 UC3724N UC3725N 4 4 8 1:2 8 1 5kW 2 5 1nF 1 6 3 100nF TO MOTOR Figure 14. Fast High-Side N-Channel Driver with Transformer Isolation Both the UC3724 and the UC3725 can operate up to 500 kHz if the pulse transformer is selected appropriately. To raise the operating frequency, either lower the timing resistor of the UC3724 (1 kΩ min), lower the timing capacitor of the UC3724 (500 pF min) or both. If there is significant capacitance between transformer primary and secondary, together with very high output slew rate, then it may be necessary to add clamp diodes from the transformer primary to 12 V and ground. General purpose small signal switching diodes such as 1N4148 are normally adequate. The UC3725 also has provisions for MOSFET current limiting. See the UC3725 data sheet for more information on implementing this. 16 Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated Product Folder Link(s) :UC1625-SP UC1625-SP SLUSAG8A – SEPTEMBER 2011 – REVISED SEPTEMBER 2011 www.ti.com Computational Truth Table Table 3 shows the outputs of the gate drive and open collector outputs for given hall input codes and direction signals. Numbers at the top of the columns are pin numbers. These devices operate with position sensor encoding that has either one or two signals high at a time, never all low or all high. This coding is sometimes referred to as "120° Coding" because the coding is the same as coding with position sensors spaced 120 magnetic degrees about the rotor. In response to these position sense signals, only one low-side driver turns on (go high) and one high-side driver turns on (pull low) at any time. Table 3. Computational Truth Table INPUTS OUTPUTS DIR H1 H2 H3 Low-Side High-Side 6 8 9 10 12 13 14 16 17 18 1 0 0 1 L H L L H H 1 0 1 1 L L H L H H 1 0 1 0 L L H H L H 1 1 1 0 H L L H L H 1 1 0 0 H L L H H L 1 1 0 1 L H L H H L 0 1 0 1 L L H H L H 0 1 0 0 L L H L H H 0 1 1 0 L H L L H H 0 0 1 0 L H L H H L 0 0 1 1 H L L H H L 0 0 0 1 H L L H L H X 1 1 1 L L L H H H X 0 0 0 L L L H H H Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated Product Folder Link(s) :UC1625-SP 17 UC1625-SP SLUSAG8A – SEPTEMBER 2011 – REVISED SEPTEMBER 2011 www.ti.com VREF +15V +5V TO HALL SENSORS 100nF 100nF 20mF QUAD ROSC 33kW 3kW 2 2N3904 10W 19 11 22 DIR 3kW 17 1 28 100nF 18 UC3625 UC1625 14 27 13 25 2200pF COSC 2N3906 IRF9350 16 6 1k 4kW TO MOTOR TO OTHER CHANNELS 10W 15 IRF532 20 21 3nF CT REQUIRED FOR BRAKE AND FAST REVERSE TO OTHER CHANNELS 12 BRAKE + 100mF 3kW + 20mF 10kW 10kW VMOTOR 26 68kW RT 3 24 23 8 9 10 4 5 7 100nF 5nF FROM HALL SENSORS 100nF 2nF 51kW 10kW 240W 5nF 240W 2nF 2nF VREF 0.02 W RS REQUIRED FOR AVERAGE CURRENT SENSING 0.02 W RD Figure 15. 45-V/8-A Brushless DC Motor Drive Circuit N-Channel power MOSFETs are used for low-side drivers, while P-Channel power MOSFETs are shown for high-side drivers. Resistors are used to level shift the UC1625 open-collector outputs, driving emitter followers into the MOSFET gate. A 12-V zener clamp insures that the MOSFET gate-source voltage never exceeds 12 V. Series 10-Ω gate resistors tame gate reactance, preventing oscillations and minimizing ringing. The oscillator timing capacitor should be placed close to pins 15 and 25, to keep ground current out of the capacitor. Ground current in the timing capacitor causes oscillator distortion and slaving to the commutation signal. The potentiometer connected to pin 1 controls PWM duty cycle directly, implementing a crude form of speed control. This control is often referred to as "voltage mode" because the potentiometer position sets the average motor voltage. This controls speed because steady-state motor speed is closely related to applied voltage. Pin 20 (Tach-Out) is connected to pin 7 (SPEED IN) through an RC filter, preventing direction reversal while the motor is spinning quickly. In two-quadrant operation, this reversal can cause kinetic energy from the motor to be forced into the power MOSFETs. A diode in series with the low-side MOSFETs facilitates PWM current control during braking by insuring that braking current will not flow backwards through low-side MOSFETs. Dual current-sense resistors give continuous current sense, whether braking or running in four-quadrant operation, an unnecessary luxury for two-quadrant operation. The 68-kΩ and 3-nF tachometer components set maximum commutation time at 140 μs. This permits smooth operation up to 35,000 RPM for four-pole motors, yet gives 140 μs of noise blanking after commutation. 18 Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated Product Folder Link(s) :UC1625-SP PACKAGE OPTION ADDENDUM www.ti.com 24-Sep-2011 PACKAGING INFORMATION Orderable Device 5962-9168902VYA Status (1) Package Type Package Drawing ACTIVE CDIP JT Pins Package Qty 28 1 Eco Plan TBD (2) Lead/ Ball Finish A42 MSL Peak Temp (3) Samples (Requires Login) N / A for Pkg Type (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. OTHER QUALIFIED VERSIONS OF UC1625-SP : • Catalog: UC1625 NOTE: Qualified Version Definitions: • Catalog - TI's standard catalog product Addendum-Page 1 MECHANICAL DATA MCER004A – JANUARY 1995 – REVISED JANUARY 1997 JT (R-GDIP-T**) CERAMIC DUAL-IN-LINE 24 LEADS SHOWN PINS ** A 13 24 B 1 24 28 A MAX 1.280 (32,51) 1.460 (37,08) A MIN 1.240 (31,50) 1.440 (36,58) B MAX 0.300 (7,62) 0.291 (7,39) B MIN 0.245 (6,22) 0.285 (7,24) DIM 12 0.070 (1,78) 0.030 (0,76) 0.100 (2,54) MAX 0.320 (8,13) 0.290 (7,37) 0.015 (0,38) MIN 0.200 (5,08) MAX Seating Plane 0.130 (3,30) MIN 0.023 (0,58) 0.015 (0,38) 0°–15° 0.014 (0,36) 0.008 (0,20) 0.100 (2,54) 4040110/C 08/96 NOTES: A. B. C. D. E. All linear dimensions are in inches (millimeters). This drawing is subject to change without notice. This package can be hermetically sealed with a ceramic lid using glass frit. Index point is provided on cap for terminal identification. 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