19-2855; Rev 2; 4/05 2- to 8-Phase VRM 10/9.1 PWM Controllers with Precise Current Sharing and Fast Voltage Positioning The MAX8525 (VRM 10/VRD 10)/MAX8524 (VRM 9.1/ VRD 9.1) current-mode step-down controllers, the MAX8523 high-speed, dual-phase MOSFET gate driver, and the MAX8552 wide-input, single-phase MOSFET gate driver provide flexible, low-cost, low-voltage CPU core supplies. The MAX8523 and MAX8552 high-speed, high-current gate drivers allow operation at high switching frequencies to reduce external component size and cost for small-footprint, low-profile designs. Pin-selectable 2-, 3-, and 4-phase operation and master-slave 6and 8-phase operation provide output-current scalability for servers, workstations, desktops, desk notes, and networking applications. The switching frequency of the MAX8524/MAX8525 is adjustable from 150kHz to 1.2MHz, permitting loop bandwidths of up to 200kHz. Peak current-mode control provides fast transient response and reduces cost. A proprietary current-sharing scheme reduces current imbalance between phases to less than 5% at full load. The MAX8524/MAX8525 offer 0.4% initial accuracy and remote-sense functionality. Both controllers also feature programmable no-load offset and output-voltage positioning to adjust the output voltage as a function of the output current. The fast-active voltage positioning further reduces bulk output capacitors and cost. Current-mode control also simplifies compensation with a variety of capacitors by eliminating the output-filter double pole associated with voltage-mode controllers. Both devices are compatible with electrolytic, tantalum, polymer, and ceramic capacitors. Output current sensing eliminates issues associated with controllers that use high-side current sense and ensure stable and jitter-free operation. Temperature-compensated, lossless inductor current sense eliminates the need for a current-sense resistor and further reduces cost, while maintaining voltage-positioning accuracy and reducing power dissipation. The MAX8525 features control VID voltage transition for dynamic VID changes and eliminate both undervoltage and overvoltage overshoot. The PWRGD signal is accurate during VID code changes for the MAX8525 to avoid any false fault signal. Adjustable foldback current-limit and overvoltage protection provide for a robust design. Applications Servers, Workstations Desktop Computers Desk Notes and LCD PCs Voltage-Regulator Modules High-End Switches and Routers Features ♦ ♦ ♦ ♦ ♦ ♦ ♦ ♦ ♦ ♦ ♦ ♦ ♦ ♦ VRD/VRM 10 (MAX8525) VRD/VRM 9.1 (MAX8524) Fastest Load-Transient Response Rapid-Active Average Current Sensing Better than 5% Current Balance Fastest Voltage Positioning ±0.4% Initial Output-Voltage Accuracy Pin-Selectable 2-/3-/4-Phase Operation Master-Slave 6-/8-Phase Operation Differential Remote Voltage Sensing Dynamic VID Change (MAX8525) Adjustable, Foldback Current Limit Soft-Start and Soft-Stop Power-Good Output 150kHz to 1.2MHz Switching Frequency per Phase 28-Lead QSOP Package Ordering Information PART TEMP RANGE PIN-PACKAGE MAX8524EEI -40°C to +85°C 28 QSOP MAX8524EEI+ -40°C to +85°C 28 QSOP MAX8525EEI -40°C to +85°C 28 QSOP MAX8525EEI+ -40°C to +85°C 28 QSOP +Denotes lead-free package. Pin Configurations TOP VIEW PWM3 1 28 PWM2 PWM1 2 27 PWM4 CS1+ 3 26 CS4+ CS1_3- 4 25 CS2_4- CS3+ 5 VCC 6 24 CS2+ MAX8525 GND 7 23 RS+ 22 RS- COMP 8 21 EN REF 9 20 VID4 ILIM 10 19 VID3 OSC 11 18 VID2 PWRGD 12 17 VID1 CLKO 13 16 VID0 CLKI 14 15 VID5 QSOP Pin Configurations continued at end of data sheet. Functional Diagram appears at end of data sheet. ________________________________________________________________ Maxim Integrated Products For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at 1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com. 1 MAX8524/MAX8525 General Description MAX8524/MAX8525 2- to 8-Phase VRM 10/9.1 PWM Controllers with Precise Current Sharing and Fast Voltage Positioning ABSOLUTE MAXIMUM RATINGS REF, COMP, VID0 to VID5, OSC, CLKI, CLKO to GND ..........................................-0.3V to VCC + 0.3V RS+, RS-, ILIM to GND .................................-0.3V to VCC + 0.3V PWM_ to GND...............................................-0.3V to VCC + 0.3V EN, PWRGD, VCC to GND ........................................-0.3V to +6V CS1_3-, CS2_4-, CS_+ to GND ....................-0.3V to VCC + 0.3V Continuous Power Dissipation (TA = +70°C) 28-Pin QSOP (derate 10.8mW/°C above +70°C).........860mW Operating Temperature Range ...........................-40°C to +85°C Junction Temperature ......................................................+150°C Storage Temperature Range .............................-65°C to +150°C Lead Temperature (soldering, 10s) .................................+300°C Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ELECTRICAL CHARACTERISTICS (VCC = 5V, VID_ = high, ILIM = 1.5V, EN = open, RS- = GND = 0V, CLKI = open, CLKO = open, ROSC = 95.3kΩ to GND, PWRGD = 100kΩ to VCC, PWM_ = open, COMP = 1V, CS_+ = 1.1V, CS1_3- = CS2_4- = RS+ = 1.1V, TA = 0°C to +85°C, unless otherwise noted.) PARAMETER CONDITIONS MIN TYP MAX UNITS 5.5 V 4.5 V GENERAL VCC Operating Range VCC UVLO Trip Level 4.5 Rising 4.0 4.25 Hysteresis 270 VCC Shutdown Supply Current VCC < 3.75V, VID_ = GND 0.7 3 mV mA VCC Standby Supply Current EN = 0V, VCC = 5.5V 13 20 mA VCC Operating Supply Current RS+ = 1.2V (no switching), set VID code for 1.100V 13 20 mA Thermal Shutdown Rising temperature, typical hysteresis = 15°C 165 °C REFERENCE 2.0 - 0.4% Reference Voltage IREF = 200µA Reference Load Regulation 100µA < IREF < 500µA Reference Line Regulation 4.5V < VCC < 5.5V -0.05 Reference UVLO Trip Level Rising edge, has 80mV typical hysteresis 1.74 2.0 1.84 2.0 + 0.4% V -0.05 % +0.05 % 1.95 V SOFT-START Soft-Start Step Size Soft-Start Time per Step 12.5 Soft-start counts from EN rising (Note 1) 17 20 mV 23 µs VOLTAGE REGULATION RS+ Input Bias Current VRS+ = 1.1V 0.1 1 µA RS- Input Bias Current VRS- = 0.2V 0.1 1 µA VOUT Initial Accuracy VID_ = 1.1V, TA = +25°C -0.4 +0.4 VID_ = 1.1V -0.6 +0.6 VOUT Droop Accuracy (CS_+) = 1.125V ±5 COMP Output Current (VO+) - (RS+) = 200mV % % 385 µA GMV Amplifier Transconductance 2 mS GMV Amplifier Gain-Bandwidth Product 5 MHz 2 _______________________________________________________________________________________ 2- to 8-Phase VRM 10/9.1 PWM Controllers with Precise Current Sharing and Fast Voltage Positioning (VCC = 5V, VID_ = high, ILIM = 1.5V, EN = open, RS- = GND = 0V, CLKI = open, CLKO = open, ROSC = 95.3kΩ to GND, PWRGD = 100kΩ to VCC, PWM_ = open, COMP = 1V, CS_+ = 1.1V, CS1_3- = CS2_4- = RS+ = 1.1V, TA = 0°C to +85°C, unless otherwise noted.) PARAMETER CONDITIONS MIN TYP MAX UNITS 0.2 5 µA +10 % 1 µA CURRENT-SENSE AMPLIFIERS CS_+, CS_- Input Bias Current CS_+ = CS_- = 2V, RS+ = 0V Average Current-Limit Trip Level Accuracy VILIM = 1.5V, TA = +85°C ILIM Input Bias Current VILIM = 1.5V ILIM Default Program Level VILIM ≥ VCC - 0.2V -10 0.01 Peak Current-Limit Delay Time 1 V 20 ns 10 % OSCILLATOR Oscillator Frequency Accuracy Switching Frequency Range (per Phase) 150 1200 Slave-Mode CLKI/Set Frequency Ratio 0.8 4.0 Maximum CLKO Duty-Cycle Skew CLKO load < 50pF and ROSC = 40.2kΩ 2 kHz % LOGIC INPUTS (EN) Input Low Level VCC = 4.5V to 5.5V Input High Level VCC = 4.5V to 5.5V Input Pullup Level Internal pullup Input Pullup Resistance Internal pullup 0.8 2.8 VCC 50 V V 100 V 200 kΩ 1.2 V LOGIC INPUTS (CLKI) Input Low Level VCC = 4.5V to 5.5V Input High Level VCC = 4.5V to 5.5V Input Pulldown Level Internal pulldown Input Pulldown Resistance Internal pulldown 3.6 V GND 50 100 V 200 kΩ 0.8 V MAX8524 LOGIC INPUTS (VID0–VID4) Input Low Level VCC = 4.5V to 5.5V Input High Level VCC = 4.5V to 5.5V 1.6 Internal pullup resistance 10 Input Pullup Level V VCC Input Pullup Resistance 15 V 20 kΩ 0.4 V MAX8525 LOGIC INPUTS (VID0–VID5) Input Low Level VCC = 4.5V to 5.5V Input High Level VCC = 4.5V to 5.5V 0.8 V PWRGD OUTPUT Output Low Level IPWRGD = 4mA 0.4 V Output High Leakage VPWRGD = 5.5V 1 µA PWRGD Blanking Time From EN rising, tracks CLKO 5 ms 3 _______________________________________________________________________________________ 3 MAX8524/MAX8525 ELECTRICAL CHARACTERISTICS (continued) MAX8524/MAX8525 2- to 8-Phase VRM 10/9.1 PWM Controllers with Precise Current Sharing and Fast Voltage Positioning ELECTRICAL CHARACTERISTICS (continued) (VCC = 5V, VID_ = high, ILIM = 1.5V, EN = open, RS- = GND = 0V, CLKI = open, CLKO = open, ROSC = 95.3kΩ to GND, PWRGD = 100kΩ to VCC, PWM_ = open, COMP = 1V, CS_+ = 1.1V, CS1_3- = CS2_4- = RS+ = 1.1V, TA = 0°C to +85°C, unless otherwise noted.) PARAMETER CONDITIONS MIN TYP MAX Output rising VID + 0.125 VID + 0.175 Output falling VID + 0.075 VID + 0.125 Output falling VID 0.250 VID 0.200 Output rising VID 0.175 VID 0.125 MAX8524 output rising VID + 0.20 VID + 0.25 MAX8525 output rising VID + 0.175 VID + 0.225 PWRGD Upper Threshold UNITS V PWRGD Lower Threshold V OVP PROTECTION Output Overvoltage Trip Threshold, OVP Action V PWM, CKLO OUTPUTS Output Low Level IPWM_ = -5mA Output High Level IPWM_ = +5mA 0.1 4.5 0.4 V 4.9 V Source Current VPWM_ = VCC - 2V 84 mA Sink Current VPWM_ = 2V 83 mA 10 ns Rise/Fall Times PWM Selection Threshold VCC = 4.5V to 5.5V 0.8 2.3 3.1 V ELECTRICAL CHARACTERISTICS (VCC = 5V, VID_ = high, ILIM = 1.5V, EN = open, RS- = GND = 0V, CLKI = open, CLKO = open, ROSC = 95.3kΩ to GND, PWRGD = 100kΩ to VCC, PWM_ = open, COMP = 1V, CS_+ = 1.1V, CS1_3- = CS2_4- = RS+ = 1.1V, TA = -40°C to +85°C, unless otherwise noted.) (Note 2) PARAMETER CONDITIONS MIN TYP MAX UNITS 4.5 5.5 V 4.0 4.5 V mA GENERAL VCC Operating Range VCC UVLO Trip Level Rising, typical hysteresis 270mV VCC Shutdown Supply Current VCC < 3.75V, VID_ = high 3 VCC Standby Supply Current EN = 0V, VCC = 5.5V 20 mA VCC Operating Supply Current RS+ = 1.2V (no switching), set VID code for 1.100V 20 mA 2.0 0.5% 2.0 + 0.4% V REFERENCE Reference Voltage IREF = 200µA Reference Load Regulation 100µA < IREF < 500µA -0.05 % Reference Line Regulation 4.5V < VCC < 5.5V -0.05 +0.05 % Reference UVLO Trip Level Rising edge, has 80mV typical hysteresis 1.74 1.95 V 4 _______________________________________________________________________________________ 2- to 8-Phase VRM 10/9.1 PWM Controllers with Precise Current Sharing and Fast Voltage Positioning (VCC = 5V, VID_ = high, ILIM = 1.5V, EN = open, RS- = GND = 0V, CLKI = open, CLKO = open, ROSC = 95.3kΩ to GND, PWRGD = 100kΩ to VCC, PWM_ = open, COMP = 1V, CS_+ = 1.1V, CS1_3- = CS2_4- = RS+ = 1.1V, TA = -40°C to +85°C, unless otherwise noted.) (Note 2) PARAMETER CONDITIONS MIN TYP MAX UNITS 23 µs SOFT-START Soft-Start Time per Step Soft-start counts from EN rising (Note 1) 17 VOLTAGE REGULATION RS+ Input Bias Current VRS+ = 1.1V 1 µA RS- Input Bias Current VRS- = 0.2V 1 µA VOUT Initial Accuracy VID_ = 1.1V +1 % -1 CURRENT-SENSE AMPLIFIERS CS_+, CS_- Input Bias Current CS_+ = CS_- = 2V, RS+ = 0V 5 µA ILIM Input Bias Current VILIM = 1.5V 1 µA kHz OSCILLATOR Switching Frequency Range (per Phase) 150 1200 Slave-Mode CLKI/Set Frequency Ratio 0.8 4.0 LOGIC INPUTS (EN) Input Low Level VCC = 4.5V to 5.5V Input High Level VCC = 4.5V to 5.5V 2.8 0.8 Input Pullup Resistance Internal pullup 50 V V 200 kΩ 1.2 V 200 kΩ 0.8 V LOGIC INPUTS (CLKI) Input Low Level VCC = 4.5V to 5.5V Input High Level VCC = 4.5V to 5.5V 3.6 Input Pulldown Resistance Internal pulldown 50 V MAX8524 LOGIC INPUTS (VID0–VID4) Input Low Level VCC = 4.5V to 5.5V Input High Level VCC = 4.5V to 5.5V 1.7 Input Pullup Resistance Internal pullup resistance 10 V 20 kΩ 0.4 V MAX8525 LOGIC INPUTS (VID0–VID5) Input Low Level VCC = 4.5V to 5.5V Input High Level VCC = 4.5V to 5.5V 0.8 V _______________________________________________________________________________________ 5 MAX8524/MAX8525 ELECTRICAL CHARACTERISTICS (continued) MAX8524/MAX8525 2- to 8-Phase VRM 10/9.1 PWM Controllers with Precise Current Sharing and Fast Voltage Positioning ELECTRICAL CHARACTERISTICS (continued) (VCC = 5V, VID_ = high, ILIM = 1.5V, EN = open, RS- = GND = 0V, CLKI = open, CLKO = open, ROSC = 95.3kΩ to GND, PWRGD = 100kΩ to VCC, PWM_ = open, COMP = 1V, CS_+ = 1.1V, CS1_3- = CS2_4- = RS+ = 1.1V, TA = -40°C to +85°C, unless otherwise noted.) (Note 2) PARAMETER CONDITIONS MIN TYP MAX UNITS 0.4 V PWRGD OUTPUT Output Low Level IPWRGD = 4mA Output High Leakage VPWRGD = 5.5V PWRGD Blanking Time From EN rising, tracks CLKO 1 µA 3 5 ms Output rising VID + 0.125 VID + 0.175 Output falling VID + 0.075 VID + 0.125 Output falling VID 0.250 VID 0.200 Output rising VID 0.175 VID 0.125 MAX8524 output rising VID + 0.20 VID + 0.25 MAX8525 output rising VID + 0.175 VID + 0.225 PWRGD Upper Threshold V PWRGD Lower Threshold V OVP PROTECTION Output Overvoltage Trip Threshold, OVP Action V PWM, CLKO OUTPUTS Output Low Level IPWM_ = -5mA Output High Level IPWM_ = +5mA 4.5 PWM Selection Threshold VCC = 4.5V to 5.5V 0.8 Note 1: Total soft-start time equals the soft-start time per step times the VID voltage divided by 12.5mV. Note 2: Specifications at -40°C are guaranteed by design. 6 _______________________________________________________________________________________ 0.4 V 3.1 V V 2- to 8-Phase VRM 10/9.1 PWM Controllers with Precise Current Sharing and Fast Voltage Positioning EFFICIENCY vs. LOAD CURRENT AT 1.45V OUTPUT OUTPUT VOLTAGE vs. LOAD CURRENT 80 1.175 80A IOUT 1.150 70 0A VIN = 12V 1.125 VOUT 60 VIN = 5V 50 40 1.100 VOUT 50mV/div 1.075 30 1.050 20 POWERGOOD OUTPUT 1.025 10 0 1.000 10 1 100 0 10µs 10 20 30 40 50 60 70 80 90 100 LOAD CURRENT (A) LOAD CURRENT (A) DYNAMIC VID RESPONSE, 250mV STEP VOLTAGE 4-PHASE ACTIVE CURRENT SHARING MAX8524 toc05 MAX8524 toc04 25 20 INDUCTOR CURRENT (A) EFFICIENCY VIN = 12V MAX8524 toc02 90 OUTPUT LOAD TRANSIENT MAX8524 toc03 1.200 MAX8524 toc01 100 POWER-GOOD OUTPUT 15 PHASE 1 INDUCTOR CURRENT 10A/div 10 OUTPUT VOLTAGE 200mV/div 5 0 0 10 20 30 40 50 60 70 80 90 100 40µs LOAD CURRENT (A) SOFT-START WAVEFORMS AT 1.45V OUTPUT SOFT-STOP WAVEFORMS AT 1.45V OUTPUT MAX8524 toc06 ENABLE INPUT MAX8524 toc07 POWERGOOD OUTPUT INPUT CURRENT 0.5A/div ENABLE INPUT POWERGOOD OUTPUT 0A INPUT CURRENT 0.5A/div OUTPUT VOLTAGE 0.5V/div OUTPUT VOLTAGE 0.5V/div IOUT = 0A 1ms 400µs _______________________________________________________________________________________ 7 MAX8524/MAX8525 Typical Operating Characteristics (VIN = 12V, VOUT = 1.2V, IOUT_MAX = 80A, fSW = 250kHz, TA = +25°C, unless otherwise noted.) Typical Operating Characteristics (continued) (VIN = 12V, VOUT = 1.2V, IOUT_MAX = 80A, fSW = 250kHz, TA = +25°C, unless otherwise noted.) SHORT-CIRCUIT AND RECOVERY WAVEFORMS REFERENCE VOLTAGE vs. TEMPERATURE CURRENT-SENSE THRESHOLD vs. VILIM MAX8524 toc09 PHASE 1 INDUCTOR CURRENT 10A/div 1.000 REFERENCE VOLTAGE (V) 1.200 VILIM (V) 2.010 0.800 0.600 0.400 MAX8524 toc11 1.400 MAX8524 toc10 POWERGOOD OUTPUT OUTPUT VOLTAGE 0.5V/div 2.005 2.000 1.995 0.200 0 1.990 0 1ms 10 20 30 40 50 60 70 80 90 100 -40 -20 0 OUTPUT CURRENT (A) 2.000 100 0 200 300 400 500 CLOCK FREQUENCY vs. TEMPERATURE CLKO RISE AND FALL TIME vs. TEMPERATURE MAX8524 toc14 ROSC = 294kΩ 9 8 8 7 RISE 6 6 5 5 4 4 3 0 3 FALL 2 2 1 1 0 -40 -20 0 20 40 60 TEMPERATURE (°C) 80 100 120 10 9 7 3 2 MAX8524 toc15 10 ROSC = 43.2kΩ ROSC = 105kΩ 80 1000 ROSC RESISTOR (kΩ) 1 8 100 10 RISE (ns) 4 4900 4600 4300 4000 3700 3400 3100 2800 2500 2200 1900 1600 1300 1000 700 400 REFERENCE LOAD CURRENT (µA) 5 60 MAX8524 toc13 MAX8524 toc12 2.001 40 CLOCK FREQUENCY vs. ROSC CLOCK FREQUENCY (kHz) REFERENCE VOLTAGE (V) 2.002 20 TEMPERATURE (°C) REFERENCE VOLTAGE LOAD REGULATION FREQUENCY (MHz) MAX8524/MAX8525 2- to 8-Phase VRM 10/9.1 PWM Controllers with Precise Current Sharing and Fast Voltage Positioning 0 -40 -20 0 20 40 60 80 100 120 TEMPERATURE (°C) _______________________________________________________________________________________ 100 120 2- to 8-Phase VRM 10/9.1 PWM Controllers with Precise Current Sharing and Fast Voltage Positioning INTERLEAVED 8-PHASE OPERATION: LX WAVEFORMS 8-PHASE OPERATION: DYNAMIC VID RESPONSE 8-PHASE ACTIVE CURRENT SHARING MAX8524 toc16 SLAVE PH1 SLAVE PH2 SLAVE PH3 20 INDUCTOR CURRENT (A) MASTER PH4 MAX8524 toc17 MASTER PH2 MASTER PH3 MAX8524 toc18 25 MASTER PH1 POWERGOOD OUTPUT 15 PHASE 1 INDUCTOR CURRENT 10A/div 10 5 OUTPUT VOLTAGE 200mV/div SLAVE PH4 0 0.193 1µs 26 52 77 101 126 150 40µs LOAD CURRENT (A) Pin Description PIN NAME FUNCTION MAX8524 MAX8525 1 1 PWM3 2 2 PWM1 PWM Signal Output for Phase 1. Logic low during shutdown Positive Input of the Output Current Sense of Phase 1. Connect to the inductor side of the output current-sense resistor. PWM Signal Output for Phase 3. Logic low during shutdown. 3 3 CS1+ 4 4 CS1_3- 5 5 CS3+ 6 6 VCC IC Supply Input. Bypass to GND with a ceramic capacitor of at least 1µF. 7 7 GND IC Ground. Single connection to system ground. Common Negative Input of the Output Current Sense of Phases 1 and 3. Connect to the load side of the output current-sense resistors. Positive Input of the Output Current Sense of Phase 3. Connect to the inductor side of the output current-sense resistor. Error-Amplifier Output. Connect to a tap in a resistor-divider from REF to GND to set the finite DC gain for active voltage positioning. Add a series RC network from COMP to GND to compensate the control loop. For 6- or 8-phase operation, connect COMP pins of two controllers together for active current sharing. 8 8 COMP 9 9 REF 2.0V ±0.4% Reference Output. Bypass REF to GND with a ≤2.2µF low-ESR capacitor. REF can source 0.5mA for external loads. REF is alive when EN is low if VCC is above UVLO. 10 10 ILIM Output Current-Limit Set. Connect to a tap of a resistor-divider from REF to GND to set the cycle-by-cycle average current-limit threshold. Current limit (per phase) = VILIM / (50 x RSENSE). Connect to VCC to set the default 20mV current-limit threshold. 11 11 OSC Internal Clock Oscillator Frequency-Set Input. Connect a resistor from OSC to GND to set the switching frequency. OSC must be connected to an external resistor even if the IC is used in slave mode. This pin is operational in shutdown if VCC is above UVLO. 12 12 PWRGD Open-Drain Power-Good Indicator. PWRGD pulls low until the output voltage is in regulation. PWRGD is low in shutdown and during UVLO. _______________________________________________________________________________________ 9 MAX8524/MAX8525 Typical Operating Characteristics (continued) (VIN = 12V, VOUT = 1.2V, IOUT_MAX = 80A, fSW = 250kHz, TA = +25°C, unless otherwise noted.) MAX8524/MAX8525 2- to 8-Phase VRM 10/9.1 PWM Controllers with Precise Current Sharing and Fast Voltage Positioning Pin Description (continued) PIN MAX8524 13 MAX8525 13 NAME FUNCTION CLKO Clock Synchronization Output for Master-Mode Operation. Connect CLKO of the master controller to CLKI of the slave controller. CLKO is active when EN is low, if VCC is above UVLO to permit synchronized slave startup. CLKO is connected to the internal oscillator in both master and slave mode. Clock Synchronization Input. Connect CLKI to CLKO of the master controller for interleaved dual controller systems or to an external synchronization clock. Internal 100kΩ pulldown to GND permits floating this pin. See the Paralleling Operation section for detailed clocking operation. 14 14 CLKI 15–19 16–19 VID0–VID4 — 15 VID5 DAC Code Input. The MAX8525 requires an external pullup resistor. Connect to VCC for the MAX8524. 20 — N.C. No Connection DAC Code Input. The MAX8524 has a 15kΩ internal pullup resistor to VCC. The MAX8525 requires an external pullup resistor. EN Enable Input, Active High. Pulls up to VCC through an internal 100kΩ resistor when UVLO is satisfied. Pull low with an external open-drain or open-collector input to shut down the controller. For master/slave operation, the EN pins of the MAX8524/MAX8525 controllers should be connected together. 22 RS- Output-Voltage Remote-Sense, Negative Input. Connect to GND directly at the load. 23 RS+ Output-Voltage Remote-Sense, Positive Input. Connect to VOUT+ directly at the load. 24 24 CS2+ 25 25 CS2_4- 26 26 CS4+ Positive Input of the Output Current Sense of Phase 4. Connect to the inductor side of the output current-sense resistor. Short CS4+ to CS2_4- for 2-, 3-, or 6-phase operation. 27 27 PWM4 PWM Signal Output for Phase 4. Connect this pin to VCC for 2-, 3-, or 6-phase operation. Logic low during shutdown. 28 28 PWM2 PWM Signal Output for Phase 2. Connect this pin to VCC for 2-phase operation. Logic low during shutdown. 21 21 22 23 Positive Input of the Output Current Sense of Phase 2. Connect to the inductor side of the output current-sense resistor. Short CS4+ to CS2_4- for 2-phase operation. Common Negative Input of the Output Current Sense of Phases 2 and 4. Connect to the load side of the output current-sense resistors. Detailed Description The MAX8524/MAX8525 are synchronous, scalable 2-/ 3-/4-phase, current-mode, step-down controllers. The MAX8524/MAX8525 can be used to implement either an embedded VRD design or a voltage regulator module (VRM) design with external MOSFET driver, such as the MAX8523. The switching frequency of each phase can be set from 150kHz to 1.2MHz, permitting control bandwidth of up to 200kHz. The 5MHz gain-bandwidth product of the voltage-error amplifier ensures sufficient loop gain for most applications. In VRM applications, current bal10 ance between modules is within 5% at full load, maximizing the benefits of multiphase operation. Lossless inductor current sensing with temperature compensation can be used to reduce power dissipation while maintaining droop accuracy. The MAX8524/MAX8525 controllers can be configured for 3-phase or 2-phase VRD or VRM applications by connecting one or two PWM pin(s) to the logic-supply pin (VCC). In these modes, internal phasing is automatically adjusted for optimal ripple cancellation. The CLKI (clock in) and CLKO (clock out) features provided by the MAX8524/MAX8525 permit true 6- or 8-phase interleaved operation when two MAX8524/MAX8525 con- ______________________________________________________________________________________ 2- to 8-Phase VRM 10/9.1 PWM Controllers with Precise Current Sharing and Fast Voltage Positioning MAX8524/MAX8525 Table 1. VID Programmed Output Voltage (VRM 10.0) VID5 VID4 VID3 VID2 VID1 VID0 VOUT VID5 VID4 VID3 VID2 VID1 VID0 VOUT 0 0 1 0 1 0 0.8375 0 1 1 0 1 0 1.2125 1 0 1 0 0 1 0.8500 1 1 1 0 0 1 1.2250 0 0 1 0 0 1 0.8625 0 1 1 0 0 1 1.2375 1 0 1 0 0 0 0.8750 1 1 1 0 0 0 1.2500 0 0 1 0 0 0 0.8875 0 1 1 0 0 0 1.2625 1 0 0 1 1 1 0.9000 1 1 0 1 1 1 1.2750 0 0 0 1 1 1 0.9125 0 1 0 1 1 1 1.2875 1 0 0 1 1 0 0.9250 1 1 0 1 1 0 1.3000 0 0 0 1 1 0 0.9375 0 1 0 1 1 0 1.3125 1 0 0 1 0 1 0.9500 1 1 0 1 0 1 1.3250 0 0 0 1 0 1 0.9625 0 1 0 1 0 1 1.3375 1 0 0 1 0 0 0.9750 1 1 0 1 0 0 1.3500 0 0 0 1 0 0 0.9875 0 1 0 1 0 0 1.3625 1 0 0 0 1 1 1.0000 1 1 0 0 1 1 1.3750 0 0 0 0 1 1 1.0125 0 1 0 0 1 1 1.3875 1 0 0 0 1 0 1.0250 1 1 0 0 1 0 1.4000 0 0 0 0 1 0 1.0375 0 1 0 0 1 0 1.4125 1 0 0 0 0 1 1.0500 1 1 0 0 0 1 1.4250 0 0 0 0 0 1 1.0625 0 1 0 0 0 1 1.4375 1 0 0 0 0 0 1.0750 1 1 0 0 0 0 1.4500 0 0 0 0 0 0 1.0875 0 1 0 0 0 0 1.4625 1 1 1 1 1 1 OFF 1 0 1 1 1 1 1.4750 0 1 1 1 1 1 OFF 0 0 1 1 1 1 1.4875 1 1 1 1 1 0 1.1000 1 0 1 1 1 0 1.5000 0 1 1 1 1 0 1.1125 0 0 1 1 1 0 1.5125 1 1 1 1 0 1 1.1250 1 0 1 1 0 1 1.5250 0 1 1 1 0 1 1.1375 0 0 1 1 0 1 1.5375 1 1 1 1 0 0 1.1500 1 0 1 1 0 0 1.5500 0 1 1 1 0 0 1.1625 0 0 1 1 0 0 1.5625 1 1 1 0 1 1 1.1750 1 0 1 0 1 1 1.5750 0 1 1 0 1 1 1.1875 0 0 1 0 1 1 1.5875 1 1 1 0 1 0 1.2000 1 0 1 0 1 0 1.5875 trollers are utilized, further reducing input and output ripple current. In 4-phase operation, the effective switching frequency is 0.6MHz to 4.8MHz. For 8-phase operation, the effective switching frequency is 1.2MHz to 9.6MHz. The MAX8525 includes a 6-bit DAC (Intel VRM 10.0 compliant) and the MAX8524 includes a 5-bit DAC (Intel VRM 9.1 compliant), both able to achieve ±0.4% initial voltage accuracy. The power-good signal is accurate during VID code changes for the MAX8525 to avoid any fault signal due to the output voltage change requested by the CPU. The MAX8524/MAX8525 also include programmable no-load offset and output-voltage positioning to adjust the output voltage as a function of the output current. ______________________________________________________________________________________ 11 MAX8524/MAX8525 2- to 8-Phase VRM 10/9.1 PWM Controllers with Precise Current Sharing and Fast Voltage Positioning Table 2. VID Programmed Output Voltage (VRM 9.1) Table 3. Clock Frequency Setting vs. Switching Frequency and Number of Phases VID4 VID3 VID2 VID1 VID0 VOUT 0 0 0 0 0 1.850 NO. OF PHASES 0 0 0 0 1 1.825 0 0 0 1 0 1.800 0 0 0 1 1 0 0 1 0 0 0 1 0 0 0 0 0 0 PIN CONNECTIONS fCLKO 2 PWM2 = PWM4 = VCC 4 x fSW 3 PWM4 = VCC 3 x fSW 1.775 4 — 4 x fSW 0 1.750 6 PWM4 = VCC 3 x fSW 0 1 1.725 8 — 4 x fSW 1 1 0 1.700 1 1 1 1.675 1 0 0 0 1.650 1 0 0 1 1.625 0 1 0 1 0 1.600 0 1 0 1 1 1.575 0 1 1 0 0 1.550 0 1 1 0 1 1.525 0 1 1 1 0 1.500 0 1 1 1 1 1.475 1 0 0 0 0 1.450 1 0 0 0 1 1.425 1 0 0 1 0 1.400 1 0 0 1 1 1.375 1 0 1 0 0 1.350 Output Current Sensing (CS_+, CS_-) 1 0 1 0 1 1.325 1 0 1 1 0 1.300 1 0 1 1 1 1.275 1 1 0 0 0 1.250 1 1 0 0 1 1.225 1 1 0 1 0 1.200 1 1 0 1 1 1.175 1 1 1 0 0 1.150 1 1 1 0 1 1.125 1 1 1 1 0 1.100 1 1 1 1 1 Shutdown The output current of each phase is sensed differentially with a shared common return for each phase pair. A low offset voltage and high-gain (50V/V) differential current amplifier at each phase allow low-resistance current-sense resistors to be used to minimize power dissipation. Sensing the current at the output of each phase offers advantages, including less noise sensitivity, more accurate current sharing between phases, and the flexibility of using either a current-sense resistor or the DC resistance of the output inductor. Using the DC resistance, RDC, of the output inductor allows higher efficiency. In this configuration, the initial tolerance and temperature coefficient of RDC must be accounted for in the output-voltage droop-error budget. An RC filtering network is needed to extract the current information from the output inductor, as shown in Figure 1. The time constant of the RC network is governed by equation 1: Clock Frequency (OSC) The clock frequency of the MAX8524/MAX8525 is set by an external resistor from OSC to ground. After selecting the switching frequency per phase, fSW, and the number of phases, using Table 3, select the clock frequency. For 6- or 8-phase operation, connect an external resistor to OSC of both master and slave controllers even if the MAX8524/MAX8525 is operated in 12 slave mode. A 1% resistor is recommended for the ROSC to maintain good frequency accuracy, and ROSC should be placed as close as possible to the OSC pin. Voltage Reference (REF) A precision 2V reference is provided by the MAX8524/MAX8525 at the REF pin. REF is capable of sourcing up to 500µA for external loads. REF stays alive when EN is low and while VCC is above UVLO. Connect a 0.22µF ceramic capacitor from REF to GND. The capacitor should be placed as close to the REF pin as possible. An internal REFOK monitors the reference voltage. The reference voltage must be above the REFOK threshold of 1.85V to activate the controller. The controller is disabled if the reference voltage falls below 1.81V. RC = L RDC ______________________________________________________________________________________ (Eq 1) 2- to 8-Phase VRM 10/9.1 PWM Controllers with Precise Current Sharing and Fast Voltage Positioning IOUT C= VRDC = RDC x IOUT CS_+ (Eq 2) where ESL is the equivalent series inductance of the current-sense resistor, RS is the value of the currentsense resistor, and C is the value of the compensation capacitor. For example, a 1mΩ 2025-package sense resistor has an ESL of 1.6nH. C R ESL RS × R CS_- RDC IS THE INDUCTOR DC RESISTANCE. Output Current-Limit and Short-Circuit Protection (ILIM) Figure 1. Inductor RDC Current Sense RS ESL IOUT VRS = RS x IOUT C R CS_+ CS_- ESL IS THE PARASITIC INDUCTANCE OF PRECISION CURRENT-SENSE RESISTOR. Figure 2. Current-Sense Resistor where L is the inductance of the output inductor. For 20A or higher current-per-phase applications, the DC resistance of commercially available inductors is about 1mΩ, as shown in Table 4. To minimize current-sense error due to the bias current at current-sense pins, choose R less than 2kΩ (Figure 1). Determine the value for C from equation 1. Choose the capacitor with 5% tolerance and the resistor with 1% tolerance. Temperature compensation is recommended for this current-sense scheme. See the Loop Compensation and Output-Voltage Positioning section for detailed information. When a current-sense resistor is used for more accurate output-voltage positioning, similar RC filtering circuits should be used to cancel the equivalent series inductance of the current-sense resistor, as shown in Figure 2. Using criteria similar to that stated in the previous paragraph, the value of C can be determined by equation 2: The MAX8524/MAX8525 provide a cycle-by-cycle current limit to control the average output current as programmed by the user at the ILIM pin. This approach is insensitive to input-voltage variation and inductor tolerance. Once the current-limit threshold is exceeded, the duty cycle is terminated immediately and the output inductor current starts to ramp down. At the next switching cycle, the PWM pulse is skipped if the output inductor current is still above the current-limit threshold. The current-limit threshold is adjustable over a wide range by connecting a resistor-divider from the REF pin to GND with the center tap connected to ILIM. Connecting ILIM to VCC sets the default current threshold to 20mV at the current-sense resistor. The MAX8524/MAX8525 offer current foldback protection under soft-start and overload conditions. This feature allows the VRM to safely operate under short-circuit conditions and to automatically recover once the short-circuit condition is removed. Once the output voltage falls below the low PWRGD threshold, the foldback current threshold is set to half the currentlimit threshold. Output Voltage Differential Sensing (RS+, RS-) The MAX8524/MAX8525 feature differential output-voltage sensing to achieve the highest possible output accuracy. This allows the controllers to sense the actual voltage at the load, so the controller can compensate for losses in the power output and ground lines. Table 4. Output Inductor List MANUFACTURER AND PART NO. BI Technologies HM73-40R50 0.5µH/50A Panasonic ETQP1H0R6BFA 0.6µH/30A Sumida CDEP149(H) 0.45µH/32A Coiltronics HC2-0R68 0.68µH/50A RDC (mΩ) 0.78 (typ) 1.0 (max) 0.9 (max) 0.9 (typ) 1.1 (max) 0.6 (max) ______________________________________________________________________________________ 13 MAX8524/MAX8525 RDC L MAX8524/MAX8525 2- to 8-Phase VRM 10/9.1 PWM Controllers with Precise Current Sharing and Fast Voltage Positioning TO POSITIVE OUTPUT OF VRM R1 50Ω MAX8524/ MAX8525 R3 100Ω RS+ TO REMOTE-SENSE LOCATION R4 100Ω RSR2 50Ω C1 470pF C1 470pF TO POWER GROUND OF VRM Figure 3. Recommended Filtering for Output-Voltage Remote Sensing Traces from the load point back to RS+ and RS- should be routed close to each other and as far away as possible from noise sources (such as inductors and high di/dt traces). Use a ground plane to shield the remotesense traces from noise sources. To filter out commonmode noise, RC filtering is recommended for these pins as shown in Figure 3. For VRD applications, a 100Ω resistor with a 470pF capacitor should be used. For VRM applications, additional 50Ω resistors should be connected from these pins to the local outputs of the converter before the VRM connector. This avoids excessive voltage at the CPU in case the remote-sense connections get disconnected. Loop Compensation (COMP) During a load transient, the output voltage instantly changes due to the ESR of the output capacitors by an amount equal to their ESR times the change in load current (∆VOUT = -RESR_CO x ∆ILOAD). The voltagepositioning method allows better utilization of the output regulation window, resulting in fewer output capacitors. The MAX8524/MAX8525 employ rapid-active average scheme, a proprietary current-mode architecture that adjusts the output current based on instantaneous output voltage, resulting in fast voltage positioning. The voltage-error amplifier consists of a high bandwidth and high-accuracy transconductance amplifier (GMV). See the Functional Diagram. The negative input of the transconductance amplifier is connected to the output of the remote-voltage differential amplifier, and the positive input is connected to the output of an internal DAC controlled by VID inputs. The DC gain of the transconductance amplifier is set to a finite value to achieve fast output-voltage positioning by connecting an equivalent 14 resistor, RE, from the COMP pin to GND (RE = RU//RB). The value of RE is determined by the amount of droop required at full load, which is specified as the output impedance or the load line in Intel VRM specifications. According to the Intel VRM specifications, the output voltage at no load cannot exceed the voltage specified by the VID code, including the initial set tolerance, ripple voltage, and other errors. Therefore, the actual output voltage should be biased lower to compensate for these errors. Connect a resistor-divider, RU and RB, from REF to GND, with the tap connected to COMP, to set the offset voltage. For 6- or 8-phase operations, connect COMP pins of the two controllers together for active current sharing. Dynamic VID Change (MAX8525 Only) The MAX8525 offers the ability to dynamically change the VID inputs while the controller is operating (on-thefly, or OTF). This feature allows the processor to adjust its core voltage in a 250mV window. The MAX8525 output voltage changes in 12.5mV steps when a VID change is detected. The VID inputs of the MAX8525 comply with Intel’s 400ns logic-skew timing specifications to prevent false code changes. Once the timer expires, the controller starts to change the DAC output. Figure 4 shows the output voltage step during a VID OTF event. The MAX8525 controller accepts both step-by-step changes of VID inputs or all-at-once VID inputs changes. For all-at-once VID input changes, the output-voltage slew rate is the same as 12.5mV per step and 2µs duration. Paralleling Operation (CLKI and CLKO) Two MAX8524/MAX8525s can be connected together to generate 6-phase or 8-phase core supplies. In this configuration, one MAX8524/MAX8525 serves as a master and the other serves as a slave. Connect the CLKI pin of the slave controller to the CLKO pin of the master controller. Interleaved operation is achieved by synchronizing the master controller to the CLKO rising edge and the slave controller to the CLKO falling edge. Figure 5 shows the clock timing between the phases of both master and slave controllers. 2-Phase and 3-Phase Operation Selection (PWM3 and PWM4) The MAX8524/MAX8525 can operate in 2-, 3-, and 4-phase operation. Connect PWM4 to VCC for 2-, 3-, or 6-phase operation. Also connect PWM2 to VCC for 2-phase operation. All PWM outputs are held low during shutdown. ______________________________________________________________________________________ 2- to 8-Phase VRM 10/9.1 PWM Controllers with Precise Current Sharing and Fast Voltage Positioning POWER-GOOD OUTPUT INDUCTOR CURRENT OF PH1 OUTPUT VOLTAGE 0.2V/div 40µs Figure 4. Output-Voltage Waveform During VID On-the-Fly Change with Load Transients EIGHT-PHASE OPERATION MASTER IC PHASE CLOCK PWRGD is an open-drain output that is pulled low when the output voltage rises above the PWRGD upper threshold or falls below the PWRGD falling threshold. PWRGD is held low in shutdown, VCC < UVLO, and during soft-start conditions. For logic-level output voltages, connect an external pullup resistor between PWRGD and the logic power supply. A 100kΩ resistor works well in most applications. UVLO, Output Enable (EN), and Soft-Start When the IC supply voltage (V CC ) is less than the UVLO threshold, all PWM outputs are held low and most internal circuitry is shut down to reduce the quiescent current. When EN is released and VCC > UVLO, the internal 100kΩ resistor pulls EN to VCC and softstart is initiated. During soft-start, the output of the internal DAC ramps up at 12.5mV per step. For 6- or 8-phase operation, connect EN of two MAX8524/ MAX8525s together and drive it by an open-drain signal, as shown in Figure 6. Output Overvoltage Protection (OVP) When the output voltage exceeds the regulation voltage by 225mV for the MAX8524 or 200mV for the MAX8525, all PWM outputs are pulled low and the controller is latched off. To discharge the output voltage, the MOSFET drivers must keep the low-side MOSFETs on and high-side MOSFETs off. The MAX8523 dualphase and the MAX8552 single-phase MOSFET drivers fulfill this requirement. The latch condition can only be cleared by cycling the input voltage (VCC). CLKOUT PHASE 1 PHASE 2 PHASE 3 PHASE 4 Thermal Protection SLAVE IC PHASE CLOCK CLKIN PHASE 1 The MAX8524/MAX8525 feature a thermal-fault-protection circuit. When the junction temperature rises above +150°C, an internal thermal sensor activates the shutdown circuit to hold all PWM outputs low to disable switching. The thermal sensor reactivates the controller after the junction temperature cools by 15°C. Design Procedure PHASE 2 Setting the Switching Frequency PHASE 3 PHASE 4 Figure 5. Clock Relationships Between the Master and Slave Controllers The switching frequency determines the switching loss and the size of the power components. Higher switching frequency results in smaller external components and more compact design. However, switching loss and magnetic core loss are directly proportional to the switching frequency. Select a switching frequency as a tradeoff of the efficiency and size. The clock frequency can be selected from Table 3. ______________________________________________________________________________________ 15 MAX8524/MAX8525 Power-Good Output (PWRGD) MAX8524 fig04 MAX8524/MAX8525 2- to 8-Phase VRM 10/9.1 PWM Controllers with Precise Current Sharing and Fast Voltage Positioning VID0 VID1 VID2 VID3 VID4 VID5 VID0 INPUT VID1 INPUT VID2 INPUT VID3 INPUT VID4 INPUT VID5 INPUT VID0 VID1 VID2 VID3 VID4 VID5 CLKI REF MASTER CLKO REF REMOTE-SENSE INPUT MAX8524/ MAX8525 RS+ RS- SLAVE MAX8524/ MAX8525 RS+ COMP COMP RS- EN EN EN INPUT Figure 6. Master and Slave Controller Connections See the Clock Frequency vs. ROSC graph in the Typical Operating Characteristics section for the relationship between the clock frequency and the value of the frequency-setting resistor, ROSC. The value of ROSC for a given clock frequency can also be approximated from equation 3: ROSC = 277.704 × fOSC(MHz)-1.197 kΩ (Eq 3) VRIPPLE = Output Inductor Selection Output inductance is set by the desired amount of inductor current ripple (LIR) and the slew rate of the inductor current during a load transient. A larger inductance value minimizes output ripple current and increases efficiency but slows down the current slew rate. For the best tradeoff of size, cost, and efficiency, an LIR of 30% to 60% is recommended (LIR = 0.3 to 0.6). Choose LIR close to the high end when more phases are used. The inductor value is determined from: L≥ 16 VOUT × (1 − D) × N H LIR × fSW × IOUT _ MAX where fSW is the switching frequency, IOUT_MAX is the maximum-rated output current, D is the duty ratio, and VOUT is the output voltage at a given VID code. Check the output-inductance ripple current for the ripple voltage it produces across the output capacitor ESR. For an n-phase VRM converter, the output ripple voltage, VRIPPLE, can be calculated using: (Eq 4) VOUT × RESR _ CO × (1 − (N × D)) fSW × L (Eq 5) For ripple voltage estimate, it is safe to replace RESR_CO with RO, the VRM output impedance. If the output ripple voltage is not satisfied, a larger value of output inductance should be chosen. The selected inductor should have the lowest possible DC resistance and the saturation current should be greater than the peak inductor current, IPEAK. IPEAK is found from: IPEAK = IOUT _ MAX (2 + LIR) 2 × N (Eq 6) When the DC resistance of the output inductor is used for current sensing, the range of DC resistances is limited by the following constraints: ______________________________________________________________________________________ 2- to 8-Phase VRM 10/9.1 PWM Controllers with Precise Current Sharing and Fast Voltage Positioning 5 × N 50 × IOUT _ MAX × (2 + LIR) (Eq 7) and RDC ≥ N 50 × IOUT _ MAX × (2 + LIR) (Eq 8) Output Capacitor Selection In most cases, selection of the output capacitor is dictated by the ESR requirement to meet the core-supply transient responses. The target equivalent series resistance is RESR_CO = RO. The minimum output capacitance, CO(min), based on the energy balance, is then calculated from: CO (min) ≥ L × IOUT _ MAX 1 × 2 N × RO × VOUT (Eq 9) There is also an upper limit on the amount of output capacitance to meet the OTF VID change requirement. Too much output capacitance may prevent the output voltage from reaching the new VID output voltage within the OTF time window: CO (max) ≤ (ILIM - IOUT _ MAX )2 × t OTF VOTF (Eq 10) where tOTF is the time window to reach VOTF, the OTF voltage steps. If CO(max) is less than CO(min), the system does not meet the VID OTF specification. Combinations of different types of capacitors, such as SPCAPs, POSCAPs, or low-ESR aluminum electrolytic capacitors may be needed to achieve the required RESR_CO and the output capacitance simultaneously. If the combination cannot be reached, the output inductance must be adjusted. Input Capacitor Selection The input capacitor reduces the peak current drawn from the power source and reduces the noise and voltage ripple on the input caused by the circuit’s switching. The input capacitors must meet the ripple current requirement, IRMS, imposed by the switching currents as defined by equation 11: IRMS = D × IOUT _ MAX × 1 -1 N× D (Eq 11) Use the minimum input voltage to calculate the input ripple current. Low-ESR capacitors, such as low-ESR aluminum electrolytic capacitors, polymer capacitors, and ceramic capacitors, should be used to avoid large voltage transients at the input during a large step load change at the output. The capacitors’ ripple-current specifications provided by the manufacturer should be carefully reviewed. Additional small-value low-ESL ceramic capacitors (1µF to 10µF/16V) can be used in parallel to reduce the high-frequency ringing. Power MOSFET Selection MOSFET power dissipation depends on the gate-drive voltage (VG), the on-resistance (RDSON), the total gate charge (QGT), and the gate threshold voltage (VTH). The supply voltage range for MOSFET drivers (MAX8523) is from 4.5V to 6.5V. With VGATE < 10V, logic-level threshold MOSFETs are recommended. Power dissipation in the high-side MOSFET consists of two parts: the conduction loss and the switching loss. The conduction loss for each high-side switch can be calculated from equation 12: PCOND _ HS = D × × I2OUT _ MAX 2 N2 RDSON _ HS LIR2 × 1 + 12 (Eq 12) MHS where MHS is the number of MOSFETs in parallel for each high-side switch. Total high-side conduction loss equals the number of phases times PCOND_HS. Switching loss is the major contributor to the high-side MOSFET power dissipation due to the hard switching transition every time it turns on. The switching loss can be found from the following: PSW _ HS = 2 × VIN × IOUT _ MAX N × fSW × MHS × RGATE × QMILLER VD − VTH (Eq 13) where VD is the gate-drive voltage and RG is the total gate resistance including the driver’s on-resistance from the MAX8523 (0.8Ω) and the MOSFET’s gate resistance. QMILLER is the MOSFET’s Miller charge, which can be found in the MOSFET’s data sheet. For a logic-level power MOSFET, the gate resistance is about 2Ω. Note that adding more MOSFETs in parallel at the high-side switch increases the switching loss. Smaller gate charge and lower gate resistance usually result in lower switching loss. The low-side MOSFET power dissipation is mostly attributed to the conduction loss. Switching loss is negligible due to the zero voltage switching at turn-on and body diode clamp at turn-off. Power dissipation in the ______________________________________________________________________________________ 17 MAX8524/MAX8525 RDC ≤ MAX8524/MAX8525 2- to 8-Phase VRM 10/9.1 PWM Controllers with Precise Current Sharing and Fast Voltage Positioning low-side MOSFETs of each phase can be calculated from the following equation: I2OUT _ MAX 2 PCOND _ LS = (1- D) × × N2 RDSON _ LS MLS LIR2 × 1 + 12 (Eq 14) where RDSON_LS is the on-resistance of the low-side MOSFET and MLS is the number of MOSFETs in parallel for the low-side switch. Total power dissipation for the low-side switches equals the number of phases times the low-side conduction loss of each phase. Even though the switching loss is insignificant in the low-side MOSFETs, RDSON is not the only parameter that should be considered in selecting the low-side MOSFET. Large Miller capacitance (CRSS) could turn on the low-side MOSFETs momentarily when the drain-to-source voltage goes high at fast slewing rates if the driver cannot hold the gate low. The ratio of C RSS/CISS should be less than 1/10th for the low-side MOSFETs to avoid shoot-through current due to momentary turn on of the low-side switch. The gate-driver power dissipation is also important. The MAX8523 is a 0.8Ω/0.6Ω dual-channel driver, whereas the MAX8552 is a 0.8Ω/0.6Ω single-channel driver. Power dissipation in each driver is given by: 2 × fSW × (MLS × QG _ LS + PDRIVER = VD × (Eq 15) MHS × QG _ HS ) + ICC where I CC is the supply current of the MAX8523. Ensure the power loss does not exceed the package power dissipation. Loop Compensation and Output-Voltage Positioning Once the current-sense resistance (RSENSE), the output impedance (RO), and the output offset voltage (VOS) are known, the values of RU and RB are calculated from equations 16 and 17: 1 (Eq 16) RU = GM NRO V OS 2 RSENSE × 50 B= 18 1 GM 2 where GM is the transconductance (2ms). A capacitor, CC, must be connected from COMP to ground to roll off the gain at high frequency. The capacitor value can be found from the following equation once the output capacitor’s ESR zero frequency is known to obtain firstorder rolloff at zero across frequency: NRO 1 + VOS 6 × R 50 SENSE 20 × 10 CC = RESR _ CO × CO (Eq 18) RE where RESR_CO is the total equivalent series resistance and CO is the total capacitance of the output capacitors, respectively. RE is the parallel equivalent resistance of RU and RB. Setting the Current Limit Current-limit threshold sets the maximum available output DC current. To meet the OTF operation, the output current limit, ILIM, should be set at least 15% higher than the maximum rated output current, IOUT_MAX. The voltage at ILIM and the value of the current-sense resistor or the DC resistance of the output inductors set the current-limit threshold: I VILIM = 50 × RSENSE × LIM N (Eq 19) for the resistor current sensing and: I VILIM = 50 × RDC × LIM N (Eq 20) for DC resistance of the output inductor current sensing. In equation 22, the value of RDC at the high ambient temperature must be used to guarantee the rated output current. VILIM can be set by connecting ILIM to a resistor-divider from REF to GND. Select resistors R26 and R27 from the schematics in Figure 7 so the current through the divider is at least 10µA: R26 + R27 ≤ 200kΩ (Eq 21) A typical value for R27 is 100kΩ; then solve for R26 using: R26 = R27 × 2 - VILIM VILIM (Eq 17) ______________________________________________________________________________________ (Eq 22) 2- to 8-Phase VRM 10/9.1 PWM Controllers with Precise Current Sharing and Fast Voltage Positioning PC Board Layout Guidelines A properly designed PC board layout is important in any switching DC-DC converter circuit. If possible, mount the MOSFETs, inductors, input/output capacitors, and current-sense resistor on the top side of the PC board. Connect the ground for these devices close together on a power ground plane. Make all other ground connections to a separate analog ground plane. Connect the analog ground plane to power ground at a single point. To help dissipate heat, place high-power components (MOSFETs and inductors) on a large PC board area, or use a heat sink. Keep high-current traces short, wide, and tightly coupled to reduce trace inductances and resistances. Also, make the gate-drive connections (DH_ and DL_) short, wide, and tightly coupled to reduce EMI and ringing induced by high-frequency gate currents. Use Kelvin-sense connections for the current-sense resistors. All signal traces of the current sense and the remote-voltage sense should be tightly coupled and as far away as possible from the inductors and other switching noise sources. Use the ground plane to shield the current-sense traces and the feedback from noise sources. Place the REF capacitor, the VCC capacitor, the currentsense decoupling capacitors, and the remote-sense decoupling capacitors as close to the MAX8524/ MAX8525 as possible. For an example PC board layout, refer to the MAX8525 evaluation kit. Chip Information TRANSISTOR COUNT: 9021 PROCESS: BiCMOS Pin Configurations (continued) TOP VIEW PWM3 1 28 PWM2 PWM1 2 27 PWM4 CS1+ 3 26 CS4+ CS1_3- 4 25 CS2_4- CS3+ 5 VCC 6 24 CS2+ MAX8524 GND 7 23 RS+ 22 RS- COMP 8 21 EN REF 9 20 N.C. ILIM 10 19 VID4 OSC 11 18 VID3 PWRGD 12 17 VID2 CLKO 13 16 VID1 CLKI 14 15 VID0 QSOP ______________________________________________________________________________________ 19 MAX8524/MAX8525 Applications Information 20 J1–11 V0_SEN- J1–52 V0_SEN+ R18 50Ω R19 50Ω J1–53 OUTEN C23 680pF R29 6.81kΩ J1–10 VCC-PWRGD VOUT R24 28.7kΩ R25 5.11kΩ ______________________________________________________________________________________ R23 200kΩ C26 470pF 11 22 23 C25 470pF 21 7 9 8 12 6 D3 OSC RS- RS+ EN AGND REF COMP PWRGD VCC U1 ILIM 14 16 17 18 19 20 15 1 PWM4 PWM2 CS4+ CS2+ CS2_4CS3+ CS1+ CS1_3- 27 28 4 3 5 25 24 26 CLKO 13 CLKI VID0 VID1 VID2 VID3 VID4 VID5 PWM3 2 2 R5 402Ω R6 1.3kΩ PWM1 R27 10 100kΩ R26 28.3kΩ MAX8525 R18 OPEN REF 1 KA317MR U4 C28 3.3nF CS1_3- CS1+ CS3+ CS2_4- CS2+ CS4+ C29 3.3nF J1–55 J1–8 J1–56 J1–7 J1–54 J1–6 C20 2.2µF C19 2.2µF VDD = 6.5V R15 OPEN C17 0.1µF R17 OPEN R14 10Ω VDD = 6.5V C18 0.1µF R12 10Ω NOTE: C30-C45 SELECTED FOR VRM 10 TRANSIENT RESPONSE SPECIFICATIONS AT 1.2V OR HIGHER OUTPUT. C27 470pF R21 100Ω R20 100Ω C24 0.22µF R22 348Ω R16 100kΩ R28 6.81kΩ C22 1µF 10V R13 10Ω 5% 2 3 1 C21 2.2µF 16V 3 4 PV1 10 9 8 7 13 4 10 9 PWM2 DH1 BST1 U3 12 14 15 16 LX1 3 DH1 2 BST1 1 DL2 LX2 DH2 BST2 5 DL1 6 PG1 11 PG2 3 2 PWM2 PWM1 DLY 15 16 DL2 12 LX2 14 DH2 BST2 5 DL1 VCC MAX8523 6 PG1 PG2 11 PV2 PV1 U2 MAX8523 LX1 PWM1 8 DLY 7 VCC 13 PV2 1 R11 3.3Ω C15 0.22µF R10 3.3Ω 3 R9 3.3Ω C13 0.22µF R8 3.3Ω 3 C16 0.22µF 1 D2 C14 0.22µF 1 D1 2 2 5 5 6 4 6 8 7 8 7 N5 3 2 N4 3 2 8 7 N2 3 2 8 7 N1 3 2 8 7 8 7 8 7 N11 3 2 N10 3 1 2 1 N8 3 2 8 7 N7 3 1 2 1 6 6 6 5 5 4 5 5 4 4 1 1 6 1 1 6 5 6 4 4 4 4 5 5 5 6 4 6 6 8 7 8 7 N6 3 2 N14 3 2 8 7 N3 3 2 8 7 N13 3 2 8 7 8 7 1 R4 24Ω C8 10µF 25V CS2+ R3 24Ω C6 10µF 25V CS3+ R2 24Ω C4 10µF 25V CS1+ R1 24Ω CS4+ L4 0.6µH C7 10µF 25V L3 0.6µH C5 10µF 25V L2 0.6µH C3 10µF 25V L1 0.6µH C2 10µF 25V CS2_4- C12 33nF RS2 1mΩ VIN+ C11 33nF RS1 1mΩ VIN+ C10 33nF R S2 1mΩ VIN+ C9 33nF RS1 1mΩ INPUT 10V TO 13.2V L1–L4: PANASONIC, N1, N4, N7, N10, N13–N16: IRF7811W N2, N3, N5, N6, N8, N9, N11, N12: IRF7822 8 7 N12 3 2 N16 3 1 2 1 N9 3 2 8 7 N15 3 1 2 1 1 6 1 1 6 6 6 5 5 4 5 5 4 4 5 6 4 4 4 4 5 C1 10µF 25V J1–13 J1–15 J1–17 J1–19 J1–21 J1–23 J1–25 J1–27 J1–29 J1–31 J1–32 J1–34 J1–36 J1–38 J1–40 J1–42 J1–44 J1–46 J1–48 VOC40–C45 470µF/6V SPCAPS VO+ J1–14 J1–16 J1–18 J1–20 J1–22 J1–24 J1–26 J1–28 J1–30 J1–33 J1–35 J1–37 J1–39 J1–41 J1–43 J1–45 J1–47 J1–49 J1–50 OUTPUT 0.8375V TO 1.6V, 80A C30–C39 390µF/2V SPCAPS CS1_3- J1–3 J1–2 J1–1 MAX8524/MAX8525 2- to 8-Phase VRM 10/9.1 PWM Controllers with Precise Current Sharing and Fast Voltage Positioning Figure 7. Typical Application Circuit for VRM 10 Using a Sense Resistor for Output Current Sensing and 8-Pin SO MOSFET Packages ______________________________________________________________________________________ V0_SEN- V0_SEN+ R18 50Ω R19 50Ω OUTEN C23 680pF R24 6.8kΩ J1–10 VCC-PWRGD VOUT R15 11.9kΩ R22 29kΩ R16 100kΩ C27 470pF R21 100Ω 11 22 23 C25 470pF 21 7 9 8 12 6 D3 C26 470pF R23 95kΩ C24 0.22µF R20 100Ω C22 1µF 10V R13 10Ω 5% 2 3 1 OSC RS- RS+ EN AGND REF COMP PWRGD VCC U1 R5 249Ω 2 14 16 17 18 19 20 15 1 PWM4 PWM2 CS4+ CS2+ CS2_4CS3+ CS1+ CS1_3- 27 28 4 3 5 25 24 26 CLKO 13 CLKI VID0 VID1 VID2 VID3 VID4 VID5 PWM3 2 R6 1.02kΩ PWM1 1 KA317MR U4 R27 27kΩ R26 10kΩ 10 ILIM REF MAX8525 R18 OPEN 3 C28 0.015µF CS1_3- CS1+ CS3+ C19 2.2µF VDD = 6.5V CS2_4- CS2+ CS4+ C29 0.015µF C20 2.2µF C17 0.1µF R14 10Ω VDD = 6.5V C18 0.1µF R12 10Ω VCC 10 9 8 7 13 4 10 9 PWM2 DH1 2 1 U3 12 14 15 16 2 LX1 3 DH1 BST1 1 DL2 LX2 DH2 BST2 5 DL1 6 PG1 11 PG2 PWM2 PWM1 DLY 15 16 DL2 12 LX2 14 DH2 BST2 5 DL1 VCC MAX8523 6 PG1 PG2 11 PV2 PV1 U2 BST1 3 MAX8523 LX1 PWM1 8 DLY 7 13 PV2 4 PV1 3 R11 0Ω C15 0.22µF R10 0Ω R9 0Ω C13 0.22µF R8 0Ω C16 0.22µF 1 D2 C14 0.22µF 1 D1 2 2 CS4+ R4 24Ω L4 0.29µH C8 10µF 25V CS2+ R3 24Ω L3 0.29µH C6 10µF 25V CS3+ R2 24Ω L2 0.29µH C4 10µF 25V CS1+ R1 24Ω L1 0.29µH C2 10µF 25V C12 0.033µF RS4 1mΩ VIN+ C11 0.033µF RS3 1mΩ VIN+ C10 0.033µF R S2 1mΩ CS_4- VIN+ VIN+ C9 0.033µF R S1 1mΩ L1–L4: TDK, SPM12535T-R23M300 N1, N3, N5, N7: IRF7801 N2, N4, N6, N8: 2XIRF7822, EACH N8 N7 C7 10µF 25V N6 N5 C5 10µF 25V N4 N3 C3 10µF 25V N2 N1 C1 10µF 25V C30–C39 330µF/10mΩ SPCAPS VOUT = 80A CS1_3- VO- VO+ MAX8524/MAX8525 C21 2.2µF 16V 3 2- to 8-Phase VRM 10/9.1 PWM Controllers with Precise Current Sharing and Fast Voltage Positioning Figure 8. 600kHz Application Circuit with Direct MOSFETs for Compact VRM 10 Design 21 MAX8524/MAX8525 2- to 8-Phase VRM 10/9.1 PWM Controllers with Precise Current Sharing and Fast Voltage Positioning Functional Diagram SYNC DETECT CLKI UVLO AND VCC REFOK EN 1 100kΩ 0.45MHz TO 4.8MHz CLKO MUX INTERNAL CLOCK div 2/3/4 0 0.9MHz TO 9.6MHz OSCILLATOR OSC div 2 RUN S CURRENT FOLDBACK AND FAULT LOGIC PWRGD PWRGD S/R PWM PWM1 S MAX8524 MAX8525 OVP PWM S/R PWM2 S/R PWM3 S/R PWM4 225mV S SOFT-START REF 2V ±0.4% PWM REF S 7-BIT COUNTER LOAD VID4 VID2 VID1 REF OPERATION MODE DETECT (MAX8525 ONLY) VID5 NO COMP RB GMV 1µs DELAY VID0 RU PWM EQUAL? OFFSET ROM VID3 DAC CS1_3- CC GMC PHASE 1 RSNS1 RCS CS1+ RAPIDACTIVE AVERAGE CURRENT SENSE GMC PHASE 2 CS3+ GMC PHASE 3 RS+ CS2+ RSDA RS- CS2_4CLAMP BUF REF /2 GMC PHASE 4 CS4+ ONE OF FOUR PHASES DEPICTED GND 22 ILIM ______________________________________________________________________________________ 2- to 8-Phase VRM 10/9.1 PWM Controllers with Precise Current Sharing and Fast Voltage Positioning QSOP.EPS PACKAGE OUTLINE, QSOP .150", .025" LEAD PITCH 21-0055 E 1 1 Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________ 23 © 2005 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products, Inc. MAX8524/MAX8525 Package Information (The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to www.maxim-ic.com/packages.)