Advanced Communications ACS406CS Reference Design REFERENCE DESIGN ACS406CS 4 x E1/T1 Reference Design Advanced Communications Revision 1.5 February 2000 4 x E1/T1 Channel Mux/Demux Chip Set over Fiber Optic Cable DESCRIPTION FEATURES · 4 independent E1/T1 channels, configurable via The ACS406CS Reference Design is a full featured 4 x E1/T1 point to point fiber mux/demux including Line Termination transformers and Line Interface Units (LIU) utilising the ACS406CS chip set. switches. · Full diagnostic modes available per channel via switches. · Incorporates Line Termination transformers and LIUs with Line Protection. · Screw termination blocks for twisted pair line terminations. · LEDs to indicate lock status and loss of line signals. · On-board oscillator for 1.544/2.048MHz. · Support for single wavelength Laser Duplex Device. This document contains the circuit description, schematics and BOM for a typical custom application of the ACS406CS chip set with a Quad LIU. A simplified block diagram of the complete system is given in Figure 3. The Reference Design can be configured for either 4 x E1 or 4 x T1 independent channel operation via a Jumper. An on board oscillator is used to generate 1.544/ 2.048MHz. Independent control of the channel diagnostic modes can be selected by switches. · Single 5V supply connection. · Board dimensions 100mm x 90mm. On board LED indicators identify locking conditions and transmission errors in both directions. The board provides terminals for both power and line interface connections. SW2 - + C12 C29 TRANR1 TIN1 RIN1 +C19 1 C11 + R7 E1 DR T1 R18 L1 L2 R16 R17 R19 R25 C13 C14 R26 C25 + TRANR0 TIN0 RIN0 OSC C24 C23 ROU0 PORB ZD MODE1 MODE2 CNTL1 CNTL2 C26 LOP3 LOP2 TRANT0 + ROU1 PWR R35 8 VDD GND ROUT0 TOUT0 1 TRANT1 R24 ACS4060CS REF_DES V1.0 LOP1 LOP0 ROUT1 TOUT1 R8 C28 ACS4060 12 SW1 TRANR2 XTALTRSEL C22 E R1 C1 5 F C3 R4 R32 R13 C6 R34 C7 R37 R33 R36 3 2 R6 R5 C5 R12 C30 R2 C2 R15 ACS9010 C4 R11 R10 R9 TRANT3 ROU3 G C31 R23 TOUT2 ROUT2 ROU2 R14 C10 L3 +C18C17 R31TRANT2 RIN3 TRANR3 TIN3 C15 R22 R20 C21 R21 C16 C20 R29R30 + C9 TIN2 RIN2 R28 C27 LXT334 R27 POL1 POL2 DM1C3 C8 DM2C3 DM1C4 DM2C4 RESEL DM1C2 DM2C2 DM1C1 DM2C1 1 4 RXMON ERRL LOSS TOUT3 ROUT3 LOS1 5 DCD DFM LOS3 LOS2 1 LOS0 BUILD RXFLAG TXFLAG Figure 1: ACS406CS component layout of the reference design (not to scale). 1 without notice. Semtech reserves the right to change specifications on catalog devices © Copyright, Semtech Corp 2000 Advanced Communications ACS406CS Reference Design Printed Circuit Layout Recommendations The circuit diagram and component values contained in the document are recommended for use in any system designed around the ACS406CS chip set. The performance of a fiber optic modem using the ACS406CS chip set is partially dependent on the layout of the printed circuit board containing the recommended components. The most critical layout issues apply to the ACS9010 and the associated external components. We suggest the following guidelines are considered when you lay out your own custom circuit board for the ACS406CS chip set and supporting components described in this User Manual. Gerber plots are available for all the PCB layers from the reference design to assist in the development of a custom PCB design. 2) Use separate power and ground planes. Figure 1. shows the component layout for the ACS406CS reference design. For the full reference PCB layout, please refer to the gerber plots provided separately in the ACS406CS section of the web site. 4) The connections between the ACS9010 drive pins and the optical components (either PPLED or Laser Duplex Device) should be of minimum length. 1) A generous ground plane should be provided, especially surrounding the sensitive PINP and PINN tracks between the ACS9010 pins and the optical component. 3) Minimise the size of cuts or openings in the power and ground planes. 5) Power supply filtering inductors must be used on the VDD (+5V) supply rail. The inductor should be a low resistance type, typically < 1Ω. The ACS406CS Reference Design incorporates outside Line Protection. While not mandatory for normal operation, these protection elements are strongly recommended to improve the line side design robustness. Appropriate Line Protection and Transient Voltage Suppression devices are available from Semtech, part no. LC01-6 or LC04-6 and SRDA05-4 - Semtech Application Note reference AN97-10. See Figure 2. Please refer to the Level One LXT384 data sheet for more details on the Line Protection. 5 Figure 2: Line Protection using Semtech LC01-6 and SRDA05-4. 2 TIN(3:0) RIN(3:0) TRING(3:0) RTIP(3:0) 100 nF RPOS(3:0) RNEG(3:0) RCLK(3:0) TPOS(3:0) TNEG(3:0) TCLK(3:0) TPOS(4:1) TNEG(4:1) TCLK(4:1) RPOS(4:1) RNEG(4:1) RCLK(4:1) ERRL 10nF DCD 1nF RSET2 DVDD 100 nF Tset RxFLG Rset COEF1 TxFLG COEF2 100pF ACS9010 27 Ω Laser LAP LOSS 10nF CTX1 CTX2 PMN LASRX LAN 100nF LASER PINRX PINP 51KΩ Txdat PORB RRING(3:0) 100KΩ VA+ PORB PIN Diode PINN DR1 IREF ENTX TxMN 5KΩ ENRXB ENCOFB RxMN 1MΩ Txdat ENTX ENRXB Rxdat+ XTAL; For E1, 32.768MHz For T1, 30.88MHz 1 1 1 XTO Rxdat+ 22pF XTI 22pF L = 47 µH R < 1Ω 100nF VDD GND L = 47 µH R < 1Ω (VDD)+5V + 100nF (GND) 0V 100 µF VB 100 nF GND VA+ ACS406CS Reference Design DR1 pin selection; For 4 x E1, DR1= VDD For 4 x T1, DR1=GND POL1 POL2 DM1C1 DM1C2 DM1C3 DM1C4 DM2C1 DM2C2 DM2C3 DM2C4 RESEL TRSEL GND 3 LOS0 LOS1 LOS2 LOS3 DFM VA+ TxVDD 100 nF 1KΩ RxVDD 50KΩ 1uF VA+ 100 nF TTIP(3:0) ACS4060 LXT334 VA+ RxGND ROUT(3:0) MCLK Rxdat- TxGND TOUT(3:0) Oscillator Unit SCEXT ECLK VA+ 680 Ω 680 Ω 680 Ω GND VD+ VDD LOP0 LOP1 LOP2 LOP3 CNTL1 CNTL2 MODE2 MODE1 Oscillator Unit; For E1, 2.048MHz For T1, 1.544MHz Figure 3: Simplified schematic comprising the ACS406CS and LXT334 Quad LIU with Laser Duplex Device. VB Advanced Communications VDD 5 Advanced Communications The ACS406CS reference configuration settings. design ACS406CS Reference Design user DR Switch Switch DR is used to configure the ACS4060 for either 4 x E1 or 4 x T1 operation. DR = HIGH, Logic1, ACS4060 configured for 4 x E1 operation; DR = LOW, Logic 0, ACS4060 configured for 4 x T1 operation. The ACS406CS Reference Design does allow some flexibility for input coding type and diagnostic settings. The ACS406CS Reference Design will be supplied pre-setup and tested with the appropriate ACS4060 XTAL (32.768MHz for E1 or 30.88MHz for T1) and LXT334 XTAL (2.048MHz for E1 or 1.544MHz for T1). The ACS406CS Reference Design has two switch banks and a jumper DR. SW1 allows user configuration of the ACS4060 and SW2 allows user configuration of the LXT334 Quad LIU. DR is used to define 4 x E1 or 4 x T1 operation. LED configurations There are LEDs provided for the following signals. For normal operation, the LED status is as follows VDD_PWR = ON ACS4060_ERRL = OFF ACS4060_LOSS = OFF Switch Bank SW1 ACS4060_DCD = ON Switch SW1 is used to configure signals on the ACS4060. SW1 defines the logic levels of signals POL(2:1), DM1C(4:1), DM2C(4:1), RESEL, TRSEL. LXT334_LOS(3:0) = OFF Switch settings HIGH, Logic1 = switch up; LOW, Logic 0 = switch down. On initial power up, ACS4060_LOSS = ON and ACS4060_DCD = OFF. After a short time, ACS4060_LOSS = OFF and ACS4060_DCD = ON. LXT334_DFM = OFF POL(2:1) Switches Power on Reset The POL(2:1) switches on SW1 sets the configuration for the specific data input signal coding types between NRZ, HDB3 or AMI. These will be presetup in combination with the LXT334 configuration, where SW2 is used to define the I/O data coding type for the LXT334. The PORB switch will reset the device by forcing the PORB input Low. DM1C(4:1) Switches The DM1C(4:1) switches on SW1 set the diagnostic modes for data channels 1 to 4 with the associated TCLK/RCLK. DM2C(4:1) Switches The DM2C(4:1) switches on SW1 set the diagnostic modes for data channels 1 to 4 with the associated TCLK/RCLK. RESEL Switch The RESEL switch on SW1 is used to define the RCLK clock edge on which the RPOS/RNEG data is valid (see ACS406CS data sheet for more details). TRSEL Switch 5 The TRESEL switch on SW1 is used to define the TCLK clock edge on which the TPOS/TNEG data is valid (see ACS406CS data sheet for more details). Switch Bank SW2 Switch SW2 is used to configure signals on the LXT334 Quad LIU. SW2 defines the logic levels of signals LOP(3:0), CNTL(2:1), MODE(2:1). These switches will be pre-set, refer to the LXT334 data sheet for more details on the configuration options. Switch settings HIGH, Logic1 = switch up; LOW, Logic 0 = switch down. 4 Advanced Communications ACS406CS Reference Design ACS406CS Reference Design recommended component listing. This BOM refers to the component layout of the ACS406CS Reference Design, as shown on ACS406CS_Ref_Design which can be found in the ACS406CS section of the web site. Instance Value Additional information PORB LED1-LED9 ROU(3:0) Surface Mount R4-R6, R32-R37 R7 R8 R9-R11 R12 R13 R14 R15 R16-R23 R24-R27 Switch LED 0R Surface Mount Surface Mount 1.6K 100K 51K 680 1K 50K POT 3.3K 27 15 120 Surface Surface Surface Surface Surface Surface Surface Surface Surface Surface C1,C4,C6,C8 C22, C24 C25-C28,C31 C2,C30 C3,C7 C5 C9,C10 C11,C13,C15,C17 C12,C14,C16,C18 C19-C21,C29 C23 100nF 100nF 100nF 100pF 10nF 1nF 22pF 470pF 470nF 68uF 100uF Surface Mount Surface Mount Surface Mount Surface Mount Surface Mount Surface Mount Surface Mount Surface Mount Surface Mount Surface Mount tant Surface Mount ZD ZD ZENER DIODE TOUT0-TOUT3,ROUT0-ROUT3, TIN0-TIN3, RIN0-RIN3, term1,term2 L1-L3 SW1 SW2 XTAL terminal terminal Inductor 47uH Switch Switch Crystal LXT334 ACS4060 ACS9010 txflag, rxflag, rxmon Oscillator 64 QFP 100 TQFP 44 TQFP Header Oscil Unit ROU0,ROU1,ROU2,ROU3 DR TRANT0,TRANT1,TRANT2,TRANT3 TRANR0,TRANR1,TRANR2,TRANR3 LINKS, 0R Pin Headers Transformer Transformer 2 way terminal block 2 way terminal block SMD 0.68 RES switch 12 way switch 8 way 32.768MHz (4 x E1) 30.88MHz (4 x T1) Quad LIU OPTICAL IC OPTICAL IC Scope probe loop 2.048MHz 1.544MHz Surface Mount 32 Way Strip Pulse Pulse LC01-6 SRDA05-4 SO-16W SO-8 Low capacitance TVS diode array - Semtech Low capacitance TVS diode array - Semtech 5 Mount Mount Mount Mount Mount Mount Mount Mount Mount Mount 5 5 VDD R7 100 K 1 (E1) 2 3 (T1) DR GND LOSS LXT RCLK1 LXT RCLK2 LXT RCLK0 17 18 19 20 21 C31 100nF L3 GND GND AGND 24 25 C27 26 R35 1.6K 47uH 23 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 76 VDD 75 74 73 72 ACS9010 SLICING 71 70 ACS9010 RXDATA 69 68 67 66 65 64 63 R8 51k C9 62 22pF 61 XTAL 60 GND C10 22pF 59 58 57 56 55 54 53 52 51 VB C28 100nF GND 100nF LXT RPOS1 LXT RPOS2 LXT RNEG2 LXT RPOS3 LXT RNEG3 GND VDD ACS9010 ENTX ACS9010 ENRXB ACS9010 TXDATA GND ACS406CS Reference Design VDD PWR LXT RNEG0 LXT RCLK3 LXT RPOS0 LXT RNEG1 22 GND 50 GND to be placed in parallel with seperate gnd planes 16 49 15 48 14 ACS4060 47 13 46 12 POL1 POL2 DM1C4 IC SCEXT IC GND DM2C4 GND RXDATRXDAT+ GND IREF RES VA+ XIN XOUT TRSEL CM1 CM2 CM3 FRAME DM2C2 SETB FHOLD 45 6 11 44 10 43 LXT TNEG3 LXT TPOS3 (GND) 42 9 41 8 40 7 39 6 38 5 37 LXT TNEG1 LXT TPOS1 LXT TNEG2 LXT TPOS2 RNEG1 RPOS1 RMD3 RNEG2 RPOS2 RNEG3 RPOS3 RMD4 RNEG4 RPOS4 VD+ VD+ GND GND GND TMCLK TCLK2 TCLK3 TCLK1 TMD1 TMD2 TNEG1 TCLK4 TPOS1 TNEG2 36 4 35 3 34 100uF 25V 2 33 TERM2 C26 100nF 32 C25 100nF 30 LXT TNEG0 LXT TPOS0 C24 100nF 29 2 (+) C23 1 ZD1 1 31 L2 TERM1 TPOS2 TNEG3 TMD3 TPOS3 TNEG4 TPOS4 VD+ TMD4 GNDP3 TXDAT GND ECLK DM1C1 ENRXB ENTX IC M4B DM2C1 CKC CKM GND VD+ DM1C2 VD+ RESEL 47uH L1 GND GND GND GND RMD1 RMD2 RCLK3 RCLK1 RCLK2 RMCLK VD+ RCLK4 GND DR1 DR2 DR3 DR5 DR4 ERRC ERRL IC DM1C3 PORB LOSS DCD VD+ DM2C3 GND GND 100 VB 28 47uH (+) GND PORB LXT TCLK1 LXT TCLK0 LXT TCLK2 LXT TCLK3 27 (VDD) C8 R6 100nF 1.6K R5 1.6K GND VA SW1 1 2 3 4 5 6 7 8 9 101112 R4 1.6K VDD VDD PCBSW DCD ERRL GND VDD Advanced Communications VDD Figure 4: ACS4060 component schematic of the reference design. txflag 1 R13 R9 R10 R14 C1 R11 100n 680 680 3k3 50K 680 R12 1K 35 CTX2 36 TXMON ENTX RTSET VC TXDATA PLLVDD CLKOUT 37 TXFLAG 38 40 39 41 42 44 1 100pF C2 SRXDATA R15 100pF 27 2 GND1 ACS4060 RXDAT- 3 ACS9010 RXDAT+ 4 C3 RSET2 GND2 VDD TXGND 30 5 ACS9010 RXDATA 7 6 10n AGND DEUTSCH 1 LAN 29 4 LASER LAP 28 RRSET TXVDD 27 7 10n C7 C30 CTX1 31 Advanced Communications Figure 5: ACS9010 component schematic of the reference design. 8 LASRX MONPIN 26 ENRXB PINN 25 100n C4 2 F 9 E 1 C5 1 rxflag 0R AGND AGND T2T4 T3 T1 rxmon R3 VA R1 R2 C6 100n AGND 3 R2 1n VDD ACS4060 ENTX ACS4060 ENRXB ACS4060 TXDAT 20 ENCOFFB RXGND RXVDD RXMON 18 COFF2 19 COFF1 17 16 RXFLAG 15 14 13 AGND R1 0R R3 0R AGND SIEMENS ACS406CS Reference Design PINRX G PINP 24 5 ACS4060_RCLK4 ACS4060_RPOS4 ACS4060_RNEG4 ACS4060_RCLK3 ACS4060_RPOS3 ACS4060_RNEG3 ACS4060_TCLK3 ACS4060_TPOS3 ACS4060_TNEG3 ACS4060_TCLK4 ACS4060_TPOS4 ACS4060_TNEG4 ACS4060_TCLK1 ACS4060_TPOS1 ACS4060_TNEG1 ACS4060_TCLK2 ACS4060_TPOS2 ACS4060_TNEG2 Advanced Communications ACS4060_RNEG2 ACS4060_RPOS2 ACS4060_RCLK2 ACS4060_RNEG1 ACS4060_RPOS1 ACS4060_RCLK1 5 Figure 6: Quad LIU component schematic of the reference design. VDD tri_sw8 SW2 1 2 3 4 5 6 7 8 GND LOP0 LOP1 LOP2 VDD 8 5 LOP3 GND 4 GND 1 2 C29 (+)68uF 3 4 5 6 7 8 9 TTIP0 10 11 12 TRING0 13 14 15 50 51 52 53 54 55 56 57 58 59 60 61 62 63 49 VDD 48 47 46 45 44 43 42 41 40 C21 (+) 39 38 8 68uF 36 35 GND 34 (+) C20 68uF 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 (+)C19 18 TTIP1 C22 100nF 37 MODE1 MODE2 RRING0 RTIP0 LOS0 RRING1 RTIP1 LOS1 RRING2 RTIP2 LOS2 RRING3 RTIP3 LOS3 CNTL1 CNTL2 16 DFM TCLK3 TPOS3 TNEG3 TCLK2 TPOS2 TNEG2 VCC TTIP3 TGND3 TVCC3 TRING3 TTIP2 TGND2 TVCC2 TRING2 LXT334 17 VDD MCLK TCLK0 TPOS0 TNEG0 TCLK1 TPOS1 TNEG1 GND TTIP0 TGND0 TVCC0 TRING0 TTIP1 TGND1 TVCC1 TRING1 RCLK0 RPOS0 RNEG0 RCLK1 RPOS1 RNEG1 LOOP0 LOOP1 LOOP2 LOOP3 RCLK2 RPOS2 RNEG2 RCLK3 RPOS3 RNEG3 64 O/P VDD OSCILLATOR RTIP0 RRING0 RTIP1 RRING1 68uF TRING1 RTIP2 RRING2 CNTL2 TTIP2 CNTL1 RTIP3 MODE2 MODE1 TRING2 TTIP3 Please place Caps C19-C22, C29 close to LXT334 TRING3 LOS2 LOS0 DFM R32 1.6K R33 1.6K GND R34 1.6K GND GND LOS1 R36 1.6K GND LOS3 R37 1.6K GND ACS406CS Reference Design RRING3 3 470nF 2 R17 15 5 6 7 8 5 6 4 1 1 3 1 ROU2 2 C15 470pF ROUT2 1 5 6 7 8 C16 12 11 10 9 16 15 14 13 ROUT0 1 2 3 4 C12 TRING0 15 1 TOUT2 LCO1-6_F 1 2 3 4 3 1 ROU0 2 C11 470pF 3 1 15 12 11 10 9 16 15 14 13 TTIP0 TRANT2 6 5 R20 TTIP2 TOUT0 LCO1-6_B 5 6 7 8 3 2 GND 4 TRANT0 6 5 1 2 SRDA05-4_C 2 GND 8 VDD Figure 7: Line Termination component schematic of the reference design. 7 6 SRDA05-4_A 1 1 2 3 4 5 6 7 8 1 2 3 4 RIN2 1 2 R16 1 4,5 RRING2 5 6 6 7 R26 240 TIN2 LCO1-6_E 1 RIN0 LCO1-6_A 8 1 4,5 RRING0 VDD 3 16 15 14 13 12 11 10 9 16 15 14 13 R24 240 TRANR2 RTIP2 1 3 TRING2 470nF 1 2 R21 15 Advanced Communications 3 12 11 10 9 TIN0 TRANR0 RTIP0 1 9 RTIP3 4,5 1 2 3 4 5 6 7 8 6 5 6 7 8 RIN3 RRING3 1 2 1 1 2 5 6 7 VDD 8 5 6 7 TIN3 LCO1-6_G GND GND 470nF R19 15 2 1 4 15 TRING3 3 470nF R23 15 12 11 10 9 3 1 ROU3 2 C17 470pF 2 1 1 ROUT3 5 6 7 8 C18 TOUT3 LCO1-6_H 16 15 14 13 1 ROUT1 1 TRANT3 6 5 1 2 3 4 ROU1 2 3 TRING1 R22 TTIP3 12 11 10 9 16 15 14 13 3 1 1 2 3 4 C14 C13 470pF TOUT1 LCO1-6_D 15 3 1 TRANT1 6 5 5 6 7 8 R18 TTIP1 2 SRDA05-4_D 4 3 2 1 SRDA05-4_B 1 ACS406CS Reference Design 6 1 RIN1 1 2 3 4 RRING1 8 R27 240 4,5 LCO1-6_C VDD 3 1 16 15 14 13 16 15 14 13 R25 240 TRANR3 1 12 11 10 9 3 12 11 10 9 TIN1 TRANR1 RTIP1 5 Advanced Communications ACS406CS Reference Design For additional information, contact the following: Semtech Corporation Advanced Communications Products E-Mail: [email protected] Internet: http://www.semtech.com USA: 652 Mitchell Road, Newbury Park, CA 91320-2289 Tel: +1 805 498 2111, Fax: +1 805 498 3804 FAR EAST: 11F, No. 46, Lane 11, Kuang Fu North Road, Taipei, Taiwan, R.O.C. Tel: +886 2 2748 3380, Fax: +886 2 2748 3390 EUROPE: Delta House, Chilworth Research Centre, Southampton, Hants, SO16 7NS, UK Tel: +44 23 80 769008, Fax: +44 23 80 768612 5 ISO9001 CERTIFIED Semtech reserves the right to change specifications on catalog devices without notice. © Copyright Semtech Corp 2000 10