ETC LRS1329A

LRS1329A
• Handle this document carefully for it contains material protected by international copyright law.
Any reproduction, full or in part, of this material is prohibited without the express written permission
of the company.
• When using the products covered herein, please observe the conditions written herein and the
precautions outlined in the following paragraphs. In no event shall the company be liable for
any damages resulting from failure to strictly adhere to these conditions and precautions.
(1) The products covered herein are designed and manufactured for the following application areas.
When using the products covered herein for the equipment listed in Paragraph (2), even for the
following application areas, be sure to observe the precautions given in Paragraph (2). Never use
the products for the equipment listed in Paragraph (3).
•Office electronics
•Instrumentation and measuring equipment
•Machine tools
•Audiovisual equipment
•Home appliance
•Communication equipment other than for trunk lines
(2) Those contemplating using the products covered herein for the following equipment
which demands high reliability, should first contact a sales representative of the company and
then accept responsibility for incorporating into the design fail-safe operation, redundancy, and
other appropriate measures for ensuring reliability and safety of the equipment and the overall
system.
•Control and safety devices for airplanes, trains, automobiles, and other transportation
equipment
•Mainframe computers
•Traffic control systems
•Gas leak detectors and automatic cutoff devices
•Rescue and security equipment
•Other safety devices and safety equipment, etc.
(3) Do not use the products covered herein for the following equipment which demands extremely
high performance in terms of functionality, reliability, or accuracy.
•Aerospace equipment
•Communications equipment for trunk lines
•Control equipment for the nuclear power industry
•Medical equipment related to life support, etc.
(4) Please direct all queries and comments regarding the interpretation of the above three
Paragraphs to a sales representative of the company.
• Please direct all queries regarding the products covered herein to a sales representative of the
company.
Rev. 1.00
LRS1329A
1
Contents
1. Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
2. Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
3. Truth Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
4. Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
5. Command Definitions for Flash Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.1 Command Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.2. Identifier Codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.3. Write Protection Alternatives . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7
7
7
7
6. Status Register Definition. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
7. Memory Map for Flash Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
8. Absolute Maximum Ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
9. Recommended DC Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
10. Pin Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
11. DC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
12. AC Electrical Characteristics for Flash Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
12.1 AC Test Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
12.2 Read Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
12.3 Write Cycle (F-WE Controlled) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
12.4 Write Cycle (F-CE Controlled) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
12.5 Block Erase and Word/Byte Write Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
12.6 Flash Memory AC Characteristics Timing Chart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
12.7 Reset Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
13
13
13
14
15
16
17
21
13. AC Electrical Characteristics for SRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
13.1 AC Test Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
13.2 Read Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
13.3 Write Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
13.4 SRAM AC Characteristics Timing Chart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
22
22
22
22
23
14. Data Retention Characteristics for SRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
15. Notes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
16. Flash Memory Data Protection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
17. Design Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
18. Related Document Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Rev. 1.00
LRS1329A
2
1. Description
The LRS1329A is a combination memory organized as 2,097,152 × 8 / 1,048,576 × 16 bit flash memory and 262,144 × 8 bit
static RAM in one package.
Features
- Power supply
• • • •
2.7V to 3.6V
- Operating temperature
• • • •
-25°C to +85°C
- Not designed or rated as radiation hardened
- 72 pin CSP (LCSP072-P-0811) plastic package
- Flash memory has P-type bulk silicon, and SRAM has P-type bulk silicon.
Flash Memory
- Access Time
• • • •
- Power Supply current (The current for F-VCC pin and F-VPP pin)
Read
• • • •
Word/Byte write
• • • •
Block erase
• • • •
Reset Power-Down
• • • •
Standby
100ns
(Max.)
25 mA
57 mA
42 mA
15µA
• • • •
65µA
(Max. tCYCLE = 200ns, CMOS Input)
(Max.)
(Max.)
(Max. F-RP = GND ± 0.2V,
IOUT(F-RY/BY) = 0mA)
(Max. F-CE = F-RP = F-VCC ± 0.2V)
• • • •
85 ns
(Max.)
•
•
•
•
35mA
6 mA
30µA
30µA
(Max. tRC,tWC = Min.)
(Max. tRC,tWC = 1µs, CMOS Input)
(Max.)
(Max.)
- Optimized Array Blocking Architecture for each Bank.
Two 4k-word/8k-byte Boot Blocks
Six 4k-word/8k-byte Parameter Blocks
Thirty-one 32k-word/64k-byte Main Blocks
Top Boot Location
- Extended Cycling Capability
100,000 Block Erase Cycles
- Enhanced Automated Suspend Options
Word/Byte Write Suspend to Read
Block Erase Suspend to Word/Byte Write
Block Erase Suspend to Read
SRAM
- Access Time
- Power Supply current
Operating current
Standby current
Data retention current
•
•
•
•
•
•
•
•
•
•
•
•
Rev. 1.00
LRS1329A
3
2. Pin Configuration
INDEX
(TOP View)
1
2
3
4
5
6
7
8
9
10
11
12
NC
NC
NC
A11
A12
A13
S-OE
F-GND
F-DQ15
/F-A-1
NC
NC
NC
B
S-CE2
S-WE
A10
A9
A16
S-CE1
DQ7
F-DQ14
C
RY/BY
F-WE
F-RP
T1
F-DQ12
DQ6
F-DQ13
DQ5
D
F-GND
S-VCC
A8
T2
F-BYTE
F-DQ11
DQ4
F-VCC
E
F-VPP
F-WP
F-A19
T3
T4
DQ3
F-DQ10
S-GND
F
F-A18
F-A17
A7
NC
A14
DQ2
DQ1
F-DQ9
G
A6
A5
A4
A1
F-GND
A15
F-DQ8
DQ0
NC
A3
A2
A0
F-CE
F-OE
S-A17
NC
NC
NC
A
H
F-
NC
NC
Note) From T1 to T4 pins are needed to be open.
Two NC pins at the corner are connected.
Do not float any GND pins.
Rev. 1.00
LRS1329A
Pin
A0 to A16
F-A-1, F-A17 to F-A19
Description
Address Inputs (Common)
Address Inputs (Flash)
4
Type
Input
F-A-1 : Not used in x16 mode.
F-A-1 : L.S.B in x8 mode.
Input
S-A17
Address Inputs (SRAM)
Input
F-CE
Chip Enable Inputs (Flash)
Input
Chip Enable Inputs (SRAM)
Input
F-WE
Write Enable Input (Flash)
Input
S-WE
Write Enable Input (SRAM)
Input
F-OE
Output Enable Input (Flash)
Input
S-OE
Output Enable Input (SRAM)
Input
F-RP
Reset Power Down Input (Flash)
Block erase and Word/Byte Write : VIH or VHH
Read : VIH or VHH
Reset Power Down : VIL
Input
F-WP
Write Protect Input (Flash)
Two Boot Blocks Locked : VIL
(With F-RP = VHH Erase of Write can operate to all block)
Input
F-BYTE
Byte Enable (Flash);
Input
F-RY/BY
Ready/Busy Output (Flash)
During an Erase or Write operation : VOL
Block Erase and Word/Byte Write Suspend : High-Z (High impedance)
Reset Power Down : High-Z (High impedance)
S-CE1, S-CE2
DQ0 to DQ7
F-DQ8 to F-DQ15
x8 mode : VIL, x16 mode : VIH
Open Drain
Output
Data Inputs and Outputs (Common)
Input / Output
Data Inputs and Outputs (Flash) ; Not used in x8 mode.
Input / Output
F-VCC
Power Supply (Flash)
Power
S-VCC
Power Supply (SRAM)
Power
F-VPP
Write, Erase Power Supply (Flash)
Block Erase and Word/Byte Write : F-VPP = VPPH
All Blocks Locked : F-VPP < VPPLK
Power
F-GND
GND (Flash)
Power
S-GND
GND (SRAM)
Power
NC
T1 to T4
Non Connection (Should be all open)
-
Test pin (Should be all open)
-
Rev. 1.00
LRS1329A
5
3. Truth Table(1)
Flash
SRAM
Read
Notes
F-CE
F-RP F-OE F-WE F-BYTE S-CE1 S-CE2 S-OE S-WE
4,5,6
Standby
5,6
L
L
2,3,4,5,6
Read
Standby
6
Write
6
Read
6
Write
X
6
X
DIN
DIN
L
H
X
X
X
L
H
H
H
L
L
X
X
X
L
H
H
H
6
L
Standby
6
H
H
Reset Power Standby
Down
6
X
L
X
X
X
(7)
X
High-Z
High-Z
DIN
DOUT
L
X
High-Z
DOUT
L
H
High-Z
High-Z
H
6
Output
Disable
Reset Power Output
Down
Disable
(7)
L
H
Write
DOUT
L
H
H
F-DQ8
to F-DQ15
DOUT
H
L
H
Output
Disable
DQ0
to DQ7
X
High-Z
High-Z
DIN
High-Z
Notes:
1. L = VIL, H = VIH, X = H or L. Refer to DC Characteristics. High-Z = High impedance.
2. Command Writes involving block erase or word/byte write are reliably executed when F-VPP = VPPH and F-VCC = 2.7V to
3.6V.
Block erase or word/byte write with VIH < F-RP < VHH produce spurious results and should not be attempted.
3. Refer Section 5. Command Definitions for valid address input and DIN during a write operation.
4. Never hold F-OE low and F-WE low at the same timing.
5. F-A-1 set to VIL or VIH in byte mode (F-BYTE = VIL)
6. F-WP set to VIL or VIH.
7. SRAM Standby Mode
S-CE1 S-CE2
H
X
X
L
Rev. 1.00
LRS1329A
6
4. Block Diagram
F-VPP
F-VCC
F-GND
F-A-1, F-A17 to F-A19
A0 to A16
F-RY/BY
F-CE
F-OE
16M (x8/x16) bit
F-WE
Flash memory
F-DQ8 to F-DQ15
F-WP
F-RP
F-BYTE
DQ0 to DQ7
S-A17
S-CE1
2M (x8) bit
SRAM
S-CE2
S-OE
S-WE
S-VCC
S-GND
Rev. 1.00
LRS1329A
7
5. Command Definitions for Flash Memory(1)
5.1 Command Definitions
Bus Cycles
Required
Command
Read Array / Reset
First Bus Cycle
Note
Second Bus Cycle
Oper(2)
Address(3)
Data(3)
Write
XA
FFH
Write
XA
1
Oper(2)
Address(3)
Data(3)
90H
Read
IA
ID
Read
XA
SRD
Read Identifier Codes
≥2
Read Status Register
2
Write
XA
70H
Clear Status Register
1
Write
XA
50H
Block Erase
2
5
Write
BA
20H
Write
BA
D0H
Word/Byte Write
2
5
Write
WA
40H or
10H
Write
WA
WD
Block Erase and Word/Byte
Write Suspend
1
5
Write
XA
B0H
Block Erase and Word/Byte
Write Resume
1
5
Write
XA
D0H
4
Notes:
1. Commands other than those shown above are reserved by SHARP for future device implementations and should not be used.
2. Bus operations are defined in 3. Truth Table.
3. XA = Any valid address within the device.
IA = Identifier code address.
BA = Address within the block being erased.
WA = Address of memory location to be written.
SRD = Data read from status register (See 6. Status Register Definition).
WD = Data to be written at location WA. Data is latched on the rising edge of F-WE or F-CE (whichever goes high first).
ID = Data read from identifier codes (See 5.2 Identifier Codes).
4. See Identifier Codes in section 5.2.
5. See Write Protection Alternatives in section 5.3.
5.2 Identifier Codes(1)
Codes
Address [A19 - A0]
Data [DQ7 - DQ0]
Manufacture Code
00000H
B0H
Device Code
00001H
48H
Notes:
1. Read Identifier Codes command is defined in 5.1 Command Definitions.
5.3 Write Protection Alternatives
F-VPP
F-RP
Operation
VIL
Block Erase or
Word/Byte
Write
>VPPLK(1)
F-WP
Effect
X
X
All Blocks Locked.
VIL
X
All Blocks Locked.
VHH
X
All Blocks Unlocked.
VIL
2 Boot Blocks Locked.
VIH
All Blocks Unlocked.
VIH
Note:
1. F-VPP is guaranteed only with the nominal voltages.
Rev. 1.00
LRS1329A
8
6. Status Register Definition
WSMS
ESS
ES
WBWS
VPPS
WBWSS
DPS
R
7
6
5
4
3
2
1
0
SR.7 = WRITE STATE MACHINE STATUS (WSMS)
1 = Ready
0 = Busy
SR.6 = ERASE SUSPEND STATUS (ESS)
1 = Block Erase Suspended
0 = Block Erase in Progress/Completed
Notes:
Check SR.7 or F-RY/BY to determine Block Erase or Word/
Byte Write completion.
SR.6 - SR.0 are invalid while SR.7 = “0”.
If both SR.5 and SR.4 are “1”s after a Block Erase attempt, an
improper command sequence was entered.
SR.5 = ERASE STATUS (ES)
1 = Error in Block Erase
0 = Successful Block Erase
SR.4 = WORD/BYTE WRITE STATUS (WBWS)
1 = Error in Word/Byte Write
0 = Successful Word/Byte Write
SR.3 = F-VPP STATUS (VPPS)
1 = F-VPP Low Detect, Operation Abort
0 = F-VPP OK
SR.2 = WORD/BYTE WRITE SUSPEND STATUS
(WBWSS)
1 = Word/Byte Write Suspended
0 = Word/Byte Write in Progress/Completed
SR.1 = DEVICE PROTECT STATUS (DPS)
1 = F-WP or F-RP Lock Detected, Operation Abort
0 = Unlocked
SR.3 does not provide a continuous indication of F-VPP level.
The WSM (Write State Machine) interrogates and
indicates the F-VPP level only after Block Erase or Word/Byte
Write command sequences. SR.3 is not guaranteed to reports
accurate feedback only when F-VPP ≠ VPPH.
SR.1 does not provide a continuous indication of F-WP and FRP values. The WSM interrogates the F-WP and F-RP only
after Block Erase or Word/Byte Write command sequences. It
informs the system, depending on the attempted operation, if
the F-WP is not VIH, F-RP is not VHH.
SR.0 is reserved for future use and should be masked out when
SR.0 = RESERVED FOR FUTURE ENHANCEMENTS (R) polling the status register.
Rev. 1.00
LRS1329A
9
7. Memory Map for Flash Memory
Top Boot
[A19 ~ A0]
FFFFF
FF000
FEFFF
FE000
FDFFF
FD000
FCFFF
FC000
FBFFF
FB000
FAFFF
FA000
F9FFF
F9000
F8FFF
F8000
F7FFF
F0000
EFFFF
E8000
E7FFF
E0000
DFFFF
D8000
D7FFF
D0000
CFFFF
C8000
C7FFF
C0000
BFFFF
B8000
B7FFF
B0000
AFFFF
A8000
A7FFF
A0000
9FFFF
98000
97FFF
90000
8FFFF
88000
87FFF
80000
7FFFF
78000
77FFF
70000
6FFFF
68000
67FFF
60000
5FFFF
58000
57FFF
50000
4FFFF
48000
47FFF
40000
3FFFF
38000
37FFF
30000
2FFFF
28000
27FFF
20000
1FFFF
18000
1FFFF
10000
0FFFF
08000
07FFF
00000
[A19 ~ A-1]
4K-word/8K-byte Boot Block 0
4K-word/8K-byte Boot Block 1
4K-word/8K-byte Parameter Block 0
4K-word/8K-byte Parameter Block 1
4K-word/8K-byte Parameter Block 2
4K-word/8K-byte Parameter Block 3
4K-word/8K-byte Parameter Block 4
4K-word/8K-byte Parameter Block 5
32K-word/64K-byte Main Block 0
32K-word/64K-byte Main Block 1
32K-word/64K-byte Main Block 2
32K-word/64K-byte Main Block 3
32K-word/64K-byte Main Block 4
32K-word/64K-byte Main Block 5
32K-word/64K-byte Main Block 6
32K-word/64K-byte Main Block 7
32K-word/64K-byte Main Block 8
32K-word/64K-byte Main Block 9
32K-word/64K-byte Main Block 10
32K-word/64K-byte Main Block 11
32K-word/64K-byte Main Block 12
32K-word/64K-byte Main Block 13
32K-word/64K-byte Main Block 14
32K-word/64K-byte Main Block 15
32K-word/64K-byte Main Block 16
32K-word/64K-byte Main Block 17
32K-word/64K-byte Main Block 18
32K-word/64K-byte Main Block 19
32K-word/64K-byte Main Block 20
32K-word/64K-byte Main Block 21
32K-word/64K-byte Main Block 22
32K-word/64K-byte Main Block 23
32K-word/64K-byte Main Block 24
32K-word/64K-byte Main Block 25
32K-word/64K-byte Main Block 26
32K-word/64K-byte Main Block 27
32K-word/64K-byte Main Block 28
32K-word/64K-byte Main Block 29
32K-word/64K-byte Main Block 30
1FFFFF
1FE000
1FDFFF
1FC000
1FBFFF
1FA000
1F9FFF
1F8000
1F7FFF
1F6000
1F5FFF
1F4000
1F3FFF
1F2000
1F1FFF
1F0000
1EFFFF
1E0000
1DFFFF
1D0000
1CFFFF
1C0000
1BFFFF
1B0000
1AFFFF
1A0000
19FFFF
190000
18FFFF
180000
17FFFF
170000
16FFFF
160000
15FFFF
150000
14FFFF
140000
13FFFF
130000
12FFFF
120000
11FFFF
110000
10FFFF
100000
0FFFFF
0F0000
0EFFFF
0E0000
0DFFFF
0D0000
0CFFFF
0C0000
0BFFFF
0B0000
0AFFFF
0A0000
09FFFF
090000
08FFFF
080000
07FFFF
070000
06FFFF
060000
05FFFF
050000
04FFFF
040000
03FFFF
030000
02FFFF
020000
01FFFF
010000
00FFFF
000000
Rev. 1.00
LRS1329A
10
8. Absolute Maximum Ratings
Symbol
Parameter
Notes
Ratings
Unit
1,2
-0.2 to +4.0
V
1,3,4,6
-0.2 to VCC+0.3
V
VCC
Supply voltage
VIN
Input voltage
TA
Operating temperature
-25 to +85
°C
TSTG
Storage temperature
-55 to +125
°C
F-VPP
F-VPP voltage
1,4,5
-0.2 to +14.0
V
F-RP
F-RP voltage
1,4,5
-0.5 to +14.0
V
Notes:
1. The maximum applicable voltage on any pins with respect to GND.
2. Except F-VPP.
3. Except F-RP.
4. -1.0V undershoot and VCC + 1.0V overshoot are allowed when the pulse width is less than 20 nsec.
5. +14.0V overshoot is allowed when the pulse width is less than 20 nsec.
6. VIN should not be over VCC + 0.3V.
9. Recommended DC Operating Conditions
(TA = -25°C to +85°C)
Symbol
VCC
Parameter
Supply Voltage
VIH
VIL
Notes
Min.
Typ.
Max.
Unit
2
2.7
3.0
3.6
V
1
2.2
VCC+0.2
V
-0.2
0.8
V
11.4
12.6
V
Input Voltage
VHH
3
Notes:
1. VCC is the lower one of F-VCC and S-VCC.
2. VCC includes both F-VCC and S-VCC.
3. This voltage is applicable to F-RP Pin only.
10. Pin Capacitance
(TA = 25°C, f = 1MHz)
Symbol
Parameter
Notes
Min.
Typ.
Max.
Unit
Condition
CIN
Input capacitance
1
20
pF
VIN = 0V
CI/O
I/O capacitance
1
22
pF
VI/O = 0V
Note:
1. Sampled but not 100% tested.
Rev. 1.00
LRS1329A
11
11. DC Electrical Characteristics(6)
DC Electrical Characteristics
(TA = -25°C to +85°, VCC = 2.7V to 3.6V)
Symbol
Parameter
Notes Min. Typ.
(1)
Max.
Unit
Conditions
ILI
Input Leakage Current
±1.5
µA VIN = VCC or GND
ILO
Output Leakage Current
±1.5
µA VOUT = VCC or GND
ICCS
ICCD
ICCR
F-VCC Standby Current
F-VCC Reset Power-Down Current
F-VCC Read Current
25
50
CMOS Input
µA F-CE = F-RP = F-V ± 0.2V
CC
0.2
2
TTL Input
mA F-CE = F-RP = V
IH
5
10
F-RP = GND ± 0.2V
µA I
OUT(F-RY/BY) = 0mA
25
CMOS Input
mA F-CE = GND, f = 5MHz, I
OUT = 0mA
30
TTL Input
mA F-CE = V , f = 5MHz, I
IL
OUT = 0mA
2,4,9
4,9
3,4
ICCW
F-VCC Word/Byte Write Current
7
17
mA F-VPP = VPPH
ICCE
F-VCC Block Erase Current
7
17
mA F-VPP = VPPH
6
mA F-CE = VIH
ICCWS F-VCC Word/Byte Write or Block
ICCES Erase Suspend Current
±2
±15
µA F-VPP ≤ F-VCC
10
200
µA F-VPP > F-VCC
4
0.1
5
µA
F-VPP Word/Byte Write Current
7
12
40
mA F-VPP = VPPH
F-VPP Block Erase Current
7
8
25
mA F-VPP = VPPH
10
200
µA F-VPP = VPPH
IPPS
IPPR
F-VPP Standby or Read Current
4
IPPD
F-VPP Reset Power-Down Current
IPPW
IPPE
IPPWS F-VPP Word/Byte Write or Block Erase
IPPES Suspend Current
CMOS Input
F-RP = GND ± 0.2V
S-CE1, S-CE2 ≥ S-VCC - 0.2V or
S-CE2 ≤ 0.2V
ISB
S-VCC Standby Current
30
µA
ISB1
S-VCC Standby Current
3
mA S-CE1 = VIH or S-CE2 = VIL
35
S-CE1 = VIL,
mA S-CE2 = VIH
VIN = VIL or VIH
tCYCLE =Min.
II/O = 0mA
6
S-CE1 = 0.2V,
S-CE2 = SVCC -0.2V,
mA
VIN = S-VCC -0.2V
or 0.2V
tCYCLE = 1µs
II/O = 0mA
ICC1
ICC2
S-VCC Operation Current
S-VCC Operation Current
Rev. 1.00
LRS1329A
12
DC Electrical Characteristics (Continue)
(TA = -25°C to +85°C, VCC = 2.7V to 3.6V)
Symbol
Parameter
Notes
Min.
Typ.(1)
Max.
Unit
Conditions
VIL
Input Low Voltage
7
-0.2
0.8
V
VIH
Input High Voltage
7
2.2
VCC
+0.2
V
VOL
Output Low Voltage
2,7
0.4
V
IOL = 2.0mA
VOH
Output High Voltage
2,7
V
IOH = -1.0mA
VPPLK
F-VPP Lockout during Normal
Operations
5,7
VPPH
F-VPP Word/Byte Write Block Erase
Operations
2.7
VLKO
F-VCC Lockout Voltage
1.5
VHH
F-RP Unlock Voltage
8
2.4
11.4
1.5
V
3.6
V
V
12.6
V
Unavailable F-WP
Notes:
1. All currents are in RMS unless otherwise noted. Reference values at VCC = 3.0V and TA = +25°C.
2. Includes F-RY/BY.
3. Automatic Power Savings (APS) for Flash Memory reduces typical ICCR to 3mA at 2.7V in static operation.
4. CMOS inputs are either VCC ± 0.2V or GND ± 0.2V. TTL inputs are either VIL or VIH.
5. Block erases and word/byte writes are inhibited when F-VPP ≤ VPPLK and not guaranteed in the range between VPPLK (Max.)
and VPPH (Min.), and above VPPH (Max.).
6. VCC includes both F-VCC and S-VCC.
7. Sampled, not 100% tested.
8. F-RP connection to a VHH supply is allowed for a maximum cumulative period of 80 hours.
9. F-BYTE is VCC ± 0.2V in word mode and is GND ± 0.2V in byte mode.
F-WP is VCC± 0.2V or GND ± 0.2V
Rev. 1.00
LRS1329A
13
12. AC Electrical Characteristics for Flash Memory
12.1 AC Test Conditions
Input pulse level
0V to 2.7V
Input rise and fall time
5ns
Input and Output timing Ref. level
1.35V
1TTL + CL (30pF)
Output load
12.2 Read Cycle
(TA = -25°C to +85°C, F-VCC = 2.7V to 3.6V)
Symbol
Parameter
tAVAV
Read Cycle Time
tAVQV
Address to Output Delay
tELQV
F-CE to Output Delay
tPHQV
F-RP High to Output Delay
tGLQV
F-OE to Output Delay
tELQX
F-CE to Output in Low-Z
tEHQZ
F-CE High to Output in High-Z
tGLQX
F-OE to Output in Low-Z
tGHQZ
F-OE High to Output in High-Z
tOH
Notes
Min.
Max.
100
1
1
Output Hold form Address, F-CE or F-OE Change, Whichever Occurs First
Unit
ns
100
ns
100
ns
10
µs
45
ns
0
ns
45
0
ns
ns
20
0
ns
ns
tFVQV
F-BYTE and A-1 to Output Delay
100
ns
tFLQZ
F-BYTE Low to Output in High-Z
30
ns
tELFV
F-CE to F-BYTE High or Low
5
ns
Note:
1. F-OE may be delayed up to tELQV - tGLQV after the falling edge of F-CE without impact on tELQV.
Rev. 1.00
LRS1329A
14
12.3 Write Cycle (F-WE Controlled)(1,5)
(TA = -25°C to +85°C, F-VCC = 2.7V to 3.6V)
Symbol
Parameter
tAVAV
Write Cycle Time
tPHWL
F-RP High Recovery to F-WE Going to Low
tELWL
tWLWH
Notes
Min.
Max.
Unit
100
ns
10
µs
F-CE Setup to F-WE Going Low
0
ns
F-WE Pulse Width
50
ns
2
tPHHWH F-RP VHH Setup to F-WE Going High
2
100
ns
tSHWH
F-WP VIH Setup to F-WE Going High
2
100
ns
tVPWH
F-VPP Setup to F-WE Going High
2
100
ns
tAVWH
Address Setup to F-WE Going High
3
50
ns
tDVWH
Data Setup to F-WE Going High
3
50
ns
tWHDX
Data Hold from F-WE High
0
ns
tWHAX
Address Hold from F-WE High
0
ns
tWHEH
F-CE Hold from F-WE High
0
ns
tWHWL
F-WE Pulse Width High
30
ns
tWHRL
F-WE High to F-RY/BY Going Low
tWHGL
Write Recovery before Read
tQVVL
F-VPP Hold from Valid SRD, F-RY/BY High-Z
tQVPH
100
ns
0
ns
2,4
0
ns
F-RP VHH Hold from Valid SRD, F-RY/BY High-Z
2,4
0
ns
tQVSL
F-WP VIH Hold from Valid SRD, F-RY/BY High-Z
2,4
0
ns
tFVWH
F-BYTE Setup to F-WE Going High
50
ns
tWHFV
F-BYTE Hold from F-WE High
100
ns
Notes:
1. Read timing characteristics during block erase and word/byte write operations. Refer to AC Characteristics for read cycle.
2. Sampled, not 100% tested.
3. Refer to Section 5. Command Definitions for Flash Memory for valid AIN and DIN for block erase or word/byte write.
4. F-VPP should be held at VPPH until determination of block erase or word/byte write success (SR.1/3/4/5 = 0).
5. It is written when F-CE and F-WE are active. The address and data needed to execute a command are latched on the rising
edge of F-WE or F-CE (Whichever goes high first).
Rev. 1.00
LRS1329A
15
12.4 Write Cycle (F-CE Controlled)(1,2,6)
(TA = -25°C to +85°C, F-VCC = 2.7V to 3.6V)
Symbol
Parameter
tAVAV
Write Cycle Time
tPHEL
F-RP High Recovery to F-CE Going Low
tWLEL
tELEH
Notes
Min.
Max.
Unit
100
ns
10
µs
F-WE Setup to F-CE Going Low
0
ns
F-CE Pulse Width
70
ns
3
tPHHEH
F-RP VHH Setup to F-CE Going High
3
100
ns
tSHEH
F-WP VIH Setup to F-CE Going High
3
100
ns
tVPEH
F-VPP Setup to F-CE Going High
3
100
ns
tAVEH
Address Setup to F-CE Going High
4
50
ns
tDVEH
Data Setup to F-CE Going High
4
50
ns
tEHDX
Data Hold from F-CE High
0
ns
tEHAX
Address Hold from F-CE High
0
ns
tEHWH
F-WE Hold from F-CE High
0
ns
tEHEL
F-CE Pulse Width High
25
ns
tEHRL
F-CE High to F-RY/BY Going Low
tEHGL
Write Recovery before Read
tQVVL
F-VPP Hold from Valid SRD, F-RY/BY High-Z
tQVPH
100
ns
0
ns
3,5
0
ns
F-RP VHH Hold from Valid SRD, F-RY/BY High-Z
3,5
0
ns
tQVSL
F-WP VIH Hold from Valid SRD, F-RY/BY High-Z
3,5
0
ns
tFVEH
F-BYTE Setup to F-WE Going High
50
ns
tEHFV
F-BYTE Hold from F-WE High
100
ns
Notes:
1. Read timing characteristics during block erase and word/byte write operations. Refer to AC Characteristics for read cycle.
2. In systems where F-CE defines the write pulse width (within a longer F-WE timing waveform), all setup, hold and inactive
F-WE times should be measured relative to the F-CE waveform.
3. Sampled, not 100% tested.
4. Refer to Section 5. Command Definitions for Flash Memory for valid AIN and DIN for block erase or word/byte write.
5. F-VPP should be held at VPPH until determination of block erase or word/byte write success (SR.1/3/4/5 = 0).
6. It is written when F-CE and F-WE are active. The address and data needed to execute a command are latched on the rising
edge of F-WE or F-CE (Whichever goes high first).
Rev. 1.00
LRS1329A
16
12.5 Block Erase and Word/Byte Write Performance(3)
(TA = -25°C to +85°C, F-VCC = 2.7V to 3.6V)
Symbol
tWHQV1
tEHQV1
Parameter
Word/Byte Write Time
Block Write Time
(at word mode)
Block Write Time
(at byte mode)
Notes
F-VPP = 2.7V to 3.6V
Typ.(1)
Unit
Max.
32K/64K-Word/Byte Block
2
55
µs
4K/8K-Word/Byte Block
2
60
µs
32K-Word Block
2
1.8
s
4K-Word Block
2
0.3
s
64K-Byte Block
2
3.6
s
8K-Byte Block
2
0.6
s
32K/64K-Word/Byte Block
2
1.2
s
s
tWHQV2
tEHQV2
Block Erase Time
4K/8K-Word/Byte Block
2
0.5
tWHRZ1
tEHRZ1
Word/Byte Write Suspend Latency Time to Read
4
7.5
8.6
µs
tWHRZ2
tEHRZ2
Erase Suspend Latency Time to Read
4
19.3
23.6
µs
Notes:
1. Reference values at TA = +25°C and F-VCC = 3.0V, F-VPP = 3.0V. Assumes corresponding lock-bits are not set. Subject to
change based on device characterization.
2. Excludes system-level overhead.
3. Sampled, not 100% tested.
4. A Latency time is required from issuing suspend command (F-WE or F-CE going high ) until F-RY/BY going High-Z or
SR.7 going “1”.
Rev. 1.00
LRS1329A
17
12.6 Flash Memory AC Characteristics Timing Chart
Read Cycle Timing Chart
Device
VIH
Standby
Address Selection
Data Valid
Address Stable
Address(A)
VIL
tAVAV
VIH
F-CE(E)
tEHQZ
VIL
VIH
F-OE(G)
tGHQZ
VIL
VIH
tGLQV
F-WE(W)
tELQV
VIL
VOH
Data(D/Q)
VOL
tGLQX
tOH
tELQX
High - Z
Valid Output
High - Z
tAVQV
F-VCC
tPHQV
VIH
F-RP(P)
VIL
Rev. 1.00
LRS1329A
18
F-BYTE Timing Waveform
Device
VIH
Standby
Address Selection
Data Valid
Address Stable
Address(A)
VIL
tAVAV
VIH
F-CE
tEHQZ
VIL
VIH
F-OE(G)
tGHQZ
VIL
tELFV
tGLQV
tFVQV
VIH
F-BYTE(F)
VIL
tELQV
tGLQX
tOH
tELQX
Data(D/Q)
(DQ0 - DQ7)
VOH
High - Z
Data Output
VOL
Valid
High - Z
Output
tAVQV
tFLQZ
Data(D/Q)
(DQ8 - DQ15)
VOH
VOL
High - Z
Valid
High - Z
Output
Rev. 1.00
LRS1329A
19
Write Cycle Timing Chart (F-WE Controlled)
1
2
3
4
AIN
AIN
5
6
VIH
Address(A)
VIL
tAVAV
tAVWH
tWHAX
VIH
F-CE(E)
VIL
tELWL
tWHEH
tWHGL
VIH
F-OE(G)
VIL
tWHWL
tWHQV1,2,3,4
VIH
F-WE(W)
VIL
VOH
Data(D/Q)
tWLWH
tDVWH
tWHDX
High - Z
VOL
Data
Valid
SRD
DIN
DIN
tFVWH
DIN
tWHFV
VIH
F-BYTE(F)
VIL
tWHRL
High-Z
F-RY/BY(R) ("1")
(SR.7)
VOL
("0")
tSHWH
tQVSL
tPHHWH
tQVPH
VIH
F-WP(S)
VIL
tPHWL
VHH
F-RP(P)
VIH
VIL
tVPWH
tQVVL
VPPH
F-VPP(V)
VPPLK
VIL
Notes:
1. F-VCC power-up and standby.
2. Write each setup command.
3. Write each comfirm command or valid address and data.
4. Automated erase or program delay
5. Read status register data.
6. Write Read Array command.
Rev. 1.00
LRS1329A
20
Write Cycle Timing Chart (F-CE Controlled)
1
2
3
4
AIN
AIN
5
6
VIH
Address(A)
VIL
tAVAV
tAVEH
tEHAX
VIH
F-CE(E)
tEHEL
VIL
tELEH
tDVEH
tEHGL
VIH
F-OE(G)
VIL
tEHQV1,2,3,4
VIH
F-WE(W)
VIL
tWLEL
VOH
Data(D/Q)
High - Z
tEHWH
tEHDX
Data
Valid
SRD
DIN
DIN
VOL
tFVEH
DIN
tEHFV
VIH
F-BYTE(F)
VIL
F-RY/BY(R)
(SR.7)
tEHRL
High-Z
("1")
VOL
("0")
tSHEH
tQVSL
tPHHWH
tQVPH
VIH
F-WP(S)
VIL
tPHWL
VHH
F-RP(P)
VIH
VIL
tVPEH
tQVVL
VPPH
F-VPP(V)
VPPLK
VIL
Notes:
1. F-VCC power-up and standby.
2. Write each setup command.
3. Write each comfirm command or valid address and data.
4. Automated erase or program delay
5. Read status register data.
6. Write Read Array command.
Rev. 1.00
LRS1329A
21
12.7 Reset Operations(1,2)
(TA = -25°C to +85°C, F-VCC = 2.7V to 3.6V)
Symbol
Parameter
Notes
tPLPH
F-RP Pulse Low Time
(If F-RP is tied to F-VCC, this specification is not applicable.)
tPLRZ
F-RP Low to Reset during Block Erase or Word/Byte Write
tVPH
F-VCC = 2.7V to F-RP High
Min.
Max.
100
ns
23.6
3
100
Unit
µs
ns
Notes:
1. If F-RP is asserted while a block erase or word/byte write operation is not executing, the reset will complete within 100ns.
2. A reset time, tPHQV, is required from the later of F-RY/BY(SR.7) going High-Z (“1”) or F-RP going high until outputs are
valid. Refer to AC Characteristics-Read Cycle for tPHQV.
3. When the device power-up, holding F-RP low minimum 100ns is required after F-VCC has been in predefined range and also
has been in stable there.
AC Waveform for Reset Operation
High-Z
F-RY/BY(R) ("1")
(SR.7)
VOL
("0")
VIH
F-RP(P)
VIL
High-Z
F-RY/BY(R) ("1")
(SR.7)
tPLPH
(A) Reset During Read Array Mode
VOL
("0")
tPLRZ
VIH
F-RP(P)
VIL
tPLPH
(B) Reset During Block Erase or Word/Byte Write
2.7V
F-VCC
VIL
tVPH
VIH
F-RP(P)
VIL
(C) F-RP Rising Timing
Rev. 1.00
LRS1329A
22
13. AC Electrical Characteristics for SRAM
13.1 AC Test Conditions
Input pulse level
0.4V to 2.2V
Input rise and fall time
5ns
Input and Output timing Ref. level
1.5V
1TTL + CL (30pF)(1)
Output load
Note:
1. Including scope and socket capacitance.
13.2 Read Cycle
(TA = -25°C to +85°C, S-VCC = 2.7V to 3.6V)
Symbol
Parameter
Notes
Min.
Max.
Unit
tRC
Read Cycle Time
tAA
Address access time
85
ns
tACE1
Chip enable access time (S-CE1)
85
ns
tACE2
Chip enable access time (S-CE2)
85
ns
tOE
Output enable to output valid
45
ns
tOH
Output hold from address change
tLZ1
S-CE1 Low to output active
tLZ2
85
ns
10
ns
1
10
ns
S-CE2 Low to output active
1
10
ns
tOLZ
S-OE Low to output active
1
5
ns
tHZ1
S-CE1 High to output in High-Z
1
0
25
ns
tHZ2
S-CE2 High to output in High-Z
1
0
25
ns
tOHZ
S-OE High to output in High-Z
1
0
25
ns
Note:
1. Active output to High-Z and High-Z to output active tests specified for a ±200mV transition from steady state levels into the
test load.
13.3 Write Cycle
(TA = -25°C to +85°C, S-VCC = 2.7V to 3.6V)
Symbol
Parameter
Notes
Min.
Max.
Unit
tWC
Write cycle time
85
ns
tCW
Chip enable to end of write
70
ns
tAW
Address valid to end of write
70
ns
tAS
Address setup time
0
ns
tWP
Write pulse width
60
ns
tWR
Write recovery time
0
ns
tDW
Input data setup time
35
ns
tDH
Input data hold time
0
ns
tOW
S-WE High to output active
1
5
ns
tWZ
S-WE Low to output in High-Z
1
0
25
ns
Note:
1. Active output to High-Z and High-Z to output active tests specified for a ±200mV transition from steady state levels into the
test load.
Rev. 1.00
LRS1329A
23
13.4 SRAM AC Characteristics Timing Chart
Read cycle timing chart
Device
VIH
Standby
Address Selection
Data Valid
Address Stable
Address
VIL
tRC
VIH
S-CE1
VIL
tLZ1,2
tHZ1,2
VIH
S-CE2
tACE1,2
VIL
tOLZ
VIH
tOHZ
tOE
S-OE
VIL
VIH
S-WE
VIL
tAA
tOH
VOH
High - Z
DQOUT
Data Valid
High - Z
VOL
Rev. 1.00
LRS1329A
24
Write cycle timing chart (S-OE Controlled)
Device
VIH
Address Selection
Standby
Address
Data Valid
Address Stable
VIL
tWC
VIH
S-OE
VIL
tAW
tWR
(4)
VIH
S-CE1
VIL
tCW
(2)
VIH
S-CE2
VIL
tAS
(3)
tWP
(1)
VIH
S-WE
VIL
tOHZ
VOH
DQOUT
tOW
Data Undefined
(6,7)
VOL
tDW
VIH
DQIN
(5)
High - Z
tDH
Data Valid
VIL
Notes:
1. A write occurs during the overlap of a low S-CE1, a high S-CE2 and a low S-WE.
A write begins at the latest transition among S-CE1 going low, S-CE2 going high and S-WE going low.
A write ends at the earliest transition among S-CE1 going high, S-CE2 going low and S-WE going high.
tWP is measured from the beginning of write to the end of write.
2. tCW is measured from the later of S-CE1 going low or S-CE2 going high to the end of write.
3. tAS is measured from the address valid to beginning of write.
4. tWR is measured from the end of write to the address change. t WR applies in case a write ends at S-CE1
going high, S-CE2 going low or S-WE going high.
5. During this period DQ pins are in the output state, therefore the input signals of opposite phase to the
outputs must not be applied.
6. If S-CE1 goes low or S-CE2 goes high simultaneously with S-WE going low or after S-WE going low,
the outputs remain in high impedance state.
7. If S-CE1 goes high or S-CE2 goes low simultaneously with S-WE going high or before S-WE going high,
the outputs remain in high impedance state.
Rev. 1.00
LRS1329A
25
Write cycle timing chart (S-OE Low fixed)
Device
VIH
Address Selection
Standby
Address
Data Valid
Address Stable
VIL
tWC
tAW
tWR
(4)
VIH
S-OE
VIL
VIH
S-CE1
VIL
tAS
(3)
tCW
(2)
VIH
S-CE2
VIL
tAS
(3)
tWP
(1)
VIH
S-WE
VIL
tWZ
VOH
DQOUT
tOW
Data Undefined
(6,7)
VOL
tDW
VIH
DQIN
(5)
High - Z
tDH
Data Valid
VIL
Notes:
1. A write occurs during the overlap of a low S-CE1, a high S-CE2 and a low S-WE.
A write begins at the latest transition among S-CE1 going low, S-CE2 going high and S-WE going low.
A write ends at the earliest transition among S-CE1 going high, S-CE2 going low and S-WE going high.
tWP is measured from the beginning of write to the end of write.
2. tCW is measured from the later of S-CE1 going low or S-CE2 going high to the end of write.
3. tAS is measured from the address valid to beginning of write.
4. tWR is measured from the end of write to the address change. t WR applies in case a write ends at S-CE1
going high, S-CE2 going low or S-WE going high.
5. During this period DQ pins are in the output state, therefore the input signals of opposite phase to the
outputs must not be applied.
6. If S-CE1 goes low or S-CE2 goes high simultaneously with S-WE going low or after S-WE going low,
the outputs remain in high impedance state.
7. If S-CE1 goes high or S-CE2 goes low simultaneously with S-WE going high or before S-WE going high,
the outputs remain in high impedance state.
Rev. 1.00
LRS1329A
26
14. Data Retention Characteristics for SRAM
(TA = -25°C to +85°C)
Typ.(1)
Symbol
Parameter
Note
Min.
Max.
Unit
VCCDR
Data Retention Supply voltage
2
2.0
ICCDR
Data Retention Supply current
2
3.6
V
S-CE2 ≤ 0.2V or
S-CE1 ≥ S-VCC - 0.2V
30
µA
S-VCC = 3.0V
S-CE2 ≤ 0.2V or
S-CE1 ≥ S-VCC - 0.2V
tCDR
Chip enable setup time
0
ns
tR
Chip enable hold time
5
ms
1
Conditions
Notes
1. Reference value at TA = 25°C, S-VCC = 3.0V.
2. S-CE1 ≥ S-VCC - 0.2V, S-CE2 ≥ S-VCC - 0.2V (S-CE1 controlled) or S-CE2 ≤ 0.2V (S-CE2 controlled).
Data Retention timing chart (S-CE1 Controlled)(1)
Data Retention mode
S-VCC
2.7V
tR
tCDR
2.2V
VCCDR
S-CE1
S-CE1
≥ S-V
CC
-0.2V
0V
Note:
1. To control the data
retention mode at S-CE 1, fix the input level of
S-CE2 between VCCDR and VCCDR-0.2V or 0V or 0.2V and during the data retention mode.
Data Retention timing chart (S-CE2 Controlled)
Data Retention mode
S-VCC
2.7V
S-CE2
tCDR
tR
VCCDR
0.4V
0V
S-CE2
≤ 0.2V
Rev. 1.00
LRS1329A
27
15. Notes
This product is a stacked CSP package that a 16M (x8/x16) bit Flash Memory and a 2M (x8) bit SRAM are assembled into.
- Supply Power
Maximum difference (between F-VCC and S-VCC) of the voltage is less than 0.3V.
- Power Supply and Chip Enable of Flash Memory and SRAM
S-CE1 should not be “low” and S-CE2 should not be “high” when F-CE is “low” simultaneously.
If the two memories are active together, possibly they may not operate normally by interference noises or data collision
on DQ bus.
Both F-VCC and S-VCC are needed to be applied by the recommended supply voltage at the same time expect SRAM
data retention mode.
- Power Up Sequence
When turning on Flash memory power supply, keep F-RP “low”. After F-VCC reaches over 2.7V, keep F-RP “low” for
more than 100nsec.
- Device Decoupling
The power supply is needed to be designed carefully because one of the SRAM and the Flash Memory is in standby
mode when the other is active. A careful decoupling of power supplies is necessary between SRAM and Flash
Memory. Note peak current caused by transition of control signals (F-CE, S-CE1, S-CE2).
Rev. 1.00
LRS1329A
28
16. Flash Memory Data Protection
Noises having a level exceeding the limit specified in the specification may be generated under specific operating
conditions on some systems. Such noises, when induced onto F-WE signal or power supply, may be interpreted as
false commands, causing undesired memory updating. To protect the data stored in the flash memory against
unwanted writing, systems operating with the flash memory should have the following write protect designs, as
appropriate.
■ The below describes data protection method.
1. Protecting data in specific block
• By setting a F-WP to low, only the boot block can be protected against overwriting. Parameter and main
blocks cannot be locked. System program, etc., can be locked by storing them in the boot block.
• When a high voltage (VHH) is applied to F-RP, overwrite operation is enabled for all blocks.
• For further information on controlling of F-WP and F-RP refer to the specification.
(See Chapter 5. Command Definitions for Flash Memory)
2. Data Protection through F-VPP
• When the level of F-VPP is lower than VPPLK (lockout voltage), write operation on the flash memory is
disabled. All blocks are locked and the data in the blocks are completely write protected.
• For the lockout voltage, refer to specification. (See Chapter 11. DC Electrical Characteristics)
■ Data Protection during voltage transition
1. Data protection thorough F-RP
• When the F-RP is kept low during power up and power down sequence, write operation on the flash memory
is disabled, write protecting all blocks.
• For the details of F-RP control, refer to the specification. (See Chapter 12. AC Electrical Characteristics for
Flash Memory)
Rev. 1.00
LRS1329A
29
17. Design Considerations
1. Power Supply Decoupling
To avoid a bad effect to the system by flash memory power switching characteristics, each device should have a
0.1µF ceramic capacitor connected between its F-VCC and GND and between its F-VPP and GND. Low
inductance capacitors should be placed as close as possible to package leads.
2. F-VPP Trace on Printed Circuit Boards
Updating the memory contents of flash memories that reside in the target system requires that the printed
circuit board designer pay attention to the F-VPP Power Supply trace. Use similar trace widths and layout
considerations given to the F-VCC power bus.
3. The Inhibition of Overwrite Operation
Please do not execute reprogramming “0” for the bit which has already been programed “0”. Overwrite
operation may generate unerasable bit.
In case of reprogramming “0” to the data which has been programed “1”.
• Program “0” for the bit in which you want to change data from “1” to “0”.
• Program “1” for the bit which has already been programmed “0”.
For example, changing data from “1011110110111101” to “1010110110111100” requires “1110111111111110”
programming.
4. Power Supply
Block erase and word/byte write with an invalid F-VPP (See Chapter 11.DC Electrical Characteristics) produce
spurious results and should not be attempted.
Device operations at invalid F-VCC voltage (See Chapter 11.DC Electrical Characteristics) produce spurious
results and should not be attempted.
18. Related Document Information(1)
Document No.
FUM99903
Document Name
LH28F400BV, LH28F800BV, LH28F160BV Appendix
Note:
1. International customers should contact their local SHARP or distribution sales offices.
Rev. 1.00
SPECIFICATIONS ARE SUBJECT TO CHANGE WITHOUT NOTICE.
Suggested applications (if any) are for standard use; See Important Restrictions for limitations on special applications. See Limited Warranty
for SHARP’s product warranty. The Limited Warranty is in lieu, and exclusive of, all other warranties, express or implied. ALL EXPRESS
AND IMPLIED WARRANTIES, INCLUDING THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR USE AND FITNESS FOR A
PARTICULAR PURPOSE, ARE SPECIFICALLY EXCLUDED. In no event will SHARP be liable, or in any way responsible, for any incidental
or consequential economic or property damage.
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