SHARP LRS1331

LRS1331
Stacked Chip
16M Flash Memory and 4M SRAM
Data Sheet
FEATURES
– Thirty-one 32K-word main blocks
– Bottom boot location
– Extended cycling capability
– 100,000 block erase cycles
– Enhanced automated suspend options
– Word write suspend to read
– Block erase suspend to word write
– Block erase suspend to read
• Flash Memory and SRAM
• Stacked Die Chip Scale Package
• 72-ball 8 mm × 11 mm CSP plastic package
• Power supply: 2.7 V to 3.6 V
• Operating temperature: -25°C to +85°C
• Flash Memory
– Access time (MAX.): 90 ns
– Operating current (MAX.)
(The current for F-VCC pin and F-VCCW pin):
– Read: 25 mA (tCYCLE = 200 ns)
– Word write: 57 mA
– Block erase: 42 mA
– Standby current (the current for F-VCC pin): 15 µA
(MAX. F-RP ≤ GND ± 0.2 V)
– Optimized array blocking architecture
– Two 4K-word boot blocks
– Six 4K-word parameter blocks
• SRAM
– Access time (MAX.): 85 ns
– Operating current: 45 mA (MAX.)
– Standby current: 15 µA (MAX.)
– Data retention current: 2 µA (MAX.)
DESCRIPTION
The LRS1331 is a combination memory organized as
1,048,576 × 16-bit flash memory and 262,144 × 16-bit
static RAM in one package.
PIN CONFIGURATION
72-BALL FBGA
TOP VIEW
INDEX
A
1
2
3
4
5
6
7
8
9
10
11
12
NC
NC
NC
A11
A15
A14
A13
A12
F-GND
NC
NC
NC
A16
A8
A10
A9
DQ15 S-WE DQ14
DQ7
NC
NC
B
C
F-WE F-RY/
BY
T1
D
GND F-RP
T2
E
F-WP
F
S-LB S-UB S-OE
NC
G
F-A18
F-A17
A7
A6
NC
A5
A4
A0
H
NC
NC
S-A17 DQ13
T4
F-VPP F-A19 DQ11
DQ6
DQ4
DQ5
DQ12 S-CE2 S-VCC F-VCC
T3
DQ10 DQ2
DQ3
DQ9
DQ8
DQ0
DQ1
A3
A2
A1
S-CE1
F-CE F-GND F-OE
NC
NOTE: All F-GND and S-GND pins are connected on the board.
Two NC pins at the corner are connected.
LRS1331-1
Figure 1. LRS1331 Pin Configuration
Data Sheet
1
LRS1331
Stacked Chip (16M Flash & 4M SRAM)
F-VCC F-VPP F-GND
F-A17 to
F-A19
A0 to A16
F-RY/BY
F-CE
F-OE
16M (x16) BIT
FLASH MEMORY
F-WE
F-RP
F-WP
DQ0 to
DQ15
S-A17
S-CE1
S-CE2
S-OE
4M (x16) BIT
SRAM
S-WE
S-UB
S-LB
S-VCC
S-GND
LRS1331-2
Figure 2. LRS1331 Block Diagram
2
Data Sheet
Stacked Chip (16M Flash & 4M SRAM)
LRS1331
Table 1. Pin Descriptions
PIN
A0 to A16
DESCRIPTION
TYPE
Address Inputs (Common)
Input
F-A17 to F-A19
Address Inputs (Flash)
Input
S-A17
Address Input (SRAM)
Input
F-CE
Chip Enable Input (Flash)
Input
Chip Enable Inputs (SRAM)
Input
F-WE
Write Enable Input (Flash)
Input
S-WE
Write Enable Input (SRAM)
Input
F-OE
Output Enable Input (Flash)
Input
S-OE
Output Enable Input (SRAM)
Input
S-LB
SRAM Byte Enable Input (DQ0 to DQ7)
Input
S-UB
SRAM Byte Enable Input (DQ8 to DQ15)
Input
F-RP
Deep Power Down Input (Flash)
Block erase and Word Write: VIH
Read: VIH
Deep Power Down: VIL
Input
F-WP
Write Protect Input (Flash)
Two Boot Blocks Locked: VIL
Input
S-CE1, S-CE2
F-RY/BY
DQ0 to DQ15
Data Input and Outputs (Common)
Output
Input/Output
F-VCC
Power Supply (Flash)
Power
S-VCC
Power Supply (SRAM)
Power
F-VPP
Write, Erase Power Supply (Flash)
Block Erase and Word Write: F-VPP = VPPLK
All Blocks Locked: F-VPP < VPPLK
Power
F-GND
Ground (Flash)
Power
S-GND
Ground (SRAM)
Power
NC
No Connection
—
Test Pins (Should be Open)
—
T1 to T5
Data Sheet
Ready/Busy Output(Flash)
During an Erase or Write operation: VOL
Block Erase and Word Write Suspend: HIGH-Z
Deep Power Down: VOH
3
LRS1331
Stacked Chip (16M Flash & 4M SRAM)
Table 2. Truth Table1
SRAM
F-CE
F-RP
F-OE
F-WE
Read
Standby
L
H
L
H
Output Disable
Standby
L
H
H
H
Write
Standby
L
H
H
L
Read
H
H
X
X
L
Output
Disable
H
H
X
X
L
H
H
X
X
Write
H
H
X
X
Read
X
L
X
Output
Disable
X
L
X
X
L
X
X
Write
X
L
X
X
Standby
Standby
H
H
X
X
Reset
Standby
X
L
X
X
FLASH
Standby
Reset
S-CE1
S-CE2
X
X
X
X
X
X
H
L
H
H
H
H
X
X
HIGH-Z
L
H
X
X
H
H
HIGH-Z
L
H
L
L
X
L
H
L
H
X
L
H
H
H
X
L
H
X
X
H
L
H
L
L
See Note 4
NOTES:
1. L = VIL, H = VIH, X = H or L. Refer to DC Characteristics.
2. Refer to the ‘Flash Memory Command Definition’ section for valid
address input and DIN during a write operation.
3. F-WP set to VIL or VIH.
4. SRAM standby data. See Table 2a.
X
X
X
X
DOUT
See Note 4
Standby
(SRAM)
4
NOTES
2, 3
HIGH-Z
3
DIN
2, 3, 5, 6
See Note 7
See Note 7
X
HIGH-Z
H
HIGH-Z
See Note 7
See Note 4
HIGH-Z
3
HIGH-Z
3
5. Command writes involving block erase or word write are reliably
executed when VCCWH (2.7 V to 3.6 V) and F-VCC = 2.7 V to
3.6 V. Block erase or word write with F-VCCW < VCCWH (MIN.)
produce spurious results and should not be attempted.
6. Never hold F-OE LOW and F-WE LOW at the same timing.
7. S-LB, S-UB Control Mode. See Table 2b.
Table 2a.
MODE
S-UB
DQ8 DQ15
S-WE
See Note 4
S-LB
DQ0 DQ7
S-OE
Table 2b.
PINS
S-CE1
S-CE2
S-LB
S-UB
H
X
X
X
X
L
X
X
X
X
H
H
MODE
(SRAM)
Read/Write
PINS
S-LB
S-UB
DQ0 - DQ7
DQ8 - DQ15
L
L
DOUT/DIN
DOUT/DIN
L
H
DOUT/DIN
HIGH-Z
H
L
HIGH-Z
DOUT/DIN
Data Sheet
Stacked Chip (16M Flash & 4M SRAM)
LRS1331
Table 3. Command Definition for Flash Memory1
COMMAND
FIRST BUS CYCLE
SECOND BUS CYCLE
BUS CYCLES
REQUIRED
OPERATION2
ADDRESS3
DATA3
1
Write
XA
FFH
Read Array/Reset
OPERATION2
ADDRESS3
DATA3
NOTES
Read Identifier Codes
≥2
Write
XA
90H
Read
IA
ID
Read Status Register
2
Write
XA
70H
Read
XA
SRD
Clear Status Register
1
Write
XA
50H
Block Erase
2
Write
BA
20H
Write
BA
D0H
Full Chip Erase
2
Write
XA
30H
Write
XA
D0H
Word Write
2
Write
WA
40H or 10H
Write
WA
WD
Block Erase and Word
Write Suspend
1
Write
XA
B0H
5
Block Erase and
Write Resume
1
Write
XA
D0H
5
Set Block Lock-Bits
2
Write
BA
60H
Write
BA
01H
6
Clear Block Lock-Bits
2
Write
XA
60H
Write
XA
D0H
6, 7
Set Permanent Lock-Bits
2
Write
XA
60H
Write
XA
F1H
4
5
5
NOTES:
1. Commands other than those shown in table are reserved by SHARP for future device
implementations and should not be used.
2. BUS operations are defined in Table 2.
3. XA = Any valid address within the device;
IA = Identifier code address;
BA = Address within the block being erased;
WA = Address of memory location to be written;
SRD = Data read from status register;
WD = Data to be written at location WA. Data is latched on the
rising edge of F-WE or F-CE (whichever goes HIGH first);
ID = Data read from identifier codes.
4. See Table 4 for Identifier Codes.
5. See Table 5 for Write Protection Alternatives.
6. If the permanent lock-bit is set, Set Block Lock-Bit and Clear Block Lock-Bits commands cannot be done.
7. The clear block lock-bits operation simultaneously clears all block lock-bits.
Table 4. Identifier Codes
ADDRESS (A0 - A19)
DATA (DQ0 - DQ7)1
Manufacture Code
00000H
B0H
Device Code
00001H
E9H
Block is Unlocked
BA + 2
DQ0 = 0
2
Block is Locked
BA + 2
DQ0 = 1
2
Device is Unlocked
00003H
DQ0 = 0
Device is Locked
00003H
DQ0 = 1
CODES
Block Lock
Configuration
Permanent Lock
Configuration
NOTES
NOTES:
1. DQ8 - DQ15 outputs 00H in word mode. DQ1 - DQ7 are reserved for future use.
2. BA selects the specific block lock configuration code to be read. See Figure 3
for the device identifier code memory map.
Data Sheet
5
LRS1331
Stacked Chip (16M Flash & 4M SRAM)
Table 5. Write Protection Alternatives
OPERATION
Block Erase or
Word Write
PERMANENT
BLOCK
LOCK-BIT
LOCK-BIT
F-RP
≤ VCCWLK
X
X
X
X
All blocks locked
VIL
X
X
X
All blocks locked
> VCCWLK
0
VIH
X
1
≤ VCCWLK
Full Chip Erase
> VCCWLK
≤ VCCWLK
Set Block
Lock-Bit
> VCCWLK
≤ VCCWLK
Clear Block
Lock-Bit
> VCCWLK
≤ VCCWLK
Set Permanent
Lock-Bit
6
F-WP
F-VCCW
> VCCWLK
EFFECT
VIL
Two boot blocks locked
VIH
Block Erase and Word Write enabled
VIL
Block Erase and Word Write disabled
VIH
Block Erase and Word Write disabled
X
X
X
X
All blocks locked
VIL
X
X
X
All blocks locked
VIH
X
VIL
All unlocked blocks are erased. Two boot
blocks and locked blocks are not erased
VIH
All unlocked blocks are erased. Locked blocks
are not erased
X
X
X
X
X
Set block lock-bit disabled
VIL
X
X
X
Set block lock-bit disabled
0
X
X
Set block lock-bit enabled
1
X
X
Set block lock-bit disabled
X
X
X
X
Clear block lock-bits disabled
VIL
X
X
X
Clear block lock-bits disabled
0
X
X
Clear block lock-bits enabled
1
X
X
Clear block lock-bits disabled
X
X
X
X
Set permanent lock-bit disabled
VIL
X
X
X
Set permanent lock-bit disabled
VIH
X
X
X
Set permanent lock-bit enabled
VIH
VIH
Data Sheet
Stacked Chip (16M Flash & 4M SRAM)
LRS1331
Table 6. Status Register Definition
WSMS
BESS
ECBLBS
WBWSLBS
VCCWS
WBWSS
DPS
R
7
6
5
4
3
2
1
0
SR.7 = Write State Machine Status (WSMS)
1 = Ready
0 = Busy
SR.6 = Erase Suspend Status (BESS)
1 = Block Erase Suspended
0 = Block Erase in Progress/Completed
SR.5 = Erase and Clear Block
Lock-Bits Status (ECBLBS)
1 = Error in Block Erase, Bank Erase or
Clear Block Lock-Bits
0 = Successful Block Erase, Bank Erase or
Clear Block Lock-Bits
SR.4 = Word/Byte Write and Set Lock-Bit
Status (WBWSLBS)
1 = Error in Word/Byte Write or Set
Block/Permanent Lock-Bit
0 = Successful Word/Byte Write or Set
Block/Permanent Lock-Bit
NOTES:
1. Check SR.7 to determine block erase, bank erase, word/byte
write or lock-bit configuration completion. SR.6 - SR.0 are invalid
while SR.7 = 0.
2. If both SR.5 and SR.4 are ‘1’s after a block erase, bank erase or
lock-bit configuration attempt, an improper command sequence
was entered.
3. SR.3 does not provide a continuous indication of F-VCCW level.
The WSM interrogates and indicates the F-VCCW level only after
block erase, bank erase, word/byte write or lock-bit configuration
command sequences. SR.3 is not guaranteed to report accurate
feedback only when F-VCCW ≠ F-VCCWH.
4. SR.1 does not provide a continuous indication of permanent and
block lock-bit and F-WP values. The WSM interrogates the permanent lock-bit, block lock-bit and F-WP only after block erase, bank
erase, word/byte write or lock-bit configuration command
sequences. It informs the system, depending on the attempted
operation, if the block lock-bit is set, permanent lock-bit is set and/
or F-WP is VIL. Reading the block lock and permanent lock configruation codes after writing the Read Identifier codes command
indicates permanent and block lock-bit status..
5. SR.0 is reserved for future use and should be masked out when
polling the status register.
SR.3 = VCCW Status (VCCWS)
1 = VCCW LOW Detect, Operation Abort
0 = VCCW Okay
SR.2 = Word/Byte Write Suspend Status (WBWSS)
1 = Word/Byte Write Suspended
0 = Word/Byte Write in Progress/Completed
SR.1 = Device Protect Status (DPS)
1 = Block Lock-Bits, Permanent Lock-Bits
and/or F-WP Lock Detected, Operation Abort
0 = Unlock
SR.0 = Reserved for future enhancements (R)
Data Sheet
7
LRS1331
Stacked Chip (16M Flash & 4M SRAM)
MEMORY MAP
[A0 - A19]
FFFFF
F8000
F7FFF
F0000
EFFFF
E8000
E7FFF
E0000
DFFFF
D8000
D7FFF
D0000
CFFFF
C8000
C7FFF
C0000
BFFFF
B8000
B7FFF
B0000
AFFFF
A8000
A7FFF
A0000
9FFFF
98000
97FFF
90000
8FFFF
88000
87FFF
80000
7FFFF
78000
77FFF
70000
6FFFF
68000
67FFF
60000
5FFFF
58000
57FFF
50000
4FFFF
48000
47FFF
40000
3FFFF
38000
37FFF
30000
2FFFF
28000
27FFF
20000
1FFFF
18000
17FFF
10000
0FFFF
08000
07FFF
07000
06FFF
06000
05FFF
05000
04FFF
04000
03FFF
03000
02FFF
02000
01FFF
01000
00FFF
00000
32K-WORD MAIN BLOCK
30
32K-WORD MAIN BLOCK
29
32K-WORD MAIN BLOCK
28
32K-WORD MAIN BLOCK
27
32K-WORD MAIN BLOCK
26
32K-WORD MAIN BLOCK
25
32K-WORD MAIN BLOCK
24
32K-WORD MAIN BLOCK
23
32K-WORD MAIN BLOCK
22
32K-WORD MAIN BLOCK
21
32K-WORD MAIN BLOCK
20
32K-WORD MAIN BLOCK
19
32K-WORD MAIN BLOCK
18
32K-WORD MAIN BLOCK
17
32K-WORD MAIN BLOCK
16
32K-WORD MAIN BLOCK
15
32K-WORD MAIN BLOCK
14
32K-WORD MAIN BLOCK
13
32K-WORD MAIN BLOCK
12
32K-WORD MAIN BLOCK
11
32K-WORD MAIN BLOCK
10
32K-WORD MAIN BLOCK
9
32K-WORD MAIN BLOCK
8
32K-WORD MAIN BLOCK
7
32K-WORD MAIN BLOCK
6
32K-WORD MAIN BLOCK
5
32K-WORD MAIN BLOCK
4
32K-WORD MAIN BLOCK
3
32K-WORD MAIN BLOCK
2
32K-WORD MAIN BLOCK
1
32K-WORD MAIN BLOCK
0
4K-WORD PARAMETER BOOT BLOCK 5
4K-WORD PARAMETER BOOT BLOCK 4
4K-WORD PARAMETER BOOT BLOCK 3
4K-WORD PARAMETER BOOT BLOCK 2
4K-WORD PARAMETER BOOT BLOCK 1
4K-WORD PARAMETER BOOT BLOCK 0
4K-WORD BOOT BLOCK
1
4K-WORD BOOT BLOCK
0
BOTTOM BOOT
LRS1331-3
Figure 3. Memory Map for Flash Memory
8
Data Sheet
Stacked Chip (16M Flash & 4M SRAM)
LRS1331
ABSOLUTE MAXIMUM RATINGS
PARAMETER
SYMBOL
RATINGS
UNIT
NOTES
Supply voltage
VCC
-0.2 to +4.6
V
1
Input voltage
VIN
-0.2 to VCC +0.3
V
1, 2, 3
Operating temperature
TOPR
-25 to +85
°C
Storage temperature
TSTG
-65 to +125
°C
F-VCCW
-0.5 to +4.6
V
F-VCCW voltage
1, 3
NOTES:
1. The maximum applicable voltage on any pins with respect to GND.
2. Except F-VCC, F-VCCW.
3. -2.0 V undershoot is allowed when the pulse width is less than 20 ns.
RECOMMENDED DC OPERATING CONDITIONS
TA = -25°C to +85°C
PARAMETER
SYMBOL
MIN.
TYP.
MAX.
UNIT
Supply voltage
VCC
2.7
3.0
3.6
V
VIH
2.2
VCC + 0.2
V
1
VIL
-0.3
0.6
V
2
Input voltage
NOTES
NOTES:
1. VCC is the lower one of S-VCC and F-VCC.
2. -2.0 V undershoot is allowed when the pulse width is less than 20 ns.
PIN CAPACITANCE
TA = 25°C, f = 1 MHz
PARAMETER
SYMBOL
CONDITION
Input capacitance*
CIN
I/O capacitance*
CI/O
MIN.
TYP.
MAX.
UNIT
VIN = 0 V
20
pF
VI/O = 0 V
22
pF
NOTE: *Sampled by not 100% tested.
Data Sheet
9
LRS1331
Stacked Chip (16M Flash & 4M SRAM)
DC CHARACTERISTICS
TA = -25°C to + 85°C, VCC = 2.7 V to 3.6 V
PARAMETER
SYMBOL
CONDITION
MIN.
TYP.1
MAX.
UNIT
Input leakage current
ILI
VIN = VCC or GND
-1.5
+1.5
µA
Output leakage current
ILO
VOUT = VCC or GND
-1.5
+1.5
µA
2
15
µA
0.2
2
mA
Standby Current
ICCS
F-CE = F-RP = F-VCC ± 0.2 V
F-WP = F-VCC ± 0.2 V
or F-GND ± 0.2 V
F-CE = F-RP = VIH, F-WP = VIH or VIL
Auto Power-Save Current
Reset/Power-Down Current
F-CE = GND ± 0.2 V
2
15
µA
2, 3
ICCD
F-RP = F-GND ± 0.2 V,
IOUT (F-RY/BY) = 0 mA
2
15
µA
2
CMOS input, F-CE = F-GND,
f = 5 MHz, IOUT = 0 mA
15
25
mA
2
30
mA
2
ICCR
TTL input, F-CE = F-GND,
f = 5 MHz, IOUT = 0 mA
Word Write or Set Lock-Bit Current
ICCW
F-VCCW = VCCWH
5
17
mA
Block Erase, Full Chip Erase or
Clear Block Lock-BIts Current
ICCE
F-VCCW = VCCWH
4
17
mA
F-CE = VIH
1
6
mA
Word Write Block Erase
Suspend Current
ICCWS
ICCES
Standby or Read Current
ICCWS
ICCWR
F-VPP ≤ F-VCC
±2
±15
µA
F-VPP > F-VCC
10
200
µA
Auto Power-Save Current
ICCWAS
F-CE = GND ± 0.2 V
0.1
5
µA
2, 3
Reset/Power-Down Current
ICCWD
F-RP = F-GND ± 0.2 V
0.1
5
µA
2
ICCWW
F-VCCW = VCCWH
12
40
mA
ICCWE
F-VCCW = VCCWH
8
25
mA
ICCWWS
ICCWES
F-VCCW = VCCWH
10
200
µA
F-VCCW Word Write or Set Lock-Bit Current
Block Erase, Full Chip Erase or
Clear Block Lock-Bits Current
Word Write or Block Erase
Suspend Current
Standby Current
S-VCC
Input LOW Voltage
S-CE1, S-CE2 ≥ S-VCC - 0.2 V
or S-CE2 ≤ 0.2 V
15
µA
ISB1
S-CE1 = VIH or S-CE2 = VIL
3
mA
ICC1
S-CE1 = VIL, S-CE2 = VIH, VIN = VIL or
VIH, tCYCLE = MIN., II/O = 0 mA
45
mA
ICC2
S-CE1 = 0.2 V, S-CE2 = S-VCC - 0.2 V,
VIN = S-VCC - 0.2 V, or 0.2 V
tCYCLE = 1 µs, II/O = 0 mA
8
mA
-0.3
0.6
V
2.2
VCC +
0.2
V
0.4
V
V
4
1.5
V
5
3.6
V
VIL
Input HIGH Voltage
VIH
Output LOW Voltage
VOL
IOL = 0.5 mA
VOH1
IOH = -0.5 mA
Output HIGH Voltage (CMOS)
2.2
F-VCCW Lockout during Normal Operations
VCCWLK
F-VCCW during Block Erase, Bank Erase, Word
Write or Lock-Bit Configuration Operations
VCCWH
2.7
VLKO
2.0
F-VCC Lockout Voltage
2
ISB
Operation Current
NOTES:
1. Reference values at VCC = 3.0 V and TA = +25°C.
2. CMOS inputs are either VCC ± 0.2 V or GND ± 0.2 V. TTL inputs
are either VIL or VIH.
3. Automatic Power Savings (APS) feature is placed automatically
power save mode that addresses not switching more than 300 ns
while read mode.
10
2
ICCAS
F-VCC
Read Current
NOTES
4
V
4. Includes F-RY/BY.
5. Block erases and word writes are inhibited when F-VCCW ≤ VCCWLK
and not guaranteed in the range between VCCWLK (MAX.) and
VCCWH (MIN.), and above VCCWH (MAX.).
Data Sheet
Stacked Chip (16M Flash & 4M SRAM)
LRS1331
FLASH MEMORY AC CHARACTERISTICS
AC Test Conditions
PARAMETER
Input pulse level
CONDITION
0 V to 2.7 V
Input rise and fall time
10 ns
Input and Output timing reference level
1.35 V
1TTL + CL (50 pF)
Output load
Read Cycle
TA = -25°C to +85°C, VCC = 2.7 V to 3.6 V
PARAMETER
SYMBOL
MIN.
Read Cycle Time
tAVAV
90
Address to Output Delay
tAVQV
90
ns
F-CE to Output Delay*
tELQV
90
ns
F-RP HIGH to Output Delay
tPHQV
600
ns
F-OE to Output Delay*
tGLQV
40
ns
F-CE to Output in LOW Z
tELQX
F-CE HIGH to Output in HIGH-Z
tEHQZ
F-OE to Output in LOW Z
tGLQX
F-OE HIGH to Output in HIGH-Z
tGHQZ
Output Hold from Address, F-CE or F-OE change,
whichever occurs first
tOH
MAX.
UNIT
ns
0
ns
40
0
ns
ns
15
0
ns
ns
NOTE: *F-OE may be delayed up to tELQV - tGLQV after the falling edge of F-OE without impact on tELQV.
Data Sheet
11
LRS1331
Stacked Chip (16M Flash & 4M SRAM)
Write Cycle (F-WE Controlled)1
TA = -25°C to +85°C, VCC = 2.7 V to 3.6 V
PARAMETER
SYMBOL
MIN.
MAX.
Write Cycle Time
tAVAV
90
ns
F-RP HIGH Recovery to F-WE going to LOW
tPHWL
1
µs
F-CE Setup to F-WE going LOW
tELWL
10
ns
F-WE Pulse Width
tWLWH
50
ns
F-WP VIH Setup to F-WE going HIGH
tSHWH
100
ns
F-VCCW Setup to F-WE going HIGH
tVPWH
100
ns
Address Setup to F-WE going HIGH
tAVWH
50
ns
Data Setup to F-WE going HIGH
tDVWH
50
ns
2
Data Hold from F-WE HIGH
tWHDX
0
ns
2
Address Hold from F-WE HIGH
tWHAX
0
ns
F-CE Hold from F-WE HIGH
tWHEH
10
ns
F-WE Pulse Width HIGH
tWHWL
30
ns
F-WE HIGH to F-RY/BY going LOW
tWHRL
Write Recovery before Read
tWHGL
0
ns
F-VCCW Hold from Valid SRD, F-RY/BY HIGH Z
tQVVL
0
ns
F-WP VIH Hold from Valid SRD, F-RY/BY HIGH
tQVSL
0
ns
100
UNIT
NOTES
ns
NOTES:
1. Read timing characteristics during block erase and word write operations are the same as
during read-only operations. Refer to AC Characteristics for Read Cycle.
2. Refer to the ‘Flash Memory Command Definition’ section for valid AIN and DIN for block erase or word write.
12
Data Sheet
Stacked Chip (16M Flash & 4M SRAM)
LRS1331
Write Cycle (F-CE Controlled)1
TA = -25°C to +85°C, VCC = 2.7 V to 3.6 V
PARAMETER
SYMBOL
MIN.
tAVAV
90
ns
F-RP HIGH Recovery to F-CE going to LOW
tPHEL
1
µs
F-WE Setup to F-CE going LOW
tWLEL
0
ns
F-CE Pulse Width
tELEH
60
ns
F-WP VIH Setup to F-CE going HIGH
tSHEH
100
ns
F-VCCW Setup to F-CE going HIGH
tVPEH
100
ns
Address Setup to F-CE going HIGH
tAVEH
50
ns
Data Setup to F-CE going HIGH
tDVEH
50
ns
2
Data Hold from F-CE HIGH
tEHDX
0
ns
2
Address Hold from F-CE HIGH
tEHAX
0
ns
F-WE Hold from F-CE HIGH
tEHWH
0
ns
F-CE Pulse Width HIGH
tEHEL
20
ns
F-CE HIGH to F-RY/BY going LOW
tEHRL
Write Cycle Time
MAX.
100
UNIT
NOTES
ns
Write Recovery before Read
tEHGL
0
ns
F-VCCW Hold from Valid SRD, F-RY/BY HIGH Z
tQVVL
0
ns
F-WP VIH Hold from Valid SRD, F-RY/BY HIGH
tQVSL
0
ns
NOTES:
1. In system where F-CE defines the pulse width (within a F-WE timing waveform), all setup,
hold, and inactive F-WE times should be measured relative to the F-CE waveform.
2. Refer to the ‘Flash Memory Command Definition’ section for valid AIN and DIN for block erase or word write.
Block Erase and Word Write Performance
TA = -25°C to +85°C, VCC = 2.7 V to 3.6 V
SYMBOL
tWHQV1
tEHQV1
tWHQV2
tEHQV2
PARAMETER
VCCW = 2.7 V to 3.6 V
UNIT
NOTES
200
µs
3
200
µs
3
1.1
2.4
s
3
0.15
0.3
s
3
Block Erase Time 32K-word Block
1.2
6
s
3
Block Erase Time 4K-word Bock
0.6
5
s
3
Full Chip Erase Time
42
210
s
3
TYP.1
MAX.2
Word Write Time 32K-word Block
33
Word Write Time 4K-word Block
36
Block Write Time 32K-word Block
Block Write Time 4K-word Block
MIN.
tWHQV3
tEHQV3
Set Lock-Bit Time
27.6
200
µs
3
tWHQV4
tEHQV4
Clear Block Lock-Bits Time
0.64
5
s
3
tWHRZ1
tEHRZ1
Word Write Suspend Latency Time to Read
6.0
15
µs
tWHRZ2
tEHRZ2
Erase Suspend Latency Time to Read
16.0
30
µs
NOTES:
1. Reference values at TA = +25°C and VCC = 3.0 V, VPP = 3.0 V.
2. Sampled, but not 100% tested.
3. Excludes system-level overhead.
Data Sheet
13
LRS1331
Stacked Chip (16M Flash & 4M SRAM)
FLASH MEMORY AC CHARACTERISTICS TIMING DIAGRAMS
Standby
Device
Address Selection
Data Valid
Address Stable
ADDRESS
tAVAV
F-CE
tEHQZ
F-OE
tGHQZ
tGLQV
F-WE
tELQV
tGLQX
tOH
tELQX
DQ
HIGH Z
HIGH Z
Valid Output
tAVQV
F-VCC
tPHQV
F-RP
LRS1331-4
Figure 4. Read Cycle Timing Diagram
14
Data Sheet
Stacked Chip (16M Flash & 4M SRAM)
1
ADDRESS
LRS1331
2
3
AIN
AIN
tAVAV
4
tAVWH
5
6
tWHAX
F-CE
tELWL t
WHEH
tWHGL
F-OE
tWHWL
tEHQV1, 2, 3, 4
F-WE
tWLWH
tDVWH
tWHDX
HIGH-Z
DQ
DIN
Data
Valid
SRD
DIN
DIN
tWHRL
tPHWL
F-RY/BY
tSHWH
tQVSL
F-WP
F-RP
tVPWH
tQVVL
VCCWH
F-VCCW
VCCWLK
VIL
NOTES:
1. VCC power-up and standby.
2. Write block erase or word write setup.
3. Write block erase confirm or valid address and data.
4. Automated erase or program delay.
5. Read status register data.
6. Write Read Array command.
LRS1331-5
Figure 5. Write Cycle Timing Diagram (F-WE Controlled)
Data Sheet
15
LRS1331
Stacked Chip (16M Flash & 4M SRAM)
1
ADDRESS
2
3
AIN
AIN
tAVAV
4
5
6
Data
Valid
SRD
DIN
tAVEH
tEHAX
F-WE
tWLEL tEHWH
tEHGL
F-OE
tEHEL
tEHQV1, 2, 3, 4
F-CE
tELEH
tDVEH
tEHDX
HIGH-Z
DQ
DIN
DIN
tPHEL
tEHRL
F-RY/BY
tSHEH
tQVSL
F-WP
F-RP
tVPEH
tQVVL
VCCWH
F-VCCW VCCWLK
VIL
NOTES:
1. VCC power-up and standby.
2. Write block erase or word write setup.
3. Write block erase confirm or valid address and data.
4. Automated erase or program delay.
5. Read status register data.
6. Write Read Array command.
LRS1331-6
Figure 6. Write Cycle Timing Diagram (F-CE Controlled)
16
Data Sheet
Stacked Chip (16M Flash & 4M SRAM)
LRS1331
RESET OPERATIONS
TA = -25°C to +85°C, VCC = 2.7 V to 3.6 V
PARAMETER
SYMBOL
MIN.
F-RP Pulse LOW Time (if F-RP is tied to VCC, this
specification is not applicable).
tPLPH
100
F-RP LOW to Reset during Block Erase or Word Write
tPLRZ
F-VCC 2.7 V to F-RP HIGH
tVPH
MAX.
UNIT
NOTES
ns
20
100
µs
1, 2
ns
3
NOTES:
1. If F-RP is asserted while a block erase or word write operation is not executing,
the reset will complete with 100 ns.
2. A reset time tPHQV is required from F-RY/BY going HIGH Z, or F-RP going HIGH until outputs are valid.
3. When the device power-up, holding F-RP LOW minimum 100 ns is required after VCC has been
in predefined range and also has been stable there.
HIGH Z
F-RY/BY (R)
VOL
F-RP (P)
VIH
VIL
tPLPH
A. Reset During Read Array Mode
HIGH Z
F-RY/BY (R)
VOL
tPLRZ
F-RP (P)
VIH
VIL
tPLPH
B. Reset During Block Erase or Word Byte Write
2.7 V
F-VCC
VIL
tVPH
F-RP (P)
VIH
VIL
C. F-RP Rising Timing
1331-7
Figure 7. AC Waveform for Reset Operation
Data Sheet
17
LRS1331
Stacked Chip (16M Flash & 4M SRAM)
SRAM AC ELECTRICAL CHARACTERISTICS
AC Test Conditions
PARAMETER
CONDITION
Input pulse level
0.6 V to 2.2 V
Input rise and fall time
5 ns
Input and Output timing reference level
1.5 V
1TTL + CL (30 pF)
Output load*
NOTE: *Including scope and jig capacitance.
Read Cycle
TA = -25°C to +85°C, VCC = 2.7 V to 3.6 V
PARAMETER
SYMBOL
MIN.
Read Cycle Time
tRC
85
Address Access Time
tAA
85
ns
S-CE1
tACE1
85
ns
S-CE2
tACE2
85
ns
Output Enable to Output Valid
tOE
45
ns
Output hold from address change
tOH
10
ns
S-CE1
tLZ1
10
ns
S-CE2
tLZ2
10
ns
S-OE LOW to Output Active*
tOLZ
5
ns
S-UB or S-LB LOW to Output in HIGH Impedance*
tBLZ
5
ns
S-CE1
tHZ1
0
25
ns
S-CE2
HHZ2
0
25
ns
S-OE HIGH to Output in HIGH Impedance*
tOHZ
0
25
ns
S-UB or S-LB HIGH to Output Active*
tBHZ
0
25
ns
Chip Enable Access Time
S-CE1, S-CE2 LOW to Output Active*
S-CE1, S-CE2 HIGH to Output in
HIGH Impedance*
MAX.
UNIT
ns
NOTE: *Active output to HIGH impedance and HIGH impedance to output active
tests specified for a ±200 mV transition from steady state levels into the test load.
Write Cycle
TA = -25°C to +85°C, VCC = 2.7 V to 3.6 V
PARAMETER
SYMBOL
MIN.
MAX.
Write Cycle Time
tWC
85
ns
Chip Enable to End of Write
tCW
70
ns
Address Valid to End of Write
tAW
70
ns
Address Setup Time
tAS
0
ns
Write Pulse Width
tWP
60
ns
Write Recovery Time
tWR
0
ns
Input Data Setup Time
tDW
35
ns
Input Data Hold Time
tDH
0
ns
S-WE HIGH to Output Active*
tOW
5
ns
S-WE LOW to Output in HIGH Impedance*
tWZ
0
25
UNIT
ns
NOTE: *Active output to HIGH impedance and HIGH impedance to output active
tests specified for a ±200 mV transition from steady state levels into the test load.
18
Data Sheet
Stacked Chip (16M Flash & 4M SRAM)
LRS1331
SRAM AC CHARACTERISTICS TIMING DIAGRAMS
tRC
ADDRESS
tAA
tACE
S-CE1
tLZ
tHZ
S-CE2
tBE
tHZ
S-UB, S-LB
tBLZ
tBHZ
tOE
S-OE
tOHZ
tOLZ
DOUT
Data Valid
tOH
NOTE: S-WE is HIGH for Read Cycle.
1331-8
Figure 8. Read Cycle Timing Diagram
Data Sheet
19
LRS1331
Stacked Chip (16M Flash & 4M SRAM)
tWC
ADDRESS
tAW
tCW
(NOTE 2)
S-CE1
tWR
S-CE2
tBW
(NOTE 3)
S-UB, S-LB
tAS
tWP
(NOTE 4)
(NOTE 1)
tWR
(NOTE 5)
S-WE
tWZ
tOW
(NOTE 7)
(NOTE 8)
DOUT
tDW
tDH
(NOTE 6)
Data Valid
DIN
NOTES:
1. A write occurs during the overlap of a LOW S-CE1, a HIGH S-CE2 and a LOW S-WE,
A write begins at the latest transition among S-CE1 going LOW, S-CE2 going HIGH
and S-WE going LOW. A write ends at the earliest transition among S-CE1 going HIGH,
S-CE2 going LOW and S-WE going HIGH. tWP is measured from the beginning of
write to the end of write.
2. tCW is measured from the later of S-CE1 going LOW or S-CE2 going HIGH to the end
of write.
3. tBW is measured from the time of going LOW S-UB or LOW S-LB to the end of write.
4. tAS is measured from the address valid to the beginning of write.
5. tWR is measured from the end of write to the address change. tWR applied in case a
write ends as S-CE1 going HIGH, S-CE2 going LOW or S-WE going HIGH.
6. During this period, DQ pins are in the output state, therefore the input signals of
opposite phase to the outputs must not be applied.
7. If S-CE1 goes LOW or S-CE2 goes HIGH simultaneously with S-WE going LOW or
after S-WE going LOW, the outputs remain in HIGH impedance state.
8. If S-CE1 goes HIGH or S-CE2 goes LOW simultaneously with S-WE going HIGH or
S-WE going HIGH, the outputs remain in HIGH impedance state.
1331-9
Figure 9. Write Cycle Timing Diagram (S-WE Controlled)
20
Data Sheet
Stacked Chip (16M Flash & 4M SRAM)
LRS1331
tWC
ADDRESS
tAW
tAS
tCW
(NOTE 4)
(NOTE 2)
tWR
S-CE1
tWR
(NOTE 5)
S-CE2
tBW
(NOTE 3)
S-UB, S-LB
tWP
(NOTE 1)
S-WE
DOUT
HIGH IMPEDANCE
tDW
tDH
(NOTE 6)
DIN
Data Valid
NOTES:
1. A write occurs during the overlap of a LOW S-CE1, a HIGH S-CE2 and a LOW S-WE,
A write begins at the latest transition among S-CE1 going LOW, S-CE2 going HIGH
and S-WE going LOW. A write ends at the earliest transition among S-CE1 going HIGH,
S-CE2 going LOW and S-WE going HIGH. tWP is measured from the beginning of
write to the end of write.
2. tCW is measured from the later of S-CE1 going LOW or S-CE2 going HIGH to the end
of write.
3. tBW is measured from the time of going LOW S-UB or LOW S-LB to the end of write.
4. tAS is measured from the address valid to the beginning of write.
5. tWR is measured from the end of write to the address change. tWR applied in case a
write ends as S-CE1 going HIGH, S-CE2 going LOW or S-WE going HIGH.
6. During this period, DQ pins are in the output state, therefore the input signals of
opposite phase to the outputs must not be applied.
1331-10
Figure 10. Write Cycle Timing Diagram (S-CE Controlled)
Data Sheet
21
LRS1331
Stacked Chip (16M Flash & 4M SRAM)
tWC
ADDRESS
tAW
S-OE
tCW
(NOTE 2)
S-CE1
tWR
(NOTE 5)
S-CE2
tAS
tBW
tWR
(NOTE 4)
(NOTE 3)
(NOTE 5)
S-UB, S-LB
tWP
(NOTE 1)
S-WE
DOUT
HIGH IMPEDANCE
tDW
DIN
tDH
Data Valid
NOTES:
1. A write occurs during the overlap of a LOW S-CE1, a HIGH S-CE2 and a LOW S-WE,
A write begins at the latest transition among S-CE1 going LOW, S-CE2 going HIGH
and S-WE going LOW. A write ends at the earliest transition among S-CE1 going HIGH,
S-CE2 going LOW and S-WE going HIGH. tWP is measured from the beginning of
write to the end of write.
2. tCW is measured from the later of S-CE1 going LOW or S-CE2 going HIGH to the end
of write.
3. tBW is measured from the time of going LOW S-UB or LOW S-LB to the end of write.
4. tAS is measured from the address valid to the beginning of write.
5. tWR is measured from the end of write to the address change. tWR applied in case a write ends
as S-CE1 going HIGH, S-CE2 going LOW or S-WE going HIGH.
1331-11
Figure 11. Write Cycle Timing Diagram (S-UB, S-LB Control)
22
Data Sheet
Stacked Chip (16M Flash & 4M SRAM)
LRS1331
SRAM DATA RETENTION CHARACTERISTICS
TA = -25°C to +85°C
CONDITIONS
MIN.
TYP.1
PARAMETER
SYMBOL
Data Retention Supply Voltage
VCCDR
S-CE2 ≤ 0.2 V or
S-CE1 ≥ VCCDR - 0.2 V
Data Retention Supply Current
ICCDR
VCCDR = 1.2 V, S-CE2 ≤ 0.2 V or
S-CE1 ≥ VCCDR - 0.2 V
Chip Enable Setup Time
tCDR
0
ns
Chip Enable Hold Time
tR
tRC
ms
1
MAX.
UNIT
NOTES
3.6
V
2
5
µA
2
NOTES:
1. Reference value at TA = 25°C, S-VCC = 3.0 V.
2. S-CE1 ≥ VCC - 0.2 V, S-CE2 ≥ VCC - 0.2 V (S-CE1 controlled) or S-CE2 ≤ 0.2 V (S-CE2 controlled).
Data Retention Mode
S-VCC
2.7 V
tR
tCDR
2.2 V
VCCDR
S-CE1 ≥ VCCDR - 0.2 V
S-CE1
0V
NOTE: To control the data retention mode at S-CE1, fix the input level of S-CE2 between
VCCDR and VCCDR - 0.2 V, or 0 V and 0.2 V, and during the data retention mode.
1331-12
Figure 12. Data Retention Timing Diagram (S-CE1 Controlled)
Data Retention Mode
S-VCC
2.7 V
tCDR
S-CE2
tR
VCCDR
0.6 V
S-CE2 ≤ 0.2 V
0V
1331-13
Figure 13. Data Retention Timing Diagram (S-CE2 Controlled)
Data Sheet
23
LRS1331
GENERAL DESIGN GUIDELINES
Supply Power
Maximum difference (between F-VCC and S-VCC) of
the voltage is less than 0.3 V.
Stacked Chip (16M Flash & 4M SRAM)
Data Protection Through F-VCCW
When the level of F-VCCW is lower than F-VCCWK
(lockout voltage), write operation on the flash memory
is disabled. All blocks are locked and the data in the
blocks are completely write protected.
Power Supply and Chip Enable of Flash
Memory and SRAM
For the lockout voltage refer to the ‘DC Characteristics’ section.
S-CE1 should not be LOW and S-CE2 should not be
HIGH when F-CE is LOW simultaneously.
Data Protection During Voltage Transition
If the two memories are active together, they may
not operate normally because of interference noises or
data collision on DQ bus.
DATA PROTECTION THROUGH F-RP
When the F-RP is kept LOW during power up and
power down sequence, write operation on the flash
memory is disabled, write protecting all blocks.
Both F-VCC and S-VCC need to be applied by the
recommended supply voltage at the same time except
SRAM data retention mode.
Power Up Sequence
When turning on Flash memory power supply, keep
F-RP LOW. After F-VCC reaches over 2.7 V, keep F-RP
LOW for more than 100 ns.
Device Decoupling
The power supply needs to be designed carefully
because one of the SRAM and the Flash Memory is in
standby mode when the other is active. A careful
decoupling of power supplies is necessary between
SRAM and Flash Memory. Note peak current caused
by transition of control signals (F-CE, S-CE1, S-CE2).
FLASH MEMORY DATA PROTECTION
Noises having a level exceeding the limit specified in
the specification may be generated under specific
operating conditions on some systems.
Such noises, when induced onto F-WE signal or
power supply may be interpreted as false commands,
causing undesired memory updating.
To protect the data store in the flash memory against
unwanted overwriting, systems operating with the flash
memory should have the following write protect
designs, as appropriate:
Protecting Data in Specific Block
For details of F-RP control refer to the ‘Flash Memory AC Electrical Characteristics’ section.
DESIGN CONSIDERATIONS
Power Supply Decoupling
To avoid a bad effect on the system by flash memory
power switching characteristics, each device should
have a 0.1 µF ceramic capacitor connected between its
VCC and GND and between its VCCW and GND. LOW
inductance capacitors should be placed as close as
possible to package leads.
VCCW Trace on Printed Circuit Boards
Updating the memory contents of flash memories
that reside in the target system requires that the printed
circuit board designer pay attention to the VCCW Power
Supply trace. Use similar trace widths and layout considerations given to the VCC power bus.
The Inhibition of Overwrite Operation
Please do not execute reprogramming ‘0’ for the bit
which has already been programmed ‘0’. Overwrite operation may generate unerasable bit. In case of reprogramming ‘0’ to the data which has been programmed ‘1’.
• Program ‘0’ for the bit in which you want to change
data from ‘1’ to ‘0’.
• Program ‘1’ for the bit which has already been programmed ‘0’.
By setting a F-WP to LOW, only the boot block can
be protected against overwriting.
For
example,
changing
data
from
‘1011110110111101’ to ‘1010110110111100’ requires
‘1110111111111110’ programming.
Parameter and main blocks with F-WP cannot be
locked.
Power Supply
System program, etc., can be locked by storing them
in the book block.
For further information on setting/resetting of block
bit, and controlling of F-WP and F-RP, refer to the
specification, see the Command Definitions section.
24
Block erase, full chip erase, word write and lock-bit
configuration with an invalid VCCW (see ‘DC Characteristics’) produce spurious results and should not be
attempted. Device operations at invalid VCC voltage
product spurious results and should not be attempted.
Data Sheet
Stacked Chip (16M Flash & 4M SRAM)
LRS1331
OUTLINE DIMENSIONS
FBGA072-P-0811
B
A
INDEX
8.0 +0.2
-0
TOP VIEW
11.0 +0.2
-0
0.10
S
S
SIDE VIEW
0.40 TYP.
(See Detail)
0.10
S
DETAIL
1.1 TYP.
0.4 TYP.
0.8 TYP.
1.4 MAX.
C
0.35 ±0.05
1.2 TYP.
H
D
BOTTOM VIEW G
F
0.8 TYP.
E
0.4 TYP.
D
C
B
A
1
2
3
4 5
6
7
8 9 10 11 12
φ 0.45 ±0.05
NOTE: Dimensions are in mm.
Data Sheet
φ 0.30 M
S AB
φ 0.15 M
S CD
72FBGA
25
Stacked Chip (16M Flash & 4M SRAM)
LRS1331
LIFE SUPPORT POLICY
SHARP components should not be used in medical devices with life support functions or in safety equipment (or similiar applications where
component failure would result in loss of life or physical harm) without the written approval of an officer of the SHARP Corporation.
LIMITED WARRANTY
SHARP warrants to its Customer that the Products will be free from defects in material and workmanship under normal use and service for a
period of one year from the date of invoice. Customer's exclusive remedy for breach of this warranty is that SHARP will either (i) repair or
replace, at its option, any Product which fails during the warranty period because of such defect (if Customer promptly reported the failure to
SHARP in writing) or, (ii) if SHARP is unable to repair or replace, refund the purchase price of the Product upon its return to SHARP. This
warranty does not apply to any Product which has been subjected to misuse, abnormal service or handling, or which has been altered or
modified in design or construction, or which has been serviced or repaired by anyone other than Sharp. The warranties set forth herein are in
lieu of, and exclusive of, all other warranties, express or implied. ALL EXPRESS AND IMPLIED WARRANTIES, INCLUDING THE
WARRANTIES OF MERCHANTABILITY, FITNESS FOR USE AND FITNESS FOR A PARTICULAR PURPOSE, ARE SPECIFICALLY
EXCLUDED. In no event will Sharp be liable, or in any way responsible, for any incidental or consequential economic or property damage.
The above warranty is also extended to Customers of Sharp authorized distributors with the following exception: reports of failures of Products
during the warranty period and return of Products that were purchased from an authorized distributor must be made through the distributor.
In case Sharp is unable to repair or replace such Products, refunds will be issued to the distributor in the amount of distributor cost.
SHARP reserves the right to make changes in specifications at any time and without notice. SHARP does not assume any responsibility
for the use of any circuitry described; no circuit patent licenses are implied.
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©1999 by SHARP Corporation
Reference Code SMA99087