ETC LRS1360C

PRODUCT SPECIFICATIONS
®
Integrated Circuits Group
LRS1360C
Stacked Chip
16M (x16) Flash and 2M (x16) SRAM
(Model No.: LRS1360C)
Spec No.: EL126089
Issue Date: July 17, 2000
sharp
LRS1360C
• Handle this document carefully for it contains material protected by international copyright law.
Any reproduction, full or in part, of this material is prohibited without the express written permission
of the company.
• When using the products covered herein, please observe the conditions written herein and the
precautions outlined in the following paragraphs. In no event shall the company be liable for
any damages resulting from failure to strictly adhere to these conditions and precautions.
(1) The products covered herein are designed and manufactured for the following application areas.
When using the products covered herein for the equipment listed in Paragraph (2), even for the
following application areas, be sure to observe the precautions given in Paragraph (2). Never use
the products for the equipment listed in Paragraph (3).
•Office electronics
•Instrumentation and measuring equipment
•Machine tools
•Audiovisual equipment
•Home appliance
•Communication equipment other than for trunk lines
(2) Those contemplating using the products covered herein for the following equipment
which demands high reliability, should first contact a sales representative of the company and
then accept responsibility for incorporating into the design fail-safe operation, redundancy, and
other appropriate measures for ensuring reliability and safety of the equipment and the overall
system.
•Control and safety devices for airplanes, trains, automobiles, and other transportation
equipment
•Mainframe computers
•Traffic control systems
•Gas leak detectors and automatic cutoff devices
•Rescue and security equipment
•Other safety devices and safety equipment, etc.
(3) Do not use the products covered herein for the following equipment which demands extremely
high performance in terms of functionality, reliability, or accuracy.
•Aerospace equipment
•Communications equipment for trunk lines
•Control equipment for the nuclear power industry
•Medical equipment related to life support, etc.
(4) Please direct all queries and comments regarding the interpretation of the above three
Paragraphs to a sales representative of the company.
• Please direct all queries regarding the products covered herein to a sales representative of the
company.
Rev. 1.00
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LRS1360C
1
Contents
1. Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
2. Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
3. Truth Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
4. Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
5. Command Definitions for Flash Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.1 Command Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.2. Identifier Codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.3. Write Protection Alternatives . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6
6
7
7
6. Status Register Definition. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
7. Memory Map for Flash Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
8. Absolute Maximum Ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
9. Recommended DC Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
10. Pin Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
11. DC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
12. AC Electrical Characteristics for Flash Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
12.1 AC Test Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
12.2 Read Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
12.3 Write Cycle (F-WE Controlled) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
12.4 Write Cycle (F-CE Controlled) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
12.5 Block Erase, Full Chip Erase, Word Write and Lock-Bits Configuration Performance . . . . . . . . . . . . . . . . . .
12.6 Flash Memory AC Characteristics Timing Chart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
12.7 Reset Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
13
13
13
14
15
16
17
20
13. AC Electrical Characteristics for SRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
13.1 AC Test Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
13.2 Read Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
13.3 Write Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
13.4 SRAM AC Characteristics Timing Chart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
21
21
21
22
23
14. Data Retention Characteristics for SRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
15. Notes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
16. Flash Memory Data Protection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
17. Design Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
18. Related Document Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
19. Package and Packing Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
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LRS1360C
2
1. Description
The LRS1360C is a combination memory organized as 1,048,576 × 16 bit flash memory and 131,072 × 16 bit static RAM in one
package.
Features
- Power supply
• • • •
2.7V to 3.6V
- Operating temperature
• • • •
-25°C to +85°C
- Not designed or rated as radiation hardened
- 72 pin CSP (LCSP072-P-0811) plastic package
- Flash memory has P-type bulk silicon, and SRAM has P-type bulk silicon.
Flash Memory
- Access Time
• • • •
- Power Supply current (The current for F-VCC pin and F-VCCW pin)
Read
• • • •
Word write
• • • •
Block erase
• • • •
Reset Power-Down
• • • •
Standby
• • • •
90 ns
(Max.)
25 mA
57 mA
42 mA
20µA
(Max. tCYCLE = 200ns, CMOS Input)
(Max.)
(Max.)
(Max. F-RP = GND ± 0.2V,
IOUT(F-RY/BY) = 0mA)
(Max. F-CE = F-RP = F-VCC ± 0.2V)
30µA
- Optimized Array Blocking Architecture for each Bank.
Two 4k-word Boot Blocks
Six 4k-word Parameter Blocks
Thirty-one 32k-word Main Blocks
Top Boot Location
- Extended Cycling Capability
100,000 Block Erase Cycles
1,000 Block Erase Cycles and total 80 hours
(F-VCCW = 2.7 to 3.6V)
(F-VCCW = 11.7 to 12.3V)
- Enhanced Automated Suspend Options
Word Write Suspend to Read
Block Erase Suspend to Word Write
Block Erase Suspend to Read
SRAM
- Access Time
- Power Supply current
Operating current
Standby current
Data retention current
• • • •
85 ns
(Max.)
•
•
•
•
45 mA
8 mA
10µA
10µA
(Max. tRC,tWC = Min.)
(Max. tRC,tWC = 1µs, CMOS Input)
(Max.)
(Max. S-VCC = 3.0V)
•
•
•
•
•
•
•
•
•
•
•
•
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LRS1360C
3
2. Pin Configuration
INDEX
(TOP View)
1
2
3
4
5
6
7
8
9
10
11
12
A NC
NC
NC
A11
A15
A14
A13
A12
GND
NC
NC
NC
A16
A8
A10
A9
DQ15 S-WE DQ14 DQ7
NC
NC
B
C
FF-WE RY/BY
T1
T3
DQ13 DQ6
D
GND F-RP
T2
T4
DQ12 S-CE2 S-VCC F-VCC
E
F-WP F-VCCW F-A19 DQ11
T5
DQ10 DQ2
DQ3
F
S-LB S-UB S-OE
NC
DQ9
DQ8
DQ0
DQ1
G
F-A18 F-A17
A7
A6
A3
A2
A1
S-CE1
A4
A0
H NC
NC
NC
A5
DQ4
F-CE GND F-OE
DQ5
NC
Note) From T1 to T5 pins are needed to be open.
Two NC pins at the corner are connected.
Do not float any GND pins.
Rev. 1.00
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LRS1360C
Pin
A0 to A16
Description
4
Type
Address Inputs (Common)
Input
Address Inputs (Flash)
Input
F-CE
Bank Enable Inputs (Flash)
Input
S-CE1, S-CE2
Chip Enable Inputs (SRAM)
Input
F-WE
Write Enable Input (Flash)
Input
S-WE
Write Enable Input (SRAM)
Input
F-OE
Output Enable Input (Flash)
Input
S-OE
Output Enable Input (SRAM)
Input
S-LB
SRAM Byte Enable Input (DQ0 to DQ7)
Input
S-UB
SRAM Byte Enable Input (DQ8 to DQ15)
Input
F-RP
Reset Power Down Input (Flash)
Block erase and Write : VIH
Read : VIH
Reset Power Down : VIL
Input
F-WP
Write Protect Input (Flash)
Two Boot Blocks Locked : VIL
Input
F-A17 to F-A19
F-RY/BY
DQ0 to DQ15
Ready/Busy Output (Flash)
During an Erase or Write operation : VOL
Block Erase and Write Suspend : High-Z (High impedance)
Data Inputs and Outputs (Common)
Open Drain
Output
Input / Output
F-VCC
Power Supply (Flash)
Power
S-VCC
Power Supply (SRAM)
Power
Write, Erase Power Supply (Flash)
Block Erase and Write : F-VCCW = VCCWH1/2
All Blocks Locked : F-VCCW < VCCWLK
Power
GND (Common)
Power
F-VCCW
GND
NC
T1 to T5
Non Connection (Should be all open)
-
Test pins (Should be all open)
-
Rev. 1.00
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LRS1360C
3. Truth Table(1)
Flash
SRAM
Read
Output
Disable
Standby
Write
Read
Standby
Output
Disable
Write
Read
Reset Power Output
Disable
Down
5
F-CE F-RP F-OE F-WE S-CE1 S-CE2 S-OE S-WE S-LB S-UB DQ0 to DQ15
DOUT
3,5
L
H
L
H
5
High-Z
(6)
X
X
(6)
H
DIN
2,3,4,5
L
5
L
H
(7)
H
H
X
X
5
H
H
X
X
L
H
High-Z
X
X
H
H
5
X
L
(7)
5
L
H
(7)
H
H
X
X
5
X
L
X
X
L
H
High-Z
X
X
H
H
5
X
L
(7)
5
H
H
X
X
(6)
X
X
(6)
High-Z
5
X
L
Notes
Write
Standby
Reset Power Standby
Down
Notes:
1. L = VIL, H = VIH, X = H or L. Refer to DC Characteristics. High-Z = High impedance.
2. Command Writes involving block erase, full chip erase, word write, or lock-bit configuration are reliably
executed when F-VCCW = VCCWH1/2 and F-VCC = 2.7V to 3.6V.
Block erase, full chip erase, word write, or lock-bit configuration with F-VCCW < VCCWH1/2 (Min.) produce
spurious results and should not be attempted.
3. Never hold F-OE low and F-WE low at the same timing.
4. Refer Section 5. Command Definitions for Flash Memory valid DIN during a write operation.
5. F-WP set to VIL or VIH.
6. SRAM Standby Mode
7. S-UB, S-LB Control Mode
S-CE1 S-CE2 S-LB S-UB
S-LB S-UB DQ0 to DQ7 DQ8 to DQ15
H
X
X
X
L
L
DOUT/DIN
DOUT/DIN
X
L
X
X
L
H
DOUT/DIN
X
X
H
H
H
L
High-Z
High-Z
DOUT/DIN
4. Block Diagram
F-VCC
F-A17 to F-A19
A0 to A16
F-CE
F-OE
F-WE
F-WP
F-RP
F-VCCW
16M (x16) bit
Flash memory
F-RY/BY
GND
DQ0 to DQ15
S-CE1
S-CE2
S-OE
S-WE
S-LB
S-UB
2M (x16) bit
SRAM
S-VCC
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LRS1360C
6
5. Command Definitions for Flash Memory(1)
5.1 Command Definitions
Command
Read Array / Reset
Read Identifier Codes
Bus Cycles
Required
First Bus Cycle
Note
1
≥2
4
Second Bus Cycle
Oper(2)
Address(3)
Data
Oper(2)
Address(3)
Data(3)
Write
XA
FFH
Write
XA
90H
Read
IA
ID
Read
XA
SRD
Read Status Register
2
Write
XA
70H
Clear Status Register
1
Write
XA
50H
Block Erase
2
5
Write
XA
20H
Write
BA
D0H
Full Chip Erase
2
5
Write
XA
30H
Write
XA
D0H
Word Write
2
5
Write
XA
40H or
10H
Write
WA
WD
Block Erase and Word Write
Suspend
1
5,9
Write
XA
B0H
Block Erase and Word Write
Resume
1
5,9
Write
XA
D0H
Set Block Lock Bit
2
7
Write
XA
60H
Write
BA
01H
Clear Block Lock Bits
2
6,7
Write
XA
60H
Write
XA
D0H
Set Permanent Lock Bit
2
8
Write
XA
60H
Write
XA
F1H
Notes:
1. Commands other than those shown above are reserved by SHARP for future device implementations and should not be used.
2. Bus operations are defined in 3. Truth Table.
3. XA = Any valid address within the device.
IA = Identifier code address.
BA = Address within the block being erased.
WA = Address of memory location to be written.
SRD = Data read from status register (See 6. Status Register Definition).
WD = Data to be written at location WA. Data is latched on the rising edge of F-WE or F-CE (whichever goes high first).
ID = Data read from identifier codes (See 5.2 Identifier Codes).
4. See Identifier Codes at next page.
5. See Write Protection Alternatives in section 5.3.
6. The clear block lock-bits operation simultaneously clears all block lock-bits.
7. If the permanent lock-bit is set, Set Block Lock-Bit and Clear Block Lock-Bits commands can not be done.
8. Once the permanent lock-bit is set, it cannot be cleared.
9. If the time between writing the Block Erase Resume command and writing the Block Erase Suspend command is shorter than
15ms and both commands are written repeatedly, a longer time is required than standard block erase until the completion of
the operation.
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LRS1360C
5.2 Identifier Codes(3)
Codes
7
Address [A19 - A0]
Data [DQ15 - DQ0]
Manufacture Code
00000H
00B0H
Device Code
00001H
00E8H
Block Lock Configuration(2)
BA(1) + 2
DQ0 = 0 : Unlocked
DQ0 = 1 : Locked
Permanent Lock Configuration(2)
00003H
DQ0 = 0 : Unlocked
DQ0 = 1 : Locked
Notes:
1. BA selects the specific block lock configuration code to be read.
2. DQ15 - DQ1 are reserved for future use.
3. Read Identifier Codes command is defined in 5.1 Command Definitions.
5.3 Write Protection Alternatives
Operation
F-VCCW
≤VCCWLK
Block Erase or
(1)
Word Write >V
CCWLK
F-RP
F-WP
Permanent
Lock-Bit
Block
Lock-Bit
X
X
X
X
All Blocks Locked.
VIL
X
X
X
All Blocks Locked.
VIL
VIH
VIH
VIL
0
X
1
VIH
≤VCCWLK
Full Chip Erase
>VCCWLK(1)
Set Block
Lock-Bit
>VCCWLK
Clear Block
Lock-Bits
>VCCWLK
Block Erase and Word Write Disabled.
Block Erase and Word Write Disabled.
X
X
All Blocks Locked.
VIL
X
X
X
All Blocks Locked.
VIL
VIH
X
X
All Unlocked Blocks are Erased.
2 Boot Blocks and Locked Blocks are Not Erased.
All Unlocked Blocks are Erased.
Locked Blocks are Not Erased.
X
X
X
X
Set Block Lock-Bit Disabled.
VIL
X
X
X
Set Block Lock-Bit Disabled.
X
0
X
Set Block Lock-Bit Enabled.
X
1
X
Set Block Lock-Bit Disabled.
X
X
X
X
Clear Block Lock-Bits Disabled.
VIL
X
X
X
Clear Block Lock-Bits Disabled.
X
0
X
Clear Block Lock-Bits Enabled.
X
1
X
Clear Block Lock-Bits Disabled.
X
X
X
X
Set Permanent Lock-Bit Disabled.
VIL
X
X
X
Set Permanent Lock-Bit Disabled.
VIH
X
X
X
Set Permanent Lock- Bit Enabled.
VIH
(1)
≤VCCWLK
Set Permanent
Lock-Bit
>VCCWLK(1)
Block Erase and Word Write Enabled.
X
(1)
≤VCCWLK
2 Boot Blocks Locked.
X
VIH
≤VCCWLK
Effect
VIH
Note:
1. F-VCCW is guaranteed only with the nominal voltages.
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LRS1360C
8
6. Status Register Definition
WSMS
BESS
ECBLBS
WWSLBS
VCCWS
WWSS
DPS
R
7
6
5
4
3
2
1
0
SR.7 = WRITE STATE MACHINE STATUS (WSMS)
1 = Ready
0 = Busy
SR.6 = BLOCK ERASE SUSPEND STATUS (BESS)
1 = Block Erase Suspended
0 = Block Erase in Progress/Completed
Notes:
Check SR.7 or F-RY/BY to determine Block Erase, Full Chip
Erase, Word Write or Lock-Bit configuration completion.
SR.6 - SR.0 are invalid while SR.7 = “0”.
If both SR.5 and SR.4 are “1”s after a Block Erase, Full Chip
SR.5 = ERASE AND CLEAR BLOCK LOCK-BITS Erase, Word Write, or Lock-Bit configuration attempt, an
STATUS (ECBLBS)
improper command sequence was entered.
1 = Error in Block Erase, Full Chip Erase or Clear Block
Lock-Bits
0 = Successful Block Erase, Full Chip Erase or Clear
Block Lock-Bits
SR.3 does not provide a continuous indication of F-VCCW
level. The WSM (Write State Machine) interrogates and
SR.4 = WORD WRITE AND SET LOCK-BIT
indicates the F-VCCW level only after Block Erase, Full Chip
STATUS (WWSLBS)
Erase,
Word Write, or Lock-Bit Configuration command
1 = Error in Word Write or Set Block/Permanent
sequences.
SR.3 is not guaranteed to reports
Lock-Bit
accurate
feedback
only when F-VCCW ≠ VCCWH1/2.
0 = Successful Word Write or Set Block/Permanent
Lock-Bit
SR.3 = F-VCCW STATUS (VCCWS)
1 = F-VCCW Low Detect, Operation Abort
0 = F-VCCW OK
SR.1 does not provide a continuous indication of permanent
and block lock-bit and F-WP values. The WSM interrogates
the permanent lock-bit, block lock-bit and F-WP only after
Block Erase, Full Chip Erase, Word Write, or Lock-Bit ConSR.2 = WORD WRITE SUSPEND STATUS (WWSS)
figuration command sequences. It informs the system, depend1 = Word Write Suspended
ing on the attempted operation, if the block lock-bit is set,
0 = Word Write in Progress/Completed
permanent lock-bit is set and/or F-WP is VIL. Reading the
block lock and permanent lock configuration codes after writSR.1 = DEVICE PROTECT STATUS (DPS)
ing the Read Identifier Codes command
1 = Block Lock-Bit, Permanent Lock-Bit and/or F-WP
indicates permanent and block lock-bit status.
Lock Detected, Operation Abort
0 = Unlocked
SR.0 is reserved for future use and should be masked out when
SR.0 = RESERVED FOR FUTURE ENHANCEMENTS (R) polling the status register.
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LRS1360C
9
7. Memory Map for Flash Memory
Top Boot
[A19 ~ A0]
FFFFF
FF000
FEFFF
FE000
FDFFF
FD000
FCFFF
FC000
FBFFF
FB000
FAFFF
FA000
F9FFF
F9000
F8FFF
F8000
F7FFF
F0000
EFFFF
E8000
E7FFF
E0000
DFFFF
D8000
D7FFF
D0000
CFFFF
C8000
C7FFF
C0000
BFFFF
B8000
B7FFF
B0000
AFFFF
A8000
A7FFF
A0000
9FFFF
98000
97FFF
90000
8FFFF
88000
87FFF
80000
7FFFF
78000
77FFF
70000
6FFFF
68000
67FFF
60000
5FFFF
58000
57FFF
50000
4FFFF
48000
47FFF
40000
3FFFF
38000
37FFF
30000
2FFFF
28000
27FFF
20000
1FFFF
18000
17FFF
10000
0FFFF
08000
07FFF
00000
4K-word Boot Block 0
4K-word Boot Block 1
4K-word Parameter Block 0
4K-word Parameter Block 1
4K-word Parameter Block 2
4K-word Parameter Block 3
4K-word Parameter Block 4
4K-word Parameter Block 5
32K-word Main Block 0
32K-word Main Block 1
32K-word Main Block 2
32K-word Main Block 3
32K-word Main Block 4
32K-word Main Block 5
32K-word Main Block 6
32K-word Main Block 7
32K-word Main Block 8
32K-word Main Block 9
32K-word Main Block 10
32K-word Main Block 11
32K-word Main Block 12
32K-word Main Block 13
32K-word Main Block 14
32K-word Main Block 15
32K-word Main Block 16
32K-word Main Block 17
32K-word Main Block 18
32K-word Main Block 19
32K-word Main Block 20
32K-word Main Block 21
32K-word Main Block 22
32K-word Main Block 23
32K-word Main Block 24
32K-word Main Block 25
32K-word Main Block 26
32K-word Main Block 27
32K-word Main Block 28
32K-word Main Block 29
32K-word Main Block 30
Rev. 1.00
sharp
LRS1360C
10
8. Absolute Maximum Ratings
Symbol
Parameter
Notes
Ratings
Unit
1,2
-0.2 to +4.6
V
1,2,3,5
-0.2 to +3.9
V
VCC
Supply voltage
VIN
Input voltage
TA
Operating temperature
-25 to +85
°C
Storage temperature
-65 to +125
°C
-0.3 to +13.0
V
TSTG
F-VCCW
F-VCCW voltage
1,3,4
Notes:
1. The maximum applicable voltage on any pins with respect to GND.
2. Except F-VCCW.
3. -1.0V undershoot and VCC +1.0V overshoot are allowed when the pulse width is less than 20 nsec.
4. Applying 12V ± 0.3V to F-VCCW during erase/write can only be done for a maximum of 1000 cycles on each block. F-VCCW
may be connected to 12V ± 0.3V for total of 80 hours maximum. +13.0V overshoot is allowed when the pulse width is less
than 20nsec.
5. VIN should not be over VCC + 0.3V.
9. Recommended DC Operating Conditions
(TA = -25°C to +85°C)
Symbol
VCC
VIH
Parameter
Notes
Min.
Typ.
Max.
Unit
Supply Voltage
2
2.7
3.0
3.6
V
Input Voltage
1
2.0
VCC+0.2
V
-0.2
0.4
V
VIL
Input Voltage
Notes:
1. VCC is the lower one of F-VCC and S-VCC.
2. VCC includes both F-VCC and S-VCC.
10. Pin Capacitance
(TA = 25°C, f = 1MHz)
Symbol
CIN
Parameter
Input capacitance
CI/O
I/O capacitance
Note:
1. Sampled but not 100% tested.
Notes
Min.
Typ.
Max.
Unit
Condition
1
10
pF
VIN = 0V
1
20
pF
VI/O = 0V
Rev. 1.00
sharp
LRS1360C
11
11. DC Electrical Characteristics(6)
DC Electrical Characteristics
(TA = -25°C to +85°, VCC = 2.7V to 3.6V)
Symbol
Parameter
Notes Min.
Typ.(1)
Max.
Unit
Conditions
ILI
Input Leakage Current
±1.5
µA VIN = VCC or GND
ILO
Output Leakage Current
±1.5
µA VOUT = VCC or GND
ICCS
F-VCC Standby Current
ICCAS F-VCC Auto Power-Save Current
ICCD
ICCR
F-VCC Reset Power-Down Current
F-VCC Read Current
2
15
CMOS Input
µA F-CE = F-RP = F-V ± 0.2V
CC
0.2
2
TTL Input
mA F-CE = F-RP = V
IH
3,4
2
15
µA
4
2
15
F-RP = GND ± 0.2V
µA I
OUT(F-RY/BY) = 0mA
15
25
CMOS Input
mA F-CE = GND, f = 5MHz, I
OUT = 0mA
30
TTL Input
mA F-CE = V , f = 5MHz, I
IL
OUT = 0mA
5
17
mA F-VCCW = VCCWH1
5
12
mA F-VCCW = VCCWH2
4
17
mA F-VCCW = VCCWH1
4
12
mA F-VCCW = VCCWH2
1
6
mA F-CE = VIH
±2
±15
µA F-VCCW ≤ F-VCC
10
200
µA F-VCCW > F-VCC
4
4
ICCW
F-VCC Word Write or Set Lock-Bit
Current
8
ICCE
F-VCC Block Erase, Full Chip Erase or
Clear Block Lock-Bits Current
8
ICCWS F-VCC Word Write or Block Erase
ICCES Suspend Current
CMOS Input
F-CE = GND ± 0.2V
ICCWS
F-VCCW Standby or Read Current
ICCWR
4
ICCWAS F-VCCW Auto Power-Save Current
3,4
0.1
5
µA
4
0.1
5
µA F-RP = GND ± 0.2V
12
40
mA F-VCCW = VCCWH1
30
mA F-VCCW = VCCWH2
25
mA F-VCCW = VCCWH1
20
mA F-VCCW = VCCWH2
10
200
µA F-VCCW = VCCWH1/2
0.5
10
µA
ICCWD F-VCCW Reset Power-Down Current
ICCWW
F-VCCW Word Write or Set Lock-Bit
Current
8
ICCWE
F-VCCW Block Erase, Full Chip Erase
or Clear Block Lock-Bits Current
8
ICCWWS F-VCCW Word Write or Block Erase
ICCWES Suspend Current
8
CMOS Input
F-CE = GND ± 0.2V
S-CE1, S-CE2 ≥ S-VCC - 0.2V or
S-CE2 ≤ 0.2V
ISB
S-VCC Standby Current
ISB1
S-VCC Standby Current
3
mA S-CE1 = VIH or S-CE2 = VIL
ICC1
S-VCC Operation Current
45
S-CE1 = VIL,
mA S-CE2 = VIH
VIN = VIL or VIH
tCYCLE =Min.
II/O = 0mA
8
S-CE1 = 0.2V,
S-CE2 = SVCC -0.2V,
mA
VIN = S-VCC -0.2V
or 0.2V
tCYCLE =1µA
II/O = 0mA
ICC2
S-VCC Operation Current
Rev. 1.00
sharp
LRS1360C
12
DC Electrical Characteristics (Continue)
(TA = -25°C to +85°C, VCC = 2.7V to 3.6V)
Symbol
Parameter
Notes
Min.
Typ.(1)
Max.
Unit
Conditions
VIL
Input Low Voltage
8
-0.2
0.4
V
VIH
Input High Voltage
8
2.0
VCC
+0.2
V
VOL
Output Low Voltage
2,8
0.4
V
IOL = 0.5mA
VOH
Output High Voltage
2,8
V
IOH = -0.5mA
F-VCCW Lockout during Normal
Operations
5,8
VCCWLK
F-VCCW during Block Erase, Full Chip
VCCWH1 Erase, Word Write, or Lock-Bit
configuration Operations
F-VCCW during Block Erase, Full Chip
VCCWH2 Erase, Word Write, or Lock-Bit
configuration Operations
VLKO
F-VCC Lockout Voltage
7
2.0
1.5
V
2.7
3.6
V
11.7
12.3
V
2.0
V
Notes:
1. All currents are in RMS unless otherwise noted. Reference values at VCC = 3.0V and TA = +25°C.
2. Includes F-RY/BY.
3. The Automatic Power Savings (APS) feature is placed automatically power save mode that addresses not switching more
than 300ns while read mode.
4. CMOS inputs are either VCC ± 0.2V or GND ± 0.2V. TTL inputs are either VIL or VIH.
5. Block erases, full chip erase, word writes and lock-bits configurations are inhibited when F-VCCW ≤ VCCWLK and not
guaranteed in the range between VCCWLK (Max.) and VCCWH (Min.), and above VCCWH (Max.).
6. VCC includes both F-VCC and S-VCC.
7. Applying VCCWH2 to F-VCCW during erase/write can only be done for a maximum of 1000 cycles on each block. F-VCCW
may be connected to VCCWH2 for a total of 80 hours maximum.
8. Sampled, not 100% tested.
Rev. 1.00
sharp
LRS1360C
13
12. AC Electrical Characteristics for Flash Memory
12.1 AC Test Conditions
Input pulse level
0V to 2.7V
Input rise and fall time
10ns
Input and Output timing Ref. level
1.35V
1TTL + CL (50pF)
Output load
12.2 Read Cycle
(TA = -25°C to +85°C, F-VCC = 2.7V to 3.6V)
Symbol
Parameter
tAVAV
Read Cycle Time
tAVQV
Address to Output Delay
tELQV
F-CE to Output Delay
tPHQV
F-RP High to Output Delay
tGLQV
F-OE to Output Delay
tELQX
F-CE to Output in Low-Z
tEHQZ
F-CE High to Output in High-Z
tGLQX
F-OE to Output in Low-Z
tGHQZ
F-OE High to Output in High-Z
tOH
Notes
Min.
Max.
90
1
1
Output Hold form Address, F-CE or F-OE Change, Whichever Occurs First
ns
90
ns
90
ns
600
ns
40
ns
0
ns
40
0
ns
ns
15
0
Unit
ns
ns
Note:
1. F-OE may be delayed up to tELQV - tGLQV after the falling edge of F-CE without impact on tELQV.
Rev. 1.00
sharp
LRS1360C
14
12.3 Write Cycle (F-WE Controlled)(1,5)
(TA = -25°C to +85°C, F-VCC = 2.7V to 3.6V)
Symbol
Parameter
tAVAV
Write Cycle Time
tPHWL
F-RP High Recovery to F-WE Going Low
tELWL
Notes
Min.
Max.
Unit
90
ns
1
µs
F-CE Setup to F-WE Going Low
10
ns
tWLWH
F-WE Pulse Width
50
ns
tSHWH
F-WP VIH Setup to F-WE Going High
2
100
ns
tVPWH
F-VCCW Setup to F-WE Going High
2
100
ns
tAVWH
Address Setup to F-WE Going High
3
50
ns
tDVWH
Data Setup to F-WE Going High
3
50
ns
tWHDX
Data Hold from F-WE High
0
ns
tWHAX
Address Hold from F-WE High
0
ns
tWHEH
F-CE Hold from F-WE High
10
ns
tWHWL
F-WE Pulse Width High
30
ns
tWHRL
F-WE going High to F-RY/BY Going Low
tWHGL
Write Recovery before Read
tQVVL
F-VCCW Hold from Valid SRD, F-RY/BY High-Z
tQVSL
F-WP VIH Hold from Valid SRD, F-RY/BY High-Z
2
100
ns
0
ns
2,4
0
ns
2,4
0
ns
Notes:
1. Read timing characteristics during block erase, full chip erase, word write and lock-bit configurations are the same as during
read-only operations. Refer to AC Characteristics for read cycle.
2. Sampled, not 100% tested.
3. Refer to Section 5. Command Definitions for Flash Memory for valid AIN and DIN for block erase, full chip erase, word
write or lock-bit configuration.
4. F-VCC should be held at VCCWH1/2 until determination of block erase, full chip erase, word write or lock-bit configuration
success (SR.1/3/4/5 = 0).
5. It is written when F-CE and F-WE are active. The address and data needed to execute a command are latched on the rising
edge of F-WE or F-CE (Whichever goes high first).
Rev. 1.00
sharp
LRS1360C
15
12.4 Write Cycle (F-CE Controlled)(1,5)
(TA = -25°C to +85°C, F-VCC = 2.7V to 3.6V)
Symbol
Parameter
tAVAV
Write Cycle Time
tPHEL
F-RP High Recovery to F-CE Going Low
tWLEL
Notes
Min.
Max.
Unit
90
ns
1
µs
F-WE Setup to F-CE Going Low
0
ns
tELEH
F-CE Pulse Width
65
ns
tSHEH
F-WP VIH Setup to F-CE Going High
2
100
ns
tVPEH
F-VCCW Setup to F-CE Going High
2
100
ns
tAVEH
Address Setup to F-CE Going High
3
50
ns
tDVEH
Data Setup to F-CE Going High
3
50
ns
tEHDX
Data Hold from F-CE High
0
ns
tEHAX
Address Hold from F-CE High
0
ns
tEHWH
F-WE Hold from F-CE High
0
ns
tEHEL
F-CE Pulse Width High
25
ns
tEHRL
F-CE going High to F-RY/BY Going Low or SR.7 Going “0”
tEHGL
Write Recovery before Read
tQVVL
F-VCC Hold from Valid SRD, F-RY/BY High-Z
tQVSL
F-WP VIH Hold from Valid SRD, F-RY/BY High-Z
2
100
ns
0
ns
2,4
0
ns
2,4
0
ns
Notes:
1. In systems where F-CE defines the write pulse width (within a longer F-WE timing waveform), all setup, hold and inactive
F-WE times should be measured relative to the F-CE waveform.
2. Sampled, not 100% tested.
3. Refer to Section 5. Command Definitions for Flash Memory for valid AIN and DIN for block erase, full chip erase, word
write or lock-bit configuration.
4. F-VCCW should be held at VCCWH1/2 until determination of block erase, full chip erase, word write or lock-bit configuration
success (SR.1/3/4/5=0).
5. It is written when F-CE and F-WE are active. The address and data needed to execute a command are latched on the rising
edge of F-WE or F-CE (Whichever goes high first).
Rev. 1.00
sharp
LRS1360C
16
12.5 Block Erase, Full Chip Erase, Word Write and Block Lock-Bits Configuration Performance(3)
(TA = -25°C to +85°C, F-VCC = 2.7V to 3.6V)
Symbol
Parameter
Notes
F-VCCW = 2.7V to 3.6V F-VCCW = 11.7V to 12.3V
Typ.(1)
Max.
Typ.(1)
Max.
Unit
32K-Word Block
2
33
200
20
µs
4K-Word Block
2
36
200
27
µs
32K-Word Block
2
1.1
4
0.66
s
4K-Word Block
2
0.15
0.5
0.12
s
32K-Word Block
2
1.2
6
0.9
s
4K-Word Block
2
0.6
5
0.5
s
2
42
210
32
s
tWHQV3
Set Lock-Bit Time
tEHQV3
2
56
200
42
µs
tWHQV4
Clear Block Lock-Bits Time
tEHQV4
2
1
5
0.69
s
tWHRZ1
Word Write Suspend Latency Time to Read
tEHRZ1
4
6
15
6
15
µs
tWHRZ2
Erase Suspend Latency Time to Read
tEHRZ2
4
16
30
16
30
µs
tWHQV1
Word Write Time
tEHQV1
Block Write Time
tWHQV2
Block Erase Time
tEHQV2
Full Chip Erase Time
Notes:
1. Reference values at TA = +25°C and F-VCC = 3.0V, F-VCCW = 3.0V or 12.0V. Assumes corresponding lock-bits are not set.
Subject to change based on device characterization.
2. Excludes system-level overhead.
3. Sampled, not 100% tested.
4. A Latency time is required from issuing suspend command (F-WE or F-CE going high ) until F-RY/BY going High-Z or
SR.7 going “1”.
Rev. 1.00
sharp
LRS1360C
17
12.6 Flash Memory AC Characteristics Timing Chart
Read Cycle Timing Chart
Address(A)
F-CE(E)
F-OE(G)
F-WE(W)
Data(D/Q)
VIH
Standby
Device
Address Selection
Data Valid
Address Stable
VIL
tAVAV
VIH
tEHQZ
VIL
VIH
tGHQZ
VIL
VIH
VIL
VOH
VOL
High - Z
tELQV
tGLQX
tELQX
tAVQV
tGLQV
tOH
Valid Output
High - Z
F-VCC
tPHQV
F-RP(P)
VIH
VIL
Rev. 1.00
sharp
LRS1360C
18
Write Cycle Timing Chart (F-WE Controlled)
Address(A)
F-CE(E)
F-OE(G)
F-WE(W)
Data(D/Q)
VIH
VIL
2
3
4
AIN
tAVAV
AIN
tAVWH
VIL
VIH
tELWL
tWHEH
VIL
VIL
VOH
High - Z
VOL
VIH
VIL
VCCWH1,2
6
tWHGL
tWHWL
VIH
5
tWHAX
VIH
High-Z
("1")
F-RY/BY(R)
(SR.7) VOL
("0")
VIH
F-WP(S)
VIL
F-RP(P)
1
tWHQV1,2,3,4
tWLWH
tDVWH
tWHDX
Data
Valid
SRD
DIN
DIN
DIN
tWHRL
tSHWH
tQVSL
tPHWL
tVPWH
tQVVL
F-VCCW(V) VCCWLK
VIL
Notes:
1. F-VCC power-up and standby.
2. Write each setup command.
3. Write each comfirm command or valid address and data.
4. Automated erase or program delay
5. Read status register data.
6. Write Read Array command.
Rev. 1.00
sharp
LRS1360C
19
Write Cycle Timing Chart (F-CE Controlled)
Address(A)
F-CE(E)
F-OE(G)
F-WE(W)
Data(D/Q)
VIH
VIL
2
3
AIN
tAVAV
AIN
4
tAVEH
VIH
tEHGL
VIL
tEHQV1,2,3,4
VIH
VOH
tWLEL
High - Z
VOL
VIH
VIL
VCCWH1,2
6
tEHAX
tELEH
tDVEH
VIH
VIL
5
tEHEL
VIL
High-Z
F-RY/BY(R) ("1")
(SR.7) VOL
("0")
VIH
F-WP(S)
VIL
F-RP(P)
1
tEHWH
tEHDX
Data
Valid
SRD
DIN
DIN
DIN
tEHRL
tSHEH
tQVSL
tPHEL
tVPEH
tQVVL
F-VCCW(V) VCCWLK
VIL
Notes:
1. F-VCC power-up and standby.
2. Write each setup command.
3. Write each comfirm command or valid address and data.
4. Automated erase or program delay
5. Read status register data.
6. Write Read Array command.
Rev. 1.00
sharp
LRS1360C
20
12.7 Reset Operations(1,2)
(TA = -25°C to +85°C, F-VCC = 2.7V to 3.6V)
Symbol
Parameter
Notes
tPLPH
F-RP Pulse Low Time
(If F-RP is tied to VCC, this specification is not applicable.)
tPLRZ
F-RP Low to Reset during Block Erase, Full Chip Erase, Word
Write or lock-bit configuration
tVPH
F-VCC = 2.7V to F-RP High
Min.
Max.
100
ns
30
3
100
Unit
µs
ns
Notes:
1. If F-RP is asserted while a block erase, full chip erase, word write or lock-bit configuration operation is not executing, the
reset will complete within 100ns.
2. A reset time, tPHQV, is required from the later of F-RY/BY(SR.7) going High-Z (“1”) or F-RP going high until outputs are
valid. Refer to AC Characteristics-Read Cycle for tPHQV.
3. When the device power-up, holding F-RP low minimum 100ns is required after F-VCC has been in predefined range and also
has been in stable there.
AC Waveform for Reset Operation
High-Z
F-RY/BY(R) ("1")
(SR.7)
VOL
("0")
F-RP(P)
VIH
VIL
High-Z
F-RY/BY(R) ("1")
(SR.7)
VOL
("0")
F-RP(P)
F-VCC
F-RP(P)
tPLPH
(A) Reset During Read Array Mode
tPLRZ
VIH
VIL
2.7V
VIL
tPLPH
(B) Reset During Block Erase, Full Chip Erase,
Word Write or Lock-Bit configuration
tVPH
VIH
VIL
(C) F-RP Rising Timing
Rev. 1.00
sharp
LRS1360C
21
13. AC Electrical Characteristics for SRAM
13.1 AC Test Conditions
Input pulse level
0.4V to 2.2V
Input rise and fall time
5ns
Input and Output timing Ref. level
1.5V
1TTL + CL (30pF)(1)
Output load
Note:
1. Including scope and socket capacitance.
13.2 Read Cycle
(TA = -25°C to +85°C, S-VCC = 2.7V to 3.6V)
Symbol
Parameter
Notes
Min.
Max.
Unit
tRC
Read Cycle Time
tAA
Address access time
85
ns
tACE1
Chip enable access time (S-CE1)
85
ns
tACE2
Chip enable access time (S-CE2)
85
ns
tBE
Byte enable access time
85
ns
tOE
Output enable to output valid
45
ns
tOH
Output hold from address change
tLZ1
S-CE1 Low to output active
tLZ2
85
ns
15
ns
1
10
ns
S-CE2 Low to output active
1
10
ns
tOLZ
S-OE Low to output active
1
5
ns
tBLZ
S-UB or S-LB Low to output in High-Z
1
10
ns
tHZ1
S-CE1 High to output in High-Z
1
0
25
ns
tHZ2
S-CE2 High to output in High-Z
1
0
25
ns
tOHZ
S-OE High to output in High-Z
1
0
25
ns
tBHZ
S-UB or S-LB High to output active
1
0
25
ns
Note:
1. Active output to High-Z and High-Z to output active tests specified for a ±200mV transition from steady state levels into the
test load.
Rev. 1.00
sharp
LRS1360C
22
13.3 Write Cycle
(TA = -25°C to +85°C, S-VCC = 2.7V to 3.6V)
Symbol
Parameter
Notes
Min.
Max.
Unit
tWC
Write cycle time
85
ns
tCW
Chip enable to end of write
70
ns
tAW
Address valid to end of write
70
ns
tBW
Byte select time
70
ns
tAS
Address setup time
0
ns
tWP
Write pulse width
60
ns
tWR
Write recovery time
0
ns
tDW
Input data setup time
35
ns
tDH
Input data hold time
0
ns
tOW
S-WE High to output active
1
5
ns
tWZ
S-WE Low to output in High-Z
1
0
25
ns
Note:
1. Active output to High-Z and High-Z to output active tests specified for a ±200mV transition from steady state levels into the
test load.
Rev. 1.00
sharp
LRS1360C
23
13.4 SRAM AC Characteristics Timing Chart
Read cycle timing chart
Address
S-CE1
S-CE2
S-UB
S-LB
S-OE
S-WE
DQOUT
VIH
Standby
Device
Address Selection
Data Valid
Address Stable
VIL
tRC
VIH
VIL
tLZ1,2
VIH
tHZ1,2
tACE1,2
VIL
tBLZ
tBE
VIH
VIL
tBHZ
tOLZ
tOE
VIH
tOHZ
VIL
VIH
VIL
VOH
VOL
tAA
High - Z
tOH
Data Valid
High - Z
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Write cycle timing chart (S-WE Controlled)
Address
S-CE1
S-CE2
S-UB
S-LB
S-OE
S-WE
DQOUT(7,8)
VIH
Standby
Device
Address Selection
Data Valid
Address Stable
VIL
tWC
VIH
VIL
tCW (2)
tWR(5)
VIH
VIL
tBW(3)
VIH
VIL
VIH
VIL
VIH
VIL
VOH
VOL
VIH
tAW
tAS (4)
Data Undefined
tWP (1)
tWZ
tOW
tDW
tDH
High - Z
High - Z
DQIN (6)
Data Valid
VIL
Notes:
1. A write occurs during the overlap of a low S-CE1, a high S-CE2 and a low S-WE.
A write begins at the latest transition among S-CE1 going low, S-CE2 going high and S-WE going low.
A write ends at the earliest transition among S-CE1 going high, S-CE2 going low and S-WE going high.
tWP is measured from the beginning of write to the end of write.
2. tCW is measured from the later of S-CE1 going low or S-CE2 going high to the end of write.
3. tBW is measured from the time of going low S-UB or low S-LB to the end of write.
4. tAS is measured from the address valid to beginning of write.
5. tWR is measured from the end of write to the address change. tWR applies in case a write ends at S-CE1
going high, S-CE2 going low or S-WE going high.
6. During this period DQ pins are in the output state, therefore the input signals of opposite phase to the
outputs must not be applied.
7. If S-CE1 goes low or S-CE2 goes high simultaneously with S-WE going low or after S-WE going low,
the outputs remain in high impedance state.
8. If S-CE1 goes high or S-CE2 goes low simultaneously with S-WE going high or before S-WE going high,
the outputs remain in high impedance state.
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Write cycle timing chart (S-CE Controlled)
Address
S-CE1
S-CE2
S-UB
S-LB
S-OE
S-WE
DQOUT
VIH
Standby
Device
Address Selection
Data Valid
Address Stable
VIL
tWC
VIH
VIL
tAS (4)
tCW(2)
tWR(5)
VIH
VIL
tBW(3)
VIH
VIL
VIH
VIL
VIH
tAW
tWP (1)
VIL
VOH
VOL
VIH
High - Z
tDW
tDH
DQIN
Data Valid
V
IL
Notes:
1. A write occurs during the overlap of a low S-CE1, a high S-CE2 and a low S-WE.
A write begins at the latest transition among S-CE1 going low, S-CE2 going high and S-WE going low.
A write ends at the earliest transition among S-CE1 going high, S-CE2 going low and S-WE going high.
tWP is measured from the beginning of write to the end of write.
2. tCW is measured from the later of S-CE1 going low or S-CE2 going high to the end of write.
3. tBW is measured from the time of going low S-UB or low S-LB to the end of write.
4. tAS is measured from the address valid to beginning of write.
5. tWR is measured from the end of write to the address change. tWR applies in case a write ends at S-CE1
going high, S-CE2 going low or S-WE going high.
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Write cycle timing chart (S-UB,S-LB Controlled)
Address
S-CE1
S-CE2
S-UB
S-LB
S-OE
S-WE
DQOUT
VIH
Standby
Device
Address Selection
Data Valid
Address Stable
VIL
tWC
VIH
VIL
tCW(2)
tWR(5,6)
VIH
VIL
VIH
tAS(4,6)
tBW(3)
VIL
VIH
VIL
VIH
tAW
tWP (1)
VIL
VOH
VOL
VIH
High - Z
tDW
tDH
DQIN
Data Valid
V
IL
Notes:
1. A write occurs during the overlap of a low S-CE1, a high S-CE2 and a low S-WE.
A write begins at the latest transition among S-CE1 going low, S-CE2 going high and S-WE going low.
A write ends at the earliest transition among S-CE1 going high, S-CE2 going low and S-WE going high.
tWP is measured from the beginning of write to the end of write.
2. tCW is measured from the later of S-CE1 going low or S-CE2 going high to the end of write.
3. tBW is measured from the time of going low S-UB or low S-LB to the end of write.
4. tAS is measured from the address valid to beginning of write.
5. tWR is measured from the end of write to the address change. tWR applies in case a write ends at S-CE1
going high, S-CE2 going low or S-WE going high.
6. S-UB and S-LB need to make the time of start of a cycle, and an end "high" level for reservation of tAS and tWR.
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27
14. Data Retention Characteristics for SRAM
(TA = -25°C to +85°C)
Typ.(1)
Symbol
Parameter
Note
Min.
VCCDR
Data Retention Supply voltage
2
1.5
ICCDR
Data Retention Supply current
2
tCDR
Chip enable setup time
0
ns
Chip enable hold time
tRC
ns
tR
Max.
Unit
3.6
V
S-CE2 ≤ 0.2V or
S-CE1 ≥ S-VCC - 0.2V
10
µA
S-VCC = 3.0V
S-CE2 ≤ 0.2V or
S-CE1 ≥ S-VCC - 0.2V
0.5
Conditions
Notes
1. Reference value at TA = 25°C, S-VCC = 3.0V.
2. S-CE1 ≥ S-VCC - 0.2V, S-CE2 ≥ S-VCC - 0.2V (S-CE1 controlled) or S-CE2 ≤ 0.2V (S-CE2 controlled).
Data Retention timing chart (S-CE1 Controlled)(1)
S-VCC
Data Retention mode
2.7V
tCDR
tR
2.0V
VCCDR
S-CE1
S-CE1 ≥ S-VCC-0.2V
0V
Note:
1. To control the data retention mode at S-CE1, fix the input level of
S-CE2 between VCCDR and VCCDR-0.2V or 0V or 0.2V and during the data retention mode.
Data Retention timing chart (S-CE2 Controlled)
S-VCC
S-CE2
Data Retention mode
2.7V
tCDR
tR
VCCDR
0.4V
0V
S-CE2 ≤ 0.2V
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28
15. Notes
This product is a stacked CSP package that a 16M (x16) bit Flash Memory and a 2M (x16) bit SRAM are assembled into.
- Supply Power
Maximum difference (between F-VCC and S-VCC) of the voltage is less than 0.3V.
- Power Supply and Chip Enable of Flash Memory and SRAM
S-CE1 should not be “low” and S-CE2 should not be “high” when F-CE is “low” simultaneously.
If the two memories are active together, possibly they may not operate normally by interference noises or data collision
on DQ bus.
Both F-VCC and S-VCC are needed to be applied by the recommended supply voltage at the same time expect SRAM
data retention mode.
- Power Up Sequence
When turning on Flash memory power supply, keep F-RP “low”. After F-VCC reaches over 2.7V, keep F-RP “low” for
more than 100nsec.
- Device Decoupling
The power supply is needed to be designed carefully because one of the SRAM and the Flash Memory is in standby
mode when the other is active. A careful decoupling of power supplies is necessary between SRAM and Flash
Memory. Note peak current caused by transition of control signals (F-CE, S-CE1, S-CE2).
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16. Flash Memory Data Protection
Noises having a level exceeding the limit specified in the specification may be generated under specific operating
conditions on some systems. Such noises, when induced onto F-WE signal or power supply, may be interpreted as
false commands, causing undesired memory updating. To protect the data stored in the flash memory against
unwanted writing, systems operating with the flash memory should have the following write protect designs, as
appropriate.
■ The below describes data protection method.
1. Protecting data in specific block
• By setting a F-WP to low, only the boot block can be protected against overwriting. Parameter and main
blocks cannot be locked. System program, etc., can be locked by storing them in the boot block. For further
information on setting/resetting of lock bit, and controlling of F-WP and F-RP refer to the specification. (See
Chapter 5. Command Definitions for Flash Memory)
2. Data Protection through F-VCCW
• When the level of F-VCCW is lower than VCCWLK (lockout voltage), write operation on the flash memory is
disabled. All blocks are locked and the data in the blocks are completely write protected. For the lockout
voltage, refer to specification. (See Chapter 11. DC Electrical Characteristics)
■ Data Protection during voltage transition
3. Data protection thorough F-RP
• When the F-RP is kept low during power up and power down sequence, write operation on the flash memory
is disabled, write protecting all blocks.
• For the details of F-RP control, refer to the specification. (See Chapter 12. AC Electrical Characteristics for
Flash Memory)
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17. Design Considerations
1. Power Supply Decoupling
To avoid a bad effect to the system by flash memory power switching characteristics, each device should have a
0.1µF ceramic capacitor connected between its F-VCC and GND and between its F-VCCW and GND. Low
inductance capacitors should be placed as close as possible to package leads.
2. F-VCCW Trace on Printed Circuit Boards
Updating the memory contents of flash memories that reside in the target system requires that the printed
circuit board designer pay attention to the F-VCCW Power Supply trace. Use similar trace widths and layout
considerations given to the F-VCC power bus.
3. The Inhibition of Overwrite Operation
Please do not execute reprogramming “0” for the bit which has already been programed “0”. Overwrite
operation may generate unerasable bit.
In case of reprogramming “0” to the data which has been programed “1”.
• Program “0” for the bit in which you want to change data from “1” to “0”.
• Program “1” for the bit which has already been programmed “0”.
For example, changing data from “1011110110111101” to “1010110110111100” requires “1110111111111110”
programming.
4. Power Supply
Block erase, full chip erase, word write and lock-bit configuration with an invalid F-VCCW (See 11. DC
Electrical Characteristics) produce spurious results and should not be attempted.
Device operations at invalid F-VCC voltage (See Chapter 11. DC Electrical Characteristics) produce spurious
results and should not be attempted.
18. Related Document Information(1)
Document No.
FUM99902
Document Name
LH28F160BJ, LH28F320BJ Series Appendix
Note:
1.International customers should contact their local SHARP or distribution sales offices.
Rev. 1.00
SPECIFICATIONS ARE SUBJECT TO CHANGE WITHOUT NOTICE.
Suggested applications (if any) are for standard use; See Important Restrictions for limitations on special applications. See Limited
Warranty for SHARP’s product warranty. The Limited Warranty is in lieu, and exclusive of, all other warranties, express or implied.
ALL EXPRESS AND IMPLIED WARRANTIES, INCLUDING THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR USE AND
FITNESS FOR A PARTICULAR PURPOSE, ARE SPECIFICALLY EXCLUDED. In no event will SHARP be liable, or in any way responsible,
for any incidental or consequential economic or property damage.
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