2N7002K 60V N-Channel Enhancement Mode MOSFET - ESD Protected FEATURES • RDS(ON), VGS@10V,IDS@500mA=3Ω • RDS(ON), [email protected],IDS@200mA=4Ω • Advanced Trench Process Technology • High Density Cell Design For Ultra Low On-Resistance • Very Low Leakage Current In Off Condition • Specially Designed for Battery Operated Systems, Solid-State Relays Drivers : Relays, Displays, Lamps, Solenoids, Memories, etc. • ESD Protected 2KV HBM • Component are in compliance with EU RoHS 2002/95/EC directives MECHANICALDATA • Case: SOT-23 Package D • Terminals : Solderable per MIL-STD-750,Method 2026 3 Top View • Marking : K72 1 2 G S Maximum RATINGS and Thermal Characteristics (TA=25OC unless otherwise noted ) PA RA M E TE R S ym b o l Li mi t U ni t s D r a i n- S o ur c e Vo l t a g e VD S 60 V G a t e - S o ur c e Vo l t a g e VGS +20 V ID 300 mA ID M 2000 mA PD 350 210 mW TJ , TS T G -5 5 to + 1 5 0 RθJ A 357 C o nt i nuo us D r a i n C ur r e nt P ul s e d D r a i n C ur r e nt 1) M a xi m um P o w e r D i s s i p a t i o n O p e r a t i n g J u n c t i o n a n d S t o r a g e Te m p e r a t u r e R a n g e Junction-to Ambient Thermal Resistance(PCB mounted)2 TA = 2 5 O C TA = 7 5 O C O O C C /W Note: 1. Maximum DC current limited by the package 2. Surface mounted on FR4 board, t < 5 sec PAN JIT RESERVES THE RIGHT TO IMPROVE PRODUCT DESIGN,FUNCTIONS AND RELIABILITY WITHOUT NOTICE STAD-JAN.03.2007 PAGE . 1 2N7002K ELECTRICALCHARACTERISTICS P a ra me te r S ym b o l Te s t C o n d i t i o n M i n. Ty p . M a x. U ni t s D r a i n- S o ur c e B r e a k d o w n Vo l t a g e BVD SS V G S = 0 V , ID = 1 0 u A 60 - - V G a t e Thr e s ho l d Vo l t a g e V G S (th) V D S = V G S , ID = 2 5 0 u A 1 - 2 .5 V D r a i n- S o ur c e O n- S t a t e R e s i s t a nc e RD S (o n) VG S =4.5V, I D =200mA - - 4 .0 D r a i n- S o ur c e O n- S t a t e R e s i s t a nc e RD S (o n) VG S =10V, I D =500mA - - 3.0 Ze r o G a t e Vo l t a g e D r a i n C ur r e nt ID S S VD S =60V, VG S =0V - - 1 uA Gate Body Leakage IG S S V G S =+ 2 0 V , V D S = 0 V - - +10 uA Forward Transconductance g fS V D S = 1 5 V , ID = 2 5 0 m A 100 - - mS D i o d e F o rwa rd Vo lta g e VSD IS = 2 0 0 m A , V G S = 0 V - 0 .8 2 1 .3 V To t a l G a t e C h a r g e Qg V D S = 1 5 V , ID = 2 0 0 m A VGS=4.5V - - 0 .8 nC Tu r n - O n D e l a y Ti m e to n - - 20 Tu r n - O f f D e l a y Ti m e to ff - - 40 In p u t C a p a c i t a n c e Ciss - - 35 O ut p ut C a p a c i t a nc e Coss - - 10 R e v e r s e Tr a n s f e r C a p a c i t a n c e C rs s - - 5 S ta ti c Ω Dynamic VD D =30V , RL =150Ω ID =200mA , VG E N =10V RG =10Ω V D S =2 5 V, V G S =0 V f=1 .0 MHZ V DD Switching Test Circuit V IN ns V DD Gate Charge Test Circuit RL pF V GS RL V OUT RG 1mA RG STAD-JAN.03.2007 PAGE . 2 2N7002K ID - Drain-to-Source Current (A) 1.2 V GS = 10V ~ 6.0V I D - Drain Source Current (A) Typical Characteristics Curves (TA=25OC,unless otherwise noted) 5.0V 1 4.0V 0.8 0.6 0.4 3.0V 0.2 0 0 1 2 3 4 1.2 V DS=10V 1 0.8 0.6 0.4 T J=25 O C 0.2 0 0 5 Fig. 1-TYPICAL FORWARD CHARACTERISTIC FIG.1- Output Characteristic R DS(ON) - On-Resistance ( W ) R DS(ON) - On-Resistance ( W ) 4 5 6 5 4 3 2 V GS=4.5V 1 V GS=10V 0 4 3 I D=500mA 2 I D=200mA 1 0 0 0.2 0.4 0.6 0.8 1 2 3 4 5 6 7 8 9 10 V GS - Gate-to-Source Voltage (V) ID - Drain Current (A) FIG.3- On Resistance vs Drain Current RDS(ON) - On-Resistance(Normalized) 3 FIG.2- Transfer Characteristic 5 1.6 2 VGS - Gate-to-Source Voltage (V) VDS - Drain-to-Source Voltage (V) 1.8 1 FIG.4- On Resistance vs Gate to Source Voltage V GS=10V I D=500mA 1.4 1.2 1 0.8 0.6 -50 -25 0 25 50 75 100 125 150 o TJ - Junction Temperature ( C) FIG.5- On Resistance vs Junction Temperature STAD-JAN.03.2007 PAGE . 3 2N7002K V GS - Gate-to-Source Voltage (V) 10 Vgs Qg Qsw Vgs(th) V DS=10V I D=250mA 8 6 4 2 0 0 Qg(th) Qgs I D=250uA 1.1 1 0.9 0.8 -25 0 25 50 75 100 125 150 o 1 88 I D=250uA 86 84 82 80 78 76 74 72 -50 -25 0 25 50 75 100 125 150 TJ - Junction Temperature ( C) Fig.8 - Threshold Voltage vs Temperature IS - Source Current (A) 0.8 o TJ - Junction Temperature ( C) 10 0.6 Fig.7 - Gate Charge BVDSS - Breakdown Voltage (V) Vth - G-S Threshold Voltage (NORMALIZED) 1.2 0.4 Qg - Gate Charge (nC) Qg Qgd Fig.6 - Gate Charge Waveform 0.7 -50 0.2 Fig.9 - Breakdown Voltage vs Junction Temperature V GS=0V 1 0.1 25 O C T J=125 O C -55 O C 0.01 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 VSD - Source-to-Drain Voltage (V) Fig.10 - Source-Drain Diode Forward Voltage STAD-JAN.03.2007 PAGE . 4 2N7002K MOUNTING PAD LAYOUT ORDER INFORMATION • Packing information T/R - 12K per 13" plastic Reel T/R - 3K per 7” plastic Reel LEGAL STATEMENT Copyright PanJit International, Inc 2007 The information presented in this document is believed to be accurate and reliable. The specifications and information herein are subject to change without notice. Pan Jit makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose. Pan Jit products are not authorized for use in life support devices or systems. Pan Jit does not convey any license under its patent rights or rights of others. STAD-JAN.03.2007 PAGE . 5