TOSHIBA TMP91C829

TOSHIBA Original CMOS 16-Bit Microcontroller
TLCS-900/L1 Series
TMP91C829
Semiconductor Company
Preface
Thank you very much for making use of Toshiba microcomputer LSIs.
Before use this LSI, refer the section, “Points of Note and Restrictions”.
Especially, take care below cautions.
**CAUTION**
How to release the HALT mode
Usually, interrupts can release all halts status. However, the interrupts = ( NMI ,
INT0 to INT4), which can release the HALT mode may not be able to do so if they
are input during the period CPU is shifting to the HALT mode (for about 5 clocks of
fFPH) with IDLE1 or STOP mode (IDLE2 is not applicable to this case). (In this
case, an interrupt request is kept on hold internally.)
If another interrupt is generated after it has shifted to HALT mode completely,
halt status can be released without difficultly. The priority of this interrupt is
compare with that of the interrupt kept on hold internally, and the interrupt with
higher priority is handled first followed by the other interrupt.
TMP91C829
CMOS 16-Bit Microcontroller
TMP91C829FG
1.
Outline and Features
TMP91C829 is a high-speed 16-bit microcontroller designed for the control of various mid- to
large-scale equipment.With 2 Kbytes of boot ROM included, it allows your programs to be erased
and rewritten on board. TMP91C829FG comes in a 100-pin flat package. Listed below are the
features.
(1) High-speed 16-bit CPU (900/L1 CPU)
•
Instruction mnemonics are upward compatible with TLCS-90/900
•
16 Mbytes of linear address space
•
General-purpose registers and register banks
•
16-bit multiplication and division instructions; bit transfer and arithmetic instructions
•
Micro DMA: 4 channels (444 ns/2 bytes at 36 MHz)
(2) Minimum instruction execution time: 111 ns (at 36 MHz)
(3) Built-in RAM: 8 Kbytes
Built-in ROM: None
Built-in Boot ROM: 2 Kbytes
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(4) External memory expansion
•
Expandable up to 16 Mbytes (Shared program/data area)
•
Can simultaneously support 8-/16-bit width external data bus
… Dynamic data bus sizing
(5) 8-bit timers: 6 channels
(6) 16-bit timer/event counter: 1 channel
(7) Serial bus interface: 2 channels
(8) 10-bit AD converter: 8 channels
(9) Watchdog timer
(10) Chip select/wait controller: 4 blocks
(11) Interrupts: 35 interrupts
•
9 CPU interrupts: Software interrupt instruction and illegal instruction
•
19 internal interrupts: 7 priority levels are selectable
•
7 external interrupts: 7 priority levels are selectable
(Level mode, rising edge mode and falling edge mode are selectable.)
(12) Input/output ports: 46 pins (Except Data bus (8bit), Address bus (16bit) and
RD
pin)
(13) Standby function
Three HALT modes: IDLE2 (Programmable), IDLE1, STOP
(14) Operating voltage
•
VCC (5 V) = 4.75 V to 5.25 V (fc max = 36 MHz)
•
VCC (3 V) = 3.0 V to 3.6 V (fc max = 36 MHz)
(15) Package
•
100-pin QFP: P-LQFP100-1414-0.50F
Power on and power off the supply
Power on and power off of the supply require the simultaneous execution of the 5 V power supply and 3.3 V
power supply. If the both power supplies cannot be turned on or off simultaneously, turn on or off each power
supply within the specifications shown in Figure 3.1.2 and 3.1.2 “Power On and Power Off of the Supply”.
When power on and power off of the supply is performed on eigher of them, overlap current may run into the
internal logic. Leaving overlap current running results in increase of power dissipation and short LSI life. Please
avoid leaving either of power supplies on.
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ADTRG (AN3/PA3)
AN0 to AN7 (PA0 to PA7)
VREFH
VREFL
AVCC
AVSS
LVCC 3V
HVCC 5V
VSS
CPU (TLCS-900L1)
10-bit 8-ch
AD
converter
Port A
XWA
XBC
XDE
XHL
XIX
XIY
XIZ
XSP
W A
B C
D E
H L
IX
IY
IZ
SP
BOOT
AM0/AM1
RESET
OSC
Clock gear
32 bits
SR F F
PC
RD
X1
X2
EMU0
EMU1
Port 1
(P10 to P17) D8 to D15
Port 2
(P20 to P27) A16 to A23
WR
PZ2 ( HWR )
PZ3
Port Z
Watchdog timer
(WDT)
TXD0 (P80)
RXD0 (P81)
SCLK0/ CTS0 (P82)
D0 to D7
Address bus
A0 to A7
A8 to A15
Serial I/O
(Channel 0)
STS0 (P83)
TXD1 (P84)
RXD1 (P85)
SCK1/ CTS1 (P86)
Data bus
Port 5
BUSRQ (P53)
BUSAK (P54)
Serial I/O
(Channel 1)
STS1 (P87)
Port 8
WAIT (P55)
TA0IN/INT1 (P70)
8-bit timer
(Timer 0)
TA1OUT (P71)
8-bit timer
(Timer 1)
CS/WAIT
controller
(4 blocks)
8-bit timer
(Timer 2)
CS2 (P62)
Interrupt
controller
NMI
INT0 (P56)
8-bit timer
(Timer 3)
TA4IN/INT3 (P73)
8-bit timer
(Timer 4)
TA5OUT (P74)
8-bit timer
(Timer 5)
INT4 (P75)
CS1 (P61)
CS3 (P63)
8-Kbyte RAM
TA3OUT/INT2 (P72)
CS0 (P60)
16-bit timer
(TMRB0)
TB0IN0 (P93)
TB0IN1 (P94)
TB0OUT0 (P95)
TB0OUT1 (P96)
2-Kbyte boot ROM
Port 9
INT5 (P90)
Port 7
( ): Initial function after reset
Figure 1.1 TMP91C829 Block Diagram
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2.
Pin Assignment and Pin Functions
The assignment of input/output pins for the TMP91C829FG, their names and functions are as
follows:
2.1
Pin Assignment Diagram
Figure 2.1.1 shows the pin assignment of the TMP91C829FG.
Pin
No.
Pin
No.
Pin name
P27/A23
P26/A22
P25/A21
P24/A20
P23/A19
P22/A18
P21/A17
P20/A16
A15
A14
A13
A12
64
65
66
67
68
69
70
71
72
73
74
75
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
RD
WR
LVCC (3 V)
PZ2/ HWR
VSS
PA0/AN0
PA1/AN1
PA2/AN2
ADTRG /PA3/AN3
PA4/AN4
PA5/AN5
PA6/AN6
PA7/AN7 100
75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
50
76
49
77
48
78
47
79
46
80
45
81
44
82
43
83
42
84
41
85
TMP91C829FG
40
86
39
87
38
88
Top view
37
89
36
90
35
91
34
92
P-LQFP100-1414-0.50F
33
93
32
94
31
95
30
96
29
97
28
98
27
99
26
100
1
2
3
4
5
6
7
HVCC (5 V)
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
D5
D4
D3
D2
D1
D0
P96/TB0OUT1
P95/TB0OUT0
P94/TB0IN1
P93/TB0IN0
P90/INT5
P75/INT4
P74/TA5OUT
P73/TA4IN/INT3
P72/TA3OUT/INT2
P71/TA1OUT
P70/TA0IN/INT1
BOOT
VSS
P17/D15
P16/D14
P15/D13
P14/D12
P13/D11
P12/D10
P11/D9
P10/D8
D7
D6
RESET
AM1
X1
DVSS
X2
LVCC (oscillator)
AM0
P63/ CS3
25 P62/ CS2
24 P61/ CS1
VREFL 2
23 P60/ CS0
22 EMU1
AVSS 3
AVCC 4
21 EMU0
20 P87/ STS1
19 P86/SCLK0/ CTS1
5
VSS 6
P53/ BUSRQ
63
62
61
60
59
58
57
56
55
54
53
52
51
8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25
VREFH 1
NMI
Pin name
7
HVCC (5 V) 8
P54/ BUSAK 9
P55/ WAIT 10
18 P85/RXD1
17 P84/TXD1
16 P83/ STS0
15 P82/SCLK0/ CTS0
14 P81/RXD0
P56/INT0 11
PZ3 12
P80/TXD0 13
Figure 2.1.1 Pin Assignment Diagram (100-pin LQFP)
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2.2
Pin Names and Functions
The names of the input/output pins and their functions are described below.
Table 2.2.1 Pin Names and Functions (1/3)
Pin Name
Number
of Pins
I/O
Functions
D0 to D7
8
I/O
Data (Lower): Bits 0 to 7 of data bus
P10 to P17
8
I/O
Port 1: I/O port that allows I/O to be selected at the bit level
(when used to the external 8-bit bus)
D8 to D15
P20 to P27
I/O
8
A16 to A23
A8 to A15
8
Data (Upper): Bits 8 to15 of data bus
Output
Port 2: Output port
Output
Address: Bits 16 to 23 of address bus
Output
Address: Bits 8 to 15 of address bus
A0 to A7
8
Output
Address: Bits 0 to 7 of address bus
RD
1
Output
Read: Strobe signal for reading external memory
WR
1
Output
P53
1
I/O
BUSRQ
P54
Input
1
BUSAK
I/O
Output
Write: Strobe signal for writing data to pins D0 to D7
Port 53: I/O port (with pull-up resistor)
Bus request: Signal used to request bus release (High impedance)
Port 54: I/O port (with pull-up resistor)
Bus acknowledge: Signal used to acknowledge bus release
(High impedance)
P55
1
P56
I/O
Input
WAIT
1
INT0
I/O
Input
Port 55: I/O port (with pull-up resistor)
Wait: Pin used to request CPU bus wait.
Port 56: I/O port (with pull-up resistor)
Interrupt request pin0: Interrupt request pin with programmable level/rising
edge/falling edge
P60
1
Output
Port 60: Output port
Output
Chip select 0: Outputs 0 when address is within specified address area
1
Output
Port 61: Output port
Output
Chip select 1: Outputs 0 when address is within specified address area
Output
Port 62: Output port
Output
Chip select 2: Outputs 0 when address is within specified address area
Output
Port 63: Output port
Output
Chip select 3: Outputs 0 when address is within specified address area
CS0
P61
CS1
P62
1
CS2
P63
1
CS3
P70
1
I/O
Port 70: I/O port
TA0IN
Input
Timer A0 input
INT1
Input
Interrupt request pin2: Interrupt request pin with programmable level/rising
edge/falling edge
P71
1
TA1OUT
P72
TA3OUT
INT2
I/O
Output
1
I/O
Output
Input
Port 71: I/O port
Timer A0 or timer A1 output
Port 72: I/O port
Timer A2 or timer A3 output
Interrupt request pin2: Interrupt request pin with programmable level/rising
edge/falling edge
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Table 2.2.2 Pin Names and Functions (2/3)
Pin Name
P73
Number
of Pins
1
I/O
I/O
TA4IN
Input
INT3
Input
Functions
Port 73: I/O port
Timer A4 input
Interrupt request pin 3: Interrupt request pin with programmable level/rising
edge/falling edge
P74
1
TA5OUT
P75
1
INT4
P80
1
I/O
Output
1
RXD0
P82
I/O
Input
TXD0
P81
I/O
Output
I/O
Input
1
I/O
SCLK0
Input
CTS0
I/O
P83
1
I/O
STS0
P84
1
I/O
Output
1
RXD1
P86
I/O
Input
1
I/O
SCLK1
Input
CTS1
I/O
P87
1
I/O
STS1
P90
Timer A4 or timer A5 output
Port 75: I/O port
Interrupt request pin 4: Interrupt request pin with programmable
Port 80: I/O port (with pull-up resistor)
Serial send data 0: Programmable open-drain output pin
Port 81: I/O port (with pull-up resistor)
Serial receive data 0
Port 82: I/O port: (with pull-up resistor)
Serial clock I/O 0
Serial data send enable 0 (Clear to send)
Port 83: I/O port (with pull-up resistor)
Serial data request signal 0
TXD1
P85
Port 74: I/O port
Port 84: I/O port (with pull-up resistor)
Serial send data 0: Programmable open-drain output pin
Port 85: I/O port (with pull-up resistor)
Serial receive data 1
Port 86: I/O port: (with pull-up resistor)
Serial clock I/O 1
Serial data send enable 1 (Clear to send)
Port 87: I/O port (with pull-up resistor)
Serial data request signal 1
1
INT5
I/O
Input
Port 90: I/O port
Interrupt request pin 5: Interrupt request pin with programmable level/rising
edge/falling edge
P93
1
TB0IN0
P94
1
TB0IN1
P95
1
TB0OUT0
P96
Port 93: I/O port
Timer B0 input 0
I/O
Port 94: I/O port
Input
Timer B0 input 1
I/O
Port 95: I/O port
Output
1
TB0OUT1
PA0 to PA7
I/O
Input
I/O
Output
Port 96: I/O port
Timer B0 output 1
Input
Port A0 to A7: Pin used to input port
AN0 to AN7
Input
Analog input 0 to 7: Pins used to input to AD converter
ADTRG
Input
PZ2
8
Timer B0 output 0
1
Output
HWR
PZ3
I/O
1
I/O
A/D trigger: Signal used to request AD start (PA3)
Port Z2: I/O port (with pull-up resistor)
High write: Strobe signal for writing data to pins D8 to D15
Port Z3: I/O port (with pull-up resistor)
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Table 2.2.3 Pin Names and Functions (3/3)
Pin Name
Number
of Pins
I/O
Functions
BOOT
1
Input
This pin sets boot mode (with pull-up resistor)
NMI
1
Input
Non-maskable interrupt request pin: Interrupt request pin with programmable
AM0 to AM1
2
Input
falling edge level or with both edge levels programmable
Address mode : External data bus with select pin
When external 16-bit bus is fixed or external 8- or 16-bit buses are mixed,
AM1 = 0 , AM0 = 1
When external 8-bit bus is fixed,
AM1 = 0 , AM0 = 0
RESET
1
Input
Reset: Initializes TMP91C829 (with pull-up resistor)
VREFH
1
Input
Pin for reference voltage input to AD converter (H)
VREFL
1
Input
AVCC
1
I/O
AVSS
1
GND supply pin for AD converter
X1/X2
2
Oscillator connection pins
Pin for reference voltage input to AD converter (L)
Power supply pin for AD converter
HVCC
2
Power supply pins (5 V)
LVCC
2
Power supply pins (3 V)
DVSS
3
EMU0
1
Output
GND pins (0 V)
Open pin
EMU1
1
Output
Open pin
Note 1: An external DMA controller cannot access the device’s built-in memory or built-in I/O devices using
the BUSRQ and BUSAK signal.
Note 2: All pins which have a built-in pull-up resistor (Other than the RESET pin and the BOOT pin ) can be
disconnected from the resistor in software.
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3.
Operation
This section describes the basic components, functions and operation of the TMP91C829.
Notes and restrictions which apply to the various items described here are outlined in section 7.
“Points to Note and Restrictions” at the end of this databook.
3.1
CPU
The TMP91C829 incorporates a high-performance 16-bit CPU (The 900/L1 CPU). For a
description of this CPU’s operation, please refer to the section of this databook which describes
the TLCS-900/L1 CPU.
The following sub sections describe functions peculiar to the CPU used in the TMP91C829;
these functions are not covered in the section devoted to the TLCS-900/L1 CPU.
3.1.1
Reset
When resetting the TMP91C829 microcontroller, ensure that the power supply voltage is
within the operating voltage range, and that the internal high-frequency oscillator has
stabilized. Then set the RESET input to low level at least for 10 system clocks (8.89 μs at
36 MHz). Thus, when turn on the switch, be set to the power supply voltage is within the
operating voltage range, and that the internal high-frequency oscillator has stabilized.
Then hold the RESET input to low-level at least for 10 system clocks.
Clock gear is intitialized 1/16 mode by reset operation. It means that the system clock
mode fSYS is set to fc/32 (= fc/16 ×1/2).
When the reset is accept, the CPU:
•
Sets the program counter (PC) as follows in accordance with the reset vector stored
at address FFFF00H to FFFF02H:
PC<0:7>
PC<8:15>
PC<16:23>
←
←
←
Data in location FFFF00H
Data in location FFFF01H
Data in location FFFF02H
•
Sets the stack pointer (XSP) to 100H.
•
Sets bits <IFF0:2> of the status register (SR) to 111. (Thereby setting the interrupt
level mask register to level 7.)
•
Sets the <MAX> bit of the status register to 1 (MAX mode).
(Note: As this product does not support MIN mode, do not write a 0 to the <MAX>
bit.)
•
Clears bits <RFP0:2> of the status register to 000. (Thereby selecting register
bank 0.)
When the reset is cleared, the CPU starts executing instructions according to the
program counter settings. CPU internal registers not mentioned above do not change
when the reset is cleared.
When the reset is accepted, the CPU sets internal I/O, ports and other pins as follows.
•
Initializes the internal I/O registers.
•
Sets the port pins, including the pins that also act as internal I/O, to
general-purpose input or output port mode.
Note: The CPU internal register (except to PC, SR, XSP) and internal RAM data do not
change by resetting.
Figure 3.1.1 shows the timing of a reset for the TMP91C829.
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HWR
Pull up (Internal)
High-Z
Data-in
Data-in
sampling
(PZ2 input mode)
sampling
(After reset released, starting 2 waits read cycle)
Data-in
0FFFF00H
Read
WR
D0 to D15
RD
D0 to D15
CS2
CS0, CS1,CS3
A23 to A0
RESET
fFPH
TMP91C829
Write
Figure 3.1.1 TMP91C829 Reset Timing Example
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TMP91C829
3.1.2
Power On and Power Off of the Supply
VCC 5
VCC 3.3
RESET
Max 1 [s]
Min 10 [ms]
Min 0 [s]
Max 1 [s]
Oscillator operation time + Clock doubler stabilization time
Figure 3.1.2 Power Supply On/Off Timing
3.2
Outline of Operation Modes
There are multi chip and multi boot modes. Which mode is selected depends on the device’s
pin state after a reset.
•
Multi chip mode: The device normally operations in this mode. After a reset, the device starts
executing the external memory program.
•
Multi boot mode: This mode is used to rewrite the external flash memory by serial transfer
(UART) or ATAPI transfer.
After a reset, internal boot program starts up, executing a on-board rewrite
program.
Table 3.2.1 Operation Mode Setup Table
Operation Mode
Mode Setup Input Pin
RESET
BOOT
Multi chip mode
H
Multi boot mode
L
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3.3
Memory Map
Figure 3.3.1 is a memory map of the TMP91C829.
Multi chip mode
000000H
Multi boot mode
000000H
Internal I/O
(4 Kbytes)
000100H
Internal I/O
(4 Kbytes)
Direct area (n)
000100H
001000H
001000H
Internal RAM
(8 Kbytes)
Internal RAM
(8 Kbytes)
003000H
003000H
External memory
01F800H
Internal boot ROM
(2 Kbytes)
16-Mbyte area
(r32)
(−r32)
01FFFFH
(r32+)
(r32 + d8/16)
(r32 + r8/16)
External memory
(nnn)
External memory
FFF800H
FFFEFFH
FFFF00H
FFFFFFH
Vector table
(256 bytes)
Internal boot ROM
(2 Kbytes)
Vector table
(256 bytes)
FFFF00H
FFFFFFH
(
= Internal area)
Figure 3.3.1 TMP91C829 Memory Map
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3.4
Triple Clock Function and Standby Function
The TMP91C829 contains (1) a clock gearing system, (2) a standby controller, and (3) a
noise-reducing circuit. It is used for low-power, low-noise systems.
The clock operating mode is as follows: (a) Single clock mode (X1, X2 pins only).
Figure 3.4.1 shows a transition figure.
Reset
(fOSCH/32)
IDLE2 mode
(I/O operate)
IDLE1 mode
(Operate only oscillator)
Instruction
Interrupt
Instruction
Interrupt
Release reset
NORMAL mode
(fOSCH/gear value/2)
Instruction
Interrupt
STOP mode
(Stops all circuits)
Clock mode transition figure
Figure 3.4.1 System Clock Block Diagram
The clock frequency input from the X1 and X2 pins is called fc. In case of TMP91C829, fc =
fFPH. The system clock fSYS is defined as the divided clock of fFPH, and one cycle of fSYS is
regarded as one state.
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3.4.1
Block Diagram of System Clock
SYSCR0<WUEF>
SYSCR2<WUPTM1:0>
SYSCR0
<PRCK1:0>
Warm-up timer (High-frequency oscillator)
φT
φT0
fc/16
fFPH
÷2 ÷4
fFPH
÷2
fc
fSYS
fc/2
fc/4
fc/8
fc/16
X1
X2
High-frequency
oscillator
fOSCH
÷2
÷4
÷8 ÷16
SYSCR1<GEAR2,0>
Clock gear
fSYS
CPU
TMRA01 to TMRA45
φT0
ROM
Prescaler
RAM
Interrupt
controller
TMRB0
Prescaler
WDT
I/O ports
SIO0, SIO1
Prescaler
Figure 3.4.2 Block Diagram of System Clock
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3.4.2
SFRs
SYSCR0 Bit symbol
(00E0H)
7
6
5
4
−
−
−
−
Read/Write
After reset
Function
1
0
−
WUEF
PRCK1
PRCK0
1
Always
0
Always
1
Always
0
Always
0
Always
write “1”.
write “0”.
write “1”.
write “0”.
write “0”.
7
6
5
4
0
Warm-up
timer
Write 0:
Don’t care
Write 1:
Start timer
Read 0:
End
warm-up
Read 1:
Do not end
warm-up
2
1
0
GEAR2
GEAR1
GEAR0
R/W
7
Read/Write
After reset
Function
00: fFPH
01: Reserved
10: fc/16
11: Reserved
−
0
Always
write “0”.
Function
SYSCR2 Bit symbol
0
0
Select prescaler clock
3
Read/Write
After reset
(00E2H)
2
R/W
SYSCR1 Bit symbol
(00E1H)
3
0
0
0
Select gear value of high frequency (fc)
000: fc
001: fc/2
010: fc/4
011: fc/8
100: fc/16
101: (Reserved)
110: (Reserved)
111: (Reserved)
6
5
4
3
2
−
WUPTM1
WUPTM0
HALTM1
HALTM0
DRVE
R/W
R/W
R/W
R/W
R/W
R/W
1
0
1: Drive the
pin during
STOP
mode
0
Always
write “0”.
1
0
Warm-up timer
00: Reserved
8
01: 2 inputted frequency
14
10: 2 inputted frequency
16
11: 2 inputted frequency
1
HALT mode
00: Reserved
01: STOP mode
10: IDLE1 mode
11: IDLE2 mode
1
0
Figure 3.4.3 SFR for System Clock
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7
EMCCR0 Bit symbol
(00E3H)
Read/Write
After reset
Function
6
5
4
3
2
1
0
PROTECT
−
−
−
−
EXTIN
−
−
R
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
Protect flag Always
0: OFF
write “0”.
1: ON
1
Always
write “1”.
0
Always
write “0”.
0
Always
write “0”.
1
Always
write “1”.
1
Always
write “1”.
0
1: External
clock
EMCCR1 Bit symbol
(00E4H)
Read/Write
After reset
Writing 1FH turns protections OFF.
Writing any value other than 1FH turns protection ON.
Function
Figure 3.4.4 SFR for Noise Reducing
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3.4.3
System Clock Controller
The system clock controller generates the system clock signal (fSYS) for the CPU core and
internal I/O. It contains a clock gear circuit for high-frequency (fc) operation. The register
SYSCR1<GEAR0:2> sets the high-frequency clock gear to either 1, 2, 4, 8, or 16 (fc, fc/2, fc/4,
fc/8, or fc/16). These functions can reduce the power consumption of the equipment in which
the device is installed.
The initialization<GEAR0:2> = 100 will cause the system clock (fSYS) to be set to fc/32
(fc/16 × 1/2) after a reset.
For example, fSYS is set to 1.125 MHz when the 36 MHz oscillator is connected to the X1
and X2 pins.
Clock gear controller
The fFPH is set according to the contents of the clock gear select register SYSCR1
<GEAR0:2> to either fc, fc/2, fc/4, fc/8, or fc/16. Using the clock gear to select a lower
value of fFPH reduces power consumption.
Example: Changing to a high-frequency gear
SYSCR1
EQU
00E1H
LD
(SYSCR1), XXXX0000B
;
Changes fSYS to fc/2.
X: Don’t care
(Changing to high-frequency clock gear)
To change the clock gear, write the appropriate value to the SYSCR1<GEAR0:2>
register. The value of fFPH will not change until a period of time equal to the warm-up
time has elapsed from the point at which the register is written to.
There is a possibility that the instruction immediately following the instruction
which changes the clock gear will be executed before the new clock setting comes into
effect. To ensure that this does not happen, insert a dummy instruction (to execute a
write cycle) as follows:
Example:
SYSCR1
EQU
00E1H
LD
(SYSCR1), XXXX0001B
;
Changes fSYS to fc/4.
LD
(DUMMY), 00H
;
Dummy instruction.
Instruction to be executed after clock gear has changed.
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3.4.4
Prescaler Clock Controller
For the internal I/O (TMRA01:45, TMRB0 and SIO0, SIO1), there is a prescaler which
can divide the clock.
The φT clock input to the prescaler is either the clock fFPH divided by 2 or the clock fc/16
divided by 2. The setting of the SYSCR0<PRCK0:1> register determines which clock signal
is input.
The φT0 clock input to the prescaler is either the clock fFPH divided by 4 or the clock fc/16
divided by 4. The setting of the SYSCR0<PRCK0:1> register determines which clock signal
is input.
3.4.5
Noise Reduction Circuits
Noise reduction circuits are built in, allowing implementation of the following features.
(1) Single drive for high-frequency oscillator
(2) Protection of register contents
The above functions are performed by making the appropriate settings in the EMCCR0
and EMCCR1 registers.
(1) Single drive for high-frequency oscillator
(Purpose)
Not need twin drive and protect mistake operation by inputted noise to X2 pin
when the external oscillator is used.
(Block diagram)
fOSCH
X1 pin
Enable oscillation (STOP + EMCCR0<EXTIN>)
X2 pin
(Setting method)
When a 1 is written to the EMCCR0<EXTIN>, the oscillator is disabled and is
operated as a buffer. The X2 pin always outputs a 1.
<EXTIN> is initialized to 0 by a reset.
Note: Do not write EMCCR0<EXTIN> = “1” when using external resonator.
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(2) Protection of register contents
(Purpose)
An item for mistake operation by inputted noise.
To execute the program certainty which is occurred mistake operation, the
protect-register can be disabled write operation for the specific SFR.
Write disabled SFRs
1. CS/WAIT controller
B0CS, B1CS, B2CS, B3CS, BEXCS,
MSAR0, MSAR1, MSAR2, MSAR3,
MAMR0, MAMR1, MAMR2, MAMR3
2. Clock gear (only EMCCR1 can be written to.)
SYSCR0, SYSCR1, SYSCR2, EMCCR0
(Block diagram)
Protect register
EMCCR0<PROTECT>
To EMCCR1
Write value other than 1FH
S Q
Write 1FH
R
Write signal SFR
Write signal to the disabled SFR
Write signal to the other SFR
(Setting method)
Writing any value other than 1FH to the EMCCR1 register turns on protection,
thereby preventing the CPU from writing to the specific SFR.
Writing 1FH to EMCCR1 turns off protection.
The protection status is set in EMCCR0<PROTECT>.
Resetting initializes the protection status to off.
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3.4.6
Standby Controller
(1) HALT modes
When the HALT instruction is executed, the operating mode switches to IDLE2,
IDLE1 or STOP mode, depending on the contents of the SYSCR2<HALTM1:0>
register.
The subsequent actions performed in each mode are as follows:
a.
IDLE2: The CPU only is halted.
In IDLE2 mode internal I/O operations can be performed by setting the
following registers.
Table 3.4.1 shows the registers of setting operation during IDLE2 mode.
Table 3.4.1 The Registers of Setting Operation during IDLE2 Mode
Internal I/O
SFR
TMRA01
TA01RUN<I2TA01>
TMRA23
TA23RUN<I2TA23>
TMRA45
TA45RUN<I2TA45>
TMRB0
TB0RUN<I2TB0>
SIO0
SC0MOD1<I2S0>
SIO1
SC1MOD1<I2S0>
AD converter
ADMOD1<I2AD>
WDT
WDMOD<I2WDT>
b.
IDLE1: Only the oscillator to operate.
c.
STOP: All internal circuits stop operating.
The operation of each of the different HALT modes is described in Table 3.4.2.
Table 3.4.2 I/O Operation during HALT Modes
HALT Mode
IDLE2
IDLE1
STOP
SYSCR2<HALTM1:0>
11
10
01
CPU
I/O ports
Stop
Maintain same state as when HALT instruction was executed.
See Table 3.4.5,
Table 3.4.6
Block
TMRA, TMRB
SIO
AD converter
Can be selected
Stopped
WDT
Interrupt controller
Operational
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(2) How to clear a HALT mode
The halt state can be cleared by a reset or by an interrupt request. The combination
of the value in <IFF0:2> of the interrupt mask register and the current HALT mode
determine in which ways the HALT mode may be cleared. The details associated with
each type of halt state clearance are shown in Table 3.4.3.
•
Clearance by interrupt request
Whether or not the HALT mode is cleared and subsequent operation depends on
the status of the generated interrupt. If the interrupt request level set before
execution of the HALT instruction is greater than or equal to the value in the
interrupt mask register, the following sequence takes place: The HALT mode is
cleared, the interrupt is then processed, and the CPU then resumes execution
starting from the instruction following the HALT instruction. If the interrupt
request level set before execution of the HALT instruction is less than the value in
the interrupt mask register, the HALT mode is not cleared. (If a non-maskable
interrupt is generated, the HALT mode is cleared and the interrupt processed,
regardless of the value in the interrupt mask register.)
However, for INT0 to INT4 only, even if the interrupt request level set before
execution of the HALT instruction is less than the value in the interrupt mask
register, the HALT mode is cleared. In this case, the interrupt is not processed and
the CPU resumes execution starting from the instruction following the HALT
instruction. The interrupt request flag remains set to 1.
Note:
•
Usually, interrupts can release all halts status. However, the interrupts ( NMI ,
INT0 to INT4) which can release the HALT mode may not be able to do so if
they are input during the period CPU is shifting to the HALT mode (for about 5
clocks of fFPH) with IDLE1 or STOP mode (IDLE2 is not applicable to this case).
(In this case, an interrupt request is kept on hold internally.)
If another interrupt is generated after it has shifted to HALT mode completely,
halt status can be released without difficulty. The priority of this interrupt is
compared with that of the interrupt kept on hold internally, and the interrupt with
higher priority is handled first followed by the other interrupt.
Clearance by reset
Any halt state can be cleared by a reset.
When STOP mode is cleared by a RESET signal, sufficient time (at least 3 ms)
must be allowed after the reset for the operation of the oscillator to stabilize.
When a HALT mode is cleared by resetting, the contents of the internal RAM
remain the same as they were before execution of the HALT instruction. However,
all other settings are reinitialized. (Clearance by an interrupt affects neither the
RAM contents nor any other settings – the state which existed before the HALT
instruction was executed is retained.)
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Table 3.4.3 Source of Halt State Clearance and Halt Clearance Operation
Status of Received Interrupt
Interrupt Enabled
Interrupt Disabled
(Interrupt level) ≥ (Interrupt mask) (Interrupt level) < (Interrupt mask)
Interrupt
Source of Halt State Clearance
HALT Mode
IDLE2
IDLE1 STOP
IDLE2
*1
IDLE1 STOP
−
−
−
−
−
*1
○
○
○*1
×
×
×
×
×
×
×
×
×
×
♦
×
×
×
×
×
INTRX0, INTTX0
♦
×
×
×
×
×
INTRX1, INTTX1
♦
×
×
×
×
×
INTAD
♦
×
×
×
×
×
NMI
♦
♦
INTWDT
♦
×
♦
×
INT0 to INT4 (Note)
♦
♦
♦
INT5
♦
INTTA0 to INTTA5
♦
INTTB00, INTTB01, INTTBOF0
RESET
−
Reset initializes the LSI
♦: After clearing the HALT mode, CPU starts interrupt processing.
○: After clearing the HALT mode, CPU resumes executing starting from instruction following the HALT
instruction.
×: Cannot be used to clear the HALT mode.
−: The priority level (Interrupt request level) of non-maskable interrupts is fixed to 7, the highest priority
level. There is not this combination type.
*1: The HALT mode is cleared when the warm-up time has elapsed.
Note: When the HALT mode is cleared by INT0 to INT4 interrupt of the level mode in the interrupt enabled
status, hold the level until starting interrupt processing. Changing level before holding level, interrupt
processing is correctly started.
(Example: Clearing IDLE1 mode)
An INT0 interrupt clears the halt state when the device is in IDLE1 mode.
Address
8200H
LD
(P5FC), 40H
; Sets P56 to INT0
8203H
LD
(IIMC0), 00H
; Sets INT0 interrupt rising edge.
8206H
LD
(INTE0AD), 06H
; Sets INT0 interrupt level to 6.
8209H
EI
5
; Sets interrupt level to 5 for CPU.
820BH
LD
(SYSCR2), 28H
820EH
HALT
; Sets HALT mode to IDLE1 mode.
; Halts CPU.
INT0 interrupt routine
INT0
RETI
820FH
LD
XX, XX
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(3) Operation
a.
IDLE2 mode
In IDLE2 mode only specific internal I/O operations, as designated by the
IDLE2 setting register, can take place. Instruction execution by the CPU stops.
Figure 3.4.5 illustrates an example of the timing for clearance of the IDLE2
mode halt state by an interrupt.
X1
A0 to A23
D0 to D15
Data
Data
RD
WR
Clearing interrupt
IDLE2 mode
Figure 3.4.5 Timing Chart for IDLE2 Mode Halt State Cleared by Interrupt
b.
IDLE1 mode
In IDLE1 mode, only the internal oscillator and the RTC continue to operate.
The system clock in the MCU stops.
In the halt state, the interrupt request is sampled asynchronously with the
system clock; however, clearance of the halt state (e.g., restart of operation) is
synchronous with it.
Figure 3.4.6 illustrates the timing for clearance of the IDLE1 mode halt state by
an interrupt.
X1
A0 to A23
D0 to D15
Data
Data
RD
WR
Clearing interrupt
IDLE1 mode
Figure 3.4.6 Timing Chart for IDLE1 Mode Halt State Cleared by Interrupt
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c.
STOP mode
When STOP mode is selected, all internal circuits stop, including the internal
oscillator pin status in STOP mode depends on the settings in the
SYSCR2<DRVE> register. Table 3.4.5, Table 3.4.6 summarizes the state of these
pins in STOP mode.
After STOP mode has been cleared system clock output starts when the
warm-up time has elapsed, in order to allow oscillation to stabilize. See the
sample warm-up times in Table 3.4.4.
Figure 3.4.7 illustrates the timing for clearance of the STOP mode halt state by
an interrupt.
Warm-up time
X1
A0 to A23
D0 to D15
Data
Data
RD
WR
Interrupt for
release
STOP
mode
Figure 3.4.7 Timing Chart for STOP Mode Halt State Cleared by Interrupt
Table 3.4.4 Sample Warm-up Times after Clearance of STOP Mode
at fOSCH = 36 MHz
SYSCR2<WUPTM1:0>
8
01 (2 )
10 (214)
11 (216)
7.1 μs
0.455 ms
1.820 ms
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Table 3.4.5 Input buffer State Table
Input Buffer State
Port Name
Input
Function
Name
When the CPU is
Operating
During
Reset
When
Used as
Function
Pin
OFF
*1
−
D0-D7
P10-17
D8-D15
P53(*6)
BUSRQ
ON
ON
P54(*6)
−
OFF
−
P55(*6)
WAIT
P56(*6)
INT0
P70
P71
P72
P73
In HALT mode
(IDLE2/IDLE1)
When Used When Used
When Used
as Input
as Function
as Input Port
Port
Pin
−
OFF
ON
*2
−
OFF
In HALT mode (STOP)
<DRVE>=1
When
Used as
Function
Pin
OFF
When
Used as
Input Port
<DRVE>=0
When
Used as
Function
Pin
−
OFF
ON
ON
ON
ON
−
OFF
−
OFF
−
OFF
−
ON
ON
ON
ON
ON
ON
INT1
ON
−
INT2
ON
TA4IN
INT3
−
*2
ON
ON
ON
ON
ON
−
ON
*3
ON
−
−
INT4
ON
ON
ON
ON
−
−
−
−
ON
ON
ON
OFF
−
−
−
−
P82(*6)
P85(*6)
RXD1
ON
SCLK1
−
ON
ON
ON
ON
ON
OFF
OFF
CTS1
P87(*6)
−
P90
INT5
P93
TB0IN0
P94
TB0IN1
P95-P96
−
PA0-PA2(*7)
AN0-AN2
ADTRG
PA4-PA7(*7)
AN4-AN7
−
BOOT (*6)
−
NMI
−
RESET (*6)
−
AM0,AM1
−
−
−
−
−
ON
ON
ON
OFF
−
−
−
−
*4
*4
*4
*4
AN3
PZ2-PZ3(*6)
X1
OFF
CTS0
−
PA3(*7)
OFF
ON
SCLK0
P83-P84(*6)
P86(*6)
*2
−
OFF
P75
−
−
OFF
−
P74
RXD0
ON
*3
ON
−
P81(*6)
OFF
OFF
TA0IN
P80(*6)
When
Used as
Input Port
OFF
ON
*5
ON
*4
OFF
*4
ON
OFF
*4
ON
*4
*2
ON
−
ON
−
−
ON
−
ON
−
OFF
ON
OFF
ON: The buffer is always turned on. A current flows the *1: The buffer is turned on if read external.
input buffer if the input pin is not driven.
OFF: The buffer is always turned off.
*2: The buffer is turned on if access port.
-: No applicable
*3: The buffer is turned off if FC register is “0”. The
buffer is turned on if FC register is “1”.
*4: The buffer is always enable to input.
*5: The buffer is turned on if read port.
*6: Port having a pull-up resistor.(Programmable)
*7: AIN input does not cause a current to flow through
the buffer.
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Table 3.4.6 Output buffer State Table
Output Buffer State
Port
Name
Output
Function
Name
−
D0-D7
P10-P17
D8-D15
P20-P27
A16-A23
−
A8-A15
−
A0-A7
−
RD
−
WR
P53
−
P54
BUSAK
P55-P56
−
P60
CS0
P61
CS1
P62
CS2
P63
CS3
P70
−
P71
TA1OUT
P72
TA3OUT
When the CPU is
Operating
During
Reset
When
Used as
Function
Pin
−
*1
When
Used as
Output
Port
−
In HALT mode
(IDLE2/IDLE1)
When
Used as
Function
Pin
OFF
ON
When
Used as
Output
Port
−
In HALT mode (STOP)
<DRVE>=1
When
Used as
Function
Pin
OFF
ON
When Used
as Output
Port
<DRVE>=0
When
Used as
Function
Pin
−
−
ON
OFF
OFF
ON
ON
ON
ON
−
−
−
−
−
ON
ON
ON
OFF
−
−
−
−
ON
OFF
−
−
−
−
ON
ON
ON
ON
−
−
−
−
ON
ON
ON
OFF
P73
−
−
−
−
−
P74
TA5OUT
ON
ON
ON
OFF
P75
−
−
−
−
P80
TXD0
ON
P81
−
−
P82
SCLK0
P83
STS0
P84
TXD1
P85
−
P86
SCLK1
P87
STS1
P90
−
P93-P94
−
P95
TB0OUT0
P96
TB0OUT1
PZ2
HWR
PZ3
−
X2
−
When
Used as
Output
Port
−
ON
ON
−
ON
ON
−
ON
OFF
−
−
ON
ON
ON
OFF
−
−
−
−
ON
ON
ON
OFF
−
−
−
−
OFF
ON
ON
ON
ON
−
−
OFF
ON
−
*3
−
*3
ON: The buffer is always turned on.
When the bus is *1: The buffer is turned on if write external.
released, however, output buffers for some pins are
turned off.
OFF: The buffer is always turned off.
*2: Port having a pull-up resistor.(Programmable)
*3: The buffer output High level.
-: No applicable
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3.5 Interrupts
Interrupts are controlled by the CPU interrupt mask register SR<IFF2:0> and by the built-in
interrupt controller.
The TMP91C829 has a total of 35 interrupts divided into the following five types:
•
Interrupts generated by CPU: 9 sources
(Software interrupts, illegal instruction interrupt)
•
Interrupts on external pins ( NMI and INT0 to INT5): 7 sources
•
Internal I/O interrupts: 19 sources
A (Fixed) individual interrupt vector number is assigned to each interrupt.
One of seven (Variable) priority level can be assigned to each maskable interrupt.
The priority level of non-maskable interrupts are fixed at 7 as the highest level.
When an interrupt is generated, the interrupt controller sends the piority of that interrupt to
the CPU. If multiple interrupts are generated simultaneously, the interrupt controller sends
the interrupt with the highest priority to the CPU. (The highest priority is level 7 using for
non-maskable interrupts.)
The CPU compares the priority level of the interrupt with the value of the CPU interrupt
mask register <IFF2:0>. If the priority level of the interrupt is higher than the value of the
interrupt mask register, the CPU accepts the interrupt.
The interrupt mask register <IFF2:0> value can be updated using the value of the EI
instruction (EI num sets <IFF2:0> data to num).
For example, specifying “EI 3” enables the maskable interrupts which priority level set in the
interrupt controller is 3 or higher, and also non-maskable interrupts.
Operationally, the DI instruction (<IFF2:0> = 7) is identical to the EI 7 instruction. DI
instruction is used to disable maskable interrupts because of the priority level of maskable
interrupts is 0 to 6. The EI instruction is vaild immediately after execution.
In addition to the above general-purpose interrupt processing mode, TLCS-900/L1 has a
micro DMA interrupt processing mode as well. The CPU can transfer the data (1 or 2 or 4 bytes)
automatically in micro DMA mode, therefore this mode is used for speed up interrupt
processing, such as transferring data to the internal or external peripheral I/O. Moreover,
TMP91C829 has software start function for micro DMA processing request by the software not
by the hardware interrupt.
Figure 3.5.1 shows the overall interrupt processing flow.
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Interrupt processing
Interrupt specified
by micro DMA
start vector?
No
Interrupt vector value “V” read
Interrupt request F/F clear
General-purpose
interrupt
processing
Yes
Micro DMA
soft start request
Clear interrupt requenst flag
Data transfer by micro DMA
Count ← Count − 1
PUSH
PC
PUSH
SR
SR<IFF2:0> ← Level of
accepted
interrupt + 1
INTNEST ← INTNEST + 1
Count = 0
Micro DMA processing
Yes
Clear vector register generating
micro DMA transfer end
interrupt (INTTC0 to INTTC3)
No
PC ← (FFFF00H + V)
Interrupt processing program
RETI instruction
POP
SR
POP
PC
INTNEST ← INTNEST − 1
End
Figure 3.5.1 Interrupt and Micro DMA Processing Sequence
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3.5.1
General-purpose Interrupt Processing
When the CPU accepts an interrupt, it usually performs the following sequence of
operations. That is also the same as TLCS-900/L and TLCS-900/H.
(1) The CPU reads the interrupt vector from the interrupt controller.
If the same level interrupts occur simultaneously, the interrupt controller generates an
interrupt vector in accordance with the default priority and clears the interrupt
request.
(The default priority is already fixed for each interrupt: The smaller vector value has
the higher priority level.)
(2) The CPU pushes the value of program counter (PC) and status register (SR) onto the
stack area (Indicated by XSP).
(3) The CPU sets the value which is the priority level of the accepted interrupt plus 1 (+1)
to the interrupt mask register <IFF2:0>. However, if the priority level of the accepted
interrupt is 7, the register’s value is set to 7.
(4) The CPU increases the interrupt nesting counter INTNEST by 1 (+1).
(5) The CPU jumps to the address indicated by the data at address “FFFF00H + interrupt
vector” and starts the interrupt processing routine.
The above processing time is 18 states (1.0 μs at 36 MHz) as the best case (16-bit data
bus width and 0 waits).
When the CPU completed the interrupt processing, use the RETI instruction to
return to the main routine. RETI restores the contents of program counter (PC) and
status register (SR) from the stack and decreases the interrupt nesting counter
INTNEST by 1 (−1).
Non-maskable interrupts cannot be disabled by a user program. Maskable
interrupts, however, can be enabled or disabled by a user program. A program can set
the priority level for each interrupt source. (A priority level setting of 0 or 7 will disable
an interrupt request.)
If an interrupt request which has a priority level equal to or greater than the value of
the CPU interrupt mask register <IFF2:0> comes out, the CPU accepts its interrupt.
Then, the CPU interrupt mask register <IFF2:0> is set to the value of the priority level
for the accepted interrupt plus 1 (+1).
Therefore, if an interrupt is generated with a higher level than the current interrupt
during its processing, the CPU accepts the later interrupt and goes to the nesting
status of interrupt processing.
Moreover, if the CPU receives another interrupt request while performing the said
(1) to (5) processing steps of the current interrupt, the latest interrupt request is
sampled immediately after execution of the first instruction of the current interrupt
processing routine. Specifying DI as the start instruction disables maskable interrupt
nesting.
A reset initializes the interrupt mask register <IFF2:0> to 111, disabling all
maskable interrupts.
Table 3.5.1 shows the TMP91C829 interrupt vectors and micro DMA start vectors.
The address FFFF00H to FFFFFFH (256 bytes) is assigned for the interrupt vector
area.
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Table 3.5.1 TMP91C829 Interrupt Vectors and Micro DMA Start Vectors
Default
Priority
Type
Interrupt Source or Source of Micro DMA
Request
Vector Value
Vector
Reference
Address
Micro DMA
Start Vector
1
Reset or “SWI0” instruction
0000H
FFFF00H
−
2
“SWI1” instruction
0004H
FFFF04H
−
3
Illegal instruction or “SWI2” instruction
0008H
FFFF08H
−
“SWI3” instruction
000CH
FFFF0CH
−
5
Non-mask
“SWI4” instruction
0010H
FFFF10H
−
6
able
“SWI5” instruction
0014H
FFFF14H
−
7
“SWI6” instruction
0018H
FFFF18H
−
8
“SWI7” instruction
001CH
FFFF1CH
−
9
NMI : NMI pin input
0020H
FFFF20H
−
10
INTWD: Watchdog timer
0024H
FFFF24H
−
−
Micro DMA
−
−
−
11
INT0: INT0 pin input
0028H
FFFF28H
0AH
12
INT1: INT1 pin input
002CH
FFFF2CH
0BH
13
INT2: INT2 pin input
0030H
FFFF30H
0CH
14
INT3: INT3 pin input
0034H
FFFF34H
0DH
4
15
INT4: INT4 pin input
0038H
FFFF38H
0EH
16
INT5: INT5 pin input
003CH
FFFF3CH
0FH
17
(Reserved)
0040H
FFFF40H
10H
18
(Reserved)
0044H
FFFF44H
11H
19
(Reserved)
0048H
FFFF48F
12H
20
INTTA0: 8-bit timer 0
004CH
FFFF4CH
13H
21
INTTA1: 8-bit timer 1
0050H
FFFF50H
14H
22
INTTA2: 8-bit timer 2
0054H
FFFF54H
15H
23
INTTA3: 8-bit timer 3
0058H
FFFF58H
16H
24
INTTA4: 8-bit timer 4
005CH
FFFF5CH
17H
25
INTTA5: 8-bit timer 5
0060H
FFFF60H
18H
26
(Reserved)
0064H
FFFF64H
19H
27
(Reserved)
0068H
FFFF68H
1AH
28
INTTB00: 16-bit timer 0 (TB0RG0)
006CH
FFFF6CH
1BH
29
30
Maskable
INTTB01: 16-bit timer 0 (TB0RG1)
0070H
FFFF70H
1CH
(Reserved)
0074H
FFFF74H
1DH
31
(Reserved)
0078H
FFFF78H
1EH
32
INTTBOF0: 16-bit timer 0 (Overflow)
007CH
FFFF7CH
1FH
33
(Reserved)
0080H
FFFF80H
20H
34
INTRX0: Serial receive (Channel 0)
0084H
FFFF84H
21H
35
INTTX0: Serial transmission (Channel 0)
0088H
FFFF88H
22H
36
INTRX1: Serial receive (Channel 1)
008CH
FFFF8CH
23H
37
INTTX1: Serial transmission (Channel 1)
0090H
FFFF90H
24H
38
(Reserved)
0094H
FFFF94H
25H
39
(Reserved)
0098H
FFFF98H
26H
40
INTAD: AD conversion end
009CH
FFFF9CH
27H
41
INTTC0: Micro DMA end (Channel 0)
00A0H
FFFFA0H
28H
42
INTTC1: Micro DMA end (Channel 1)
00A4H
FFFFA4H
29H
43
INTTC2: Micro DMA end (Channel 2)
00A8H
FFFFA8H
2AH
44
INTTC3: Micro DMA end (Channel 3)
00ACH
FFFFACH
2BH
−
to
00B0H
FFFFB0H
(Reserved)
to
to
−
to
00FCH
FFFFFCH
−
−
91C829-29
2006-03-15
TMP91C829
3.5.2
Micro DMA Processing
In addition to general-purpose interrupt processing, the TMP91C829 supprots a micro
DMA function. Interrupt requests set by micro DMA perform micro DMA processing at the
highest priority level (Level 6) among maskable interrupts, regardless of the priority level
of the particular interrupt source. The micro DMA has 4 channels and is possible
continuous transmission by specifing the say later burst mode.
Because the micro DMA function has been implemented with the cooperative operation
of CPU, when CPU goes to a standby mode by HALT instruction, the requirement of micro
DMA will be ignored (Pending).
(1) Micro DMA operation
When an interrupt request specified by the micro DMA start vector register is
generated, the micro DMA triggers a micro DMA request to the CPU at interrupt
priority level 6 and starts processing the request in spite of any interrupt source’s level.
The micro DMA is ignored on <IFF2:0> = “7”
The 4 micro DMA channels allow micro DMA processing to be set for up to 4 types of
interrupts at any one time. When micro DMA is accepted, the interrupt request
flip-flop assigned to that channel is cleared.
The data are automatically transferred once (1 or 2 or 4 bytes) from the transfer
source address to the transfer destination address set in the control register, and the
transfer counter is decreased by 1 (−1).
If the decreased result is 0, the micro DMA transfer end interrupt (INTTC0 to
INTTC3) passes from the CPU to the interrupt controller. In addition, the micro DMA
start vector register DMAnV is cleared to 0, the next micro DMA is disabled and micro
DMA processing completes. If the decreased result is other than 0, the micro DMA
processing completes if it isn’t specified the say later burst mode. In this case, the
micro DMA transfer end interrupt (INTTC0 to INTTC3) aren’t generated.
If an interrupt request is triggered for the interrupt source in use during the interval
between the clearing of the micro DMA start vector and the next setting,
general-purpose interrupt processing executes at the interrupt level set. Therefore, if
only using the interrupt for starting the micro DMA (Not using the interrupts as a
general-purpose interrupt: level 1 to 6), first set the interrupts level to 0 (Interrupt
requests disabled).
If using micro DMA and general-purpose interrupts together, first set the level of the
interrupt used to start micro DMA processing lower than all the other interrupt levels
(Note). In this case, the cause of general interrupt is limited to the edge interrupt.
The priority of the micro DMA transfer end interrupt (INTTC0 to INTTC3) is defined
by the interrupt level and the default priority as same as the other maskable interrupt.
Note: If the priority level of micro DMA is set higher than that of other interrupts, CPU operates as follows.
In case INTxxx interrupt is generated first and then INTyyy interrupt is generated between checking
“Interrupt specified by micro DMA start vector” (in the Figure 3.5.1 ) and reading interrupt vector with
setting below. The vector shifts to that of INTyyy at the time.
This is because the priority level of INTyyy is higher than that of INTxxx.
In the interrupt routine, CPU reads the vector of INTyyy because cheking of micro DMA has finished.
And INTyyy is generated regardless of transfer counter of micro DMA.
INTxxx: level 1 without micro DMA
INTyyy: level 6 with micro DMA
91C829-30
2006-03-15
TMP91C829
If a micro DMA request is set for more than one channel at the same time, the
priority is not based on the interrupt priority level but on the channel number. The
smaller channel number has the higher priority (Channel 0 (High) > Channel 3 (Low)).
While the register for setting the transfer source/transfer destination addresses is a
32-bit control register, this register can only effectively output 24-bit addresses.
Accordingly, micro DMA can access 16 Mbytes (The upper eight bits of the 32 bits are
not valid).
Three micro DMA transfer modes are supported: 1-byte transfer, 2-byte (One word)
transfer, and 4-byte transfer. After a transfer in any mode, the transfer source/transfer
destination addresses are increased, decreased, or remain unchanged.
This simplifies the transfer of data from I/O to memory, from memory to I/O. For
details of the transfer modes, see (4) “Detailed description of the transfer mode
register”. As the transfer counter is a 16-bit counter, micro DMA processing can be set
for up to 65536 times per interrupt source. (The micro DMA processing count is
maximized when the transfer counter initial value is set to 0000H.)
Micro DMA processing can be started by the 23 interrupts shown in the micro DMA
start vectors of Figure 3.5.1 and by the micro DMA soft start, making a total of 24
interrupts.
Figure 3.5.2 shows the word transfer micro DMA cycle in transfer destination
address INC mode (except for counter mode, the same as for other modes).
(The conditions for this cycle are based on an external 16-bit bus, 0 waits, transfer
source/transfer destination addresses both even numbered values.)
1 state
DM1
(Note 1)
DM2
DM3
DM4
DM5
(Note 2)
DM6
DM7
DM8
X1
A0 to A23
Transfer source address
Transfer destination
address
RD
WR / HWR
D0 to D15
Input
Output
Figure 3.5.2 Timing for Micro DMA Cycle
States 1 to 3: Instruction fetch cycle (Gets next address code).
If 3 bytes and more instruction codes are inserted in the instruction queue
buffer, this cycle becomes a dummy cycle.
States 4 to 5: Micro DMA read cycle.
State 6:
Dummy cycle (The address bus remains unchanged from state 5.)
States 7 to 8: Micro DMA write cycle.
Note 1: If the source address area is an 8-bit bus, it is increased by 2 states.
If the source address area is a 16-bit bus and the address starts from an odd number, it is
increased by 2 states.
Note 2: If the destination address area is an 8-bit bus, it is increased by 2 states.
If the destination address area is a 16-bit bus and the address starts from an odd number,
it is increased by 2 states.
91C829-31
2006-03-15
TMP91C829
(2) Soft start function
In addition to starting the micro DMA function by interrupts, TMP91C829 includes
a micro DMA software start function that starts micro DMA on the generation of the
write cycle to the DMAR register.
Writing 1 to each bit of DMAR register causes micro DMA once (If write 0 to each
bitm micro DMA doesn’t operate). At the end of transfer, the corresponding bit of the
DMAR register is automatically cleared to 0.
Only one-channel can be set for micro DMA at once. (Do not write 1 to plural bits.)
When writing again 1 to the DMAR register, check whether the bit is 0 before
writing 1. If read 1, micro DMA transfer isn’t started yet.
When a burst is specified by DMAB register, data is continuously transferred until
the value in the micro DMA transfer counter is 0 after start up of the micro DMA
transfer counter doesn’t change. Don’t use Read-modify –write instruction to avoid
writing to other bits by mistake.
Symbol
DMAR
Name
Address
DMA
89H
request
(Prohibit
register
RMW)
7
6
5
4
3
2
DMAR3
DMAR2
1
0
DMAR1
DMAR0
R/W
0
0
0
0
DMA request
(3) Transfer control registers
The transfer source address and the transfer destination address are set in the
following registers. Data setting for these registers is done by an “LDC cr,r”
instruction.
Channel 0
DMAS0
DMA source address register 0: Only use LSB 24 bits.
DMAD0
DMA destination address register 0: Only use LSB 24 bits.
DMAC0
DMA counter register 0: 1 to 65536.
DMAM0
DMA mode register 0.
Channel 3
DMAS3
DMA source address register 3.
DMAD3
DMA destination address register 3.
DMAC3
DMA counter register 3.
DMAM3
DMA mode register 3.
8 bits
16 bits
32 bits
91C829-32
2006-03-15
TMP91C829
(4) Detailed description of the transfer mode register
8 bits
DMAM0 to
0
DMAM3
0
0
Mode
Number of
Transfer Bytes
000
(Fixed)
000
001
010
011
100
101
Note: When setting a value in this register, write 0 to the upper 3
bits.
Mode Description
Transfer destination address INC mode
.............. I/O to memory
(DMADn+) ← (DMASn)
DMACn ← DMACn − 1
If DMACn = 0, then INTTCn is generated.
00
Byte transfer
01
Word transfer
10
4-byte transfer
00
Byte transfer
01
Word transfer
10
4-byte transfer
00
Byte transfer
01
Word transfer
10
4-byte transfer
00
Byte transfer
01
Word transfer
10
4-byte transfer
00
Byte transfer
01
Word transfer
10
4-byte transfer
00
Counter mode
............. For counting number of times interrupt is generated.
DMASn ← DMASn + 1
DMACn ← DMACn − 1
If DMACn = 0, then INTTCn is generated.
Transfer destination address DEC mode
.............. I/O to memory
(DMADn−) ← (DMASn)
DMACn ← DMACn − 1
If DMACn = 0, then INTTCn is generated.
Transfer source address INC mode
.............. Memory to I/O
(DMADn) ← (DMASn+)
DMACn ← DMACn − 1
If DMACn = 0, then INTTCn is generated.
Transfer source address DEC mode
.............. Memory to I/O
(DMADn) ← (DMASn−)
DMACn ← DMACn − 1
If DMACn = 0, then INTTCn is generated.
Number of
Minimum
Execution States Execution Time
at fc = 36 MHz
8 states
444 ns
12 states
667 ns
8 states
444 ns
12 states
667 ns
8 states
444ns
12 states
667 ns
8 states
444ns
12 states
667 ns
8 states
444 ns
12 states
667 ns
5 states
278 ns
Fixed address mode
.............. I/O to I/O
(DMADn) ← (DMASn−)
DMACn ← DMACn − 1
If DMACn = 0, then INTTCn is generated.
Note 1: “n” is the corresponding micro DMA channels 0 to 3.
DMADn+/DMASn+: Post-increment (Increment register value after transfer)
DMADn−/DMASn−: Post-decrement (Decrement register value after transfer)
The I/Os in the table mean fixed address and the memory means increment (INC) or decrement
(DEC) addresses.
Note 2: Execution time is under the condition of:
16-bit bus width (both translation and destination address area)/0 waits/
fc = 36 MHz/selected high-frequency mode (fc × 1)
Note 3: Do not use an undefined code for the transfer mode register except for the defined codes listed in
the above table.
91C829-33
2006-03-15
TMP91C829
3.5.3
Interrupt Controller Operation
The block diagram in Figure 3.5.3 shows the interrupt circuits. The left-hand side of the
diagram shows the interrupt controller circuit. The right-hand side shows the CPU
interrupt request signal circuit and the halt release circuit.
For each of the 26 interrupt channels there is an interrupt request flag (Consisting of a
flip-flop), an interrupt priority setting register and a micro DMA start vector register. The
interrupt request flag latches interrupt requests from the peripherals. The flag is cleared to
zero in the following cases:
•
When reset occurs
•
When the CPU reads the channel vector after accepted its interrupt
•
When executing an instruction that clears the interrupt (Write micro DMA start vector
to INTCLR register)
•
When the CPU receives a micro DMA request (when micro DMA is set)
•
When the micro DMA burst transfer is terminated
An interrupt priority can be set independently for each interrupt source by writing the
priority to the interrupt priority setting register (e.g., INTE0AD or INTE12). 6 interrupt
priorities levels (1 to 6) are provided. Setting an interrupt source’s priority level to 0 (or 7)
disables interrupt requests from that source. The priority of non-maskable interrupts (NMI
pin interrupts and watchdog timer interrupts) are fixed at 7. If interrupt request with the
same level are generated at the same time, the default priority (The interrupt with the
lowest priority or, in other words, the interrupt with the lowest vector value) is used to
determine which interrupt request is accepted first.
The 3rd and 7th bits of the interrupt priority setting register indicate the state of the
interrupt request flag and thus whether an interrupt request for a given channel has
occurred.
The interrupt controller sends the interrupt request with the highest priority among the
simulateous interrupts and its vector address to the CPU. The CPU compares the priority
value <IFF2:0> in the status register by the interrupt request signal with the priority value
set; if the latter is higher, the interrupt is accepted. Then the CPU sets a value higher than
the priority value by 1 (+1) in the CPU SR <IFF2:0>. Interrupt request where the priority
value equals or is higher than the set value are accepted simultaneously during the
previous interrupt routine.
When interrupt processing is completed (after execution of the RETI instruction), the
CPU restores the priority value saved in the stack before the interrupt was generated to
the CPU SR<IFF2:0>.
The interrupt controller also has registers (4 channels) used to store the micro DMA start
vector. Writing the start vector of the interrupt source for the micro DMA processing (See
Table 3.5.1), enables the corresponding interrupt to be processed by micro DMA processing.
The values must be set in the micro DMA parameter register (e.g., DMAS and DMAD) prior
to the micro DMA processing.
91C829-34
2006-03-15
Micro
DMA
counter 0
interrupt
91C829-35
INTAD
INTTC0
INTTC1
INTTC2
INTTC3
INT1
INT2
INT3
INT4
INT5
INTTA0
INT0
INTWD
NMI
S
R
Q
INTTC
V = 9CH
V = A0H
V = A4H
V = A8H
V = ACH
DMA0V
DMA1V
DMA2V
DMA3V
S
6 Selector
34
6
V = 28H
V = 2CH
V = 30H
V = 34H
V = 38H
V = 3CH
V = 4CH
Soft start
Interrupt vector read
Micro DMA acknowledge
D
Q
CLR
RESET
D5
D4
D3
D2
D1
D0
Decoder
Y1
Y2
Y3
Y4
Y5
Y6
A
B
C
V = 20H
V = 24H
Interrupt
request F/F
Dn + 3
S Q
R
Interrupt request flag
CLR
Micro DMA start vector setting register
Reset
Dn + 2
Priority setting register
Dn
Dn + 1
D
Q
RESET
interrupt
vector read
Interrupt request F/F
Interrupt controller
4
1
7
0
1
2
3
B
A
D2
D3
D4
D5
D6
D7
D0
D1
3 INTRQ2 to 0
2
Interrupt vector
read
Interrupt
vector
generator
4 input OR
26
1
2 Highest A
3 priority B
interrupt C
4
level select
5
6
7
Micro DMA channel
priority encoder
6
1
Interrupt
request signal
Priority encoder to CPU
Interrupt
level detect
2
if IFF = 7 then 0
INT0 to INT4
NMI
RESET
Micro DMA channel
specification
Micro DMA request
Halt release
During
IDLE1
During
STOP
Interrupt request
signal
EI1 to 7
DI
RESET
if INTRQ2 to 0 ≥ IFF
2 to 0 then 1.
3
3
IFF2:0
Interrupt
mask F/F
CPU
TMP91C829
Figure 3.5.3 Block Diagram of Interrupt Controller
2006-03-15
TMP91C829
(1) Interrupt priority setting registers
Symbol
Name
INTE0AD
INTE0
&
INTAD
enable
INTE12
INTE34
INT1
&
INT2
enable
INT3
&
INT4
enable
Address
7
6
IADC
IADM2
5
4
3
2
IADM1
IADM0
I0C
I0M2
INTAD
90H
R
0
I2C
I2M2
R
R
0
0
0
I2M1
I2M0
I1C
I1M2
0
I4C
I4M2
R
R
0
0
0
0
0
I4M1
I4M0
I3C
I3M2
0
I1M1
I1M0
0
0
I3M1
I3M0
INT3
R/W
0
0
R/W
INT4
92H
I0M0
INT1
R/W
0
I0M1
R/W
0
INT2
91H
0
INT0
R/W
0
1
R
0
0
R/W
0
0
0
0
I5M1
I5M0
INT5
INTE5
INT5
enable
INTETA01
INTTA0
&
INTTA1
enable
INTETA23
INTTA2
&
INTTA3
enable
INTETA45
INTTA4
&
INTTA5
enable
I5C
93H
I5M2
R
R/W
0
0
ITA0C
ITA0M2
INTTA1 (TMRA1)
95H
ITA1C
ITA1M2
0
ITA1M0
R/W
0
R
0
0
ITA3C
ITA3M2
0
0
ITA3M0
0
ITA2C
R/W
0
ITA5C
ITA5M2
0
0
Interrupt request flag
ITA2M2
ITA2M1
ITA2M0
R/W
0
ITA5M0
0
ITA4C
R/W
0
0
0
0
INTTA4 (TMRA4)
ITA5M1
R
0
R
0
INTTA5 (TMRA5)
97H
ITA0M0
INTTA2 (TMRA2)
ITA3M1
R
ITA0M1
R/W
INTTA3 (TMRA3)
96H
0
INTTA0 (TMRA0)
ITA1M1
R
0
ITA4M2
R
0
0
0
ITA4M1
ITA4M0
R/W
0
0
lxxM2
lxxM1
lxxM0
0
0
0
Disables interrupt requests
0
0
1
Sets interrupt priority level to 1
0
1
0
Sets interrupt priority level to 2
0
1
1
Sets interrupt priority level to 3
1
0
0
Sets interrupt priority level to 4
1
0
1
Sets interrupt priority level to 5
1
1
0
Sets interrupt priority level to 6
1
1
1
Disables interrupt requests
91C829-36
0
Function (Write)
2006-03-15
TMP91C829
Symbol
Name
INTETB0
Interrupt
enable
TMRB0
Address
7
6
5
4
3
2
ITB01M2 ITB01M1 ITB01M0
ITB00C
ITB00M2
R/W
R
INTTB01 (TMRB0)
99H
ITB01C
R
0
Interrupt
enable
INTETB0V
TMRB0V
(overflow)
INTES0
Interrupt
enable
serial 0
INTES1
Interrupt
enable
serial 1
INTETC01
INTTC0
&
INTTC1
enable
0
INTETC23
0
0
ITF0M2
0
ITX1C
ITX1M2
0
R
ITX0M0
IRX0C
IRX0M2
R
0
0
0
ITX1M1
ITX1M0
IRX1C
IRX1M2
ITC1C
R/W
R
0
ITC1M2
0
0
ITC3C
ITC1M0
ITC0C
ITC0M2
R
0
ITC3M2
0
0
Interrupt request flag
IRX1M1
IRX1M0
0
0
ITC0M1
ITC0M0
R/W
0
ITC3M0
0
ITC2C
R/W
0
0
0
0
ITC2M1
ITC2M0
INTTC2
ITC3M1
R
0
0
INTTC3
A1H
IRX0M0
R/W
0
R/W
0
IRX0M1
INTTC0
ITC1M1
R
0
INTRX1
INTTC1
A0H
0
R/W
0
0
ITF0M0
INTRX0
ITX0M1
INTTX1
9DH
ITF0M1
R/W
0
R/W
0
0
INTTBOF0 (overflow)
INTTX0
R
ITB00M0
0
R
ITX0M2
ITB00M1
R/W
0
9BH
0
INTTC2
&
INTTC3
enable
0
ITF0C
ITX0C
0
INTTB00 (TMRB0)
(Reserved)
9CH
1
ITC2M2
R
0
0
0
R/W
0
0
lxxM2
lxxM1
lxxM0
0
0
0
Disables interrupt requests
0
0
1
Sets interrupt priority level to 1
0
1
0
Sets interrupt priority level to 2
0
1
1
Sets interrupt priority level to 3
1
0
0
Sets interrupt priority level to 4
1
0
1
Sets interrupt priority level to 5
1
1
0
Sets interrupt priority level to 6
1
1
1
Disables interrupt requests
91C829-37
0
Function (Write)
2006-03-15
TMP91C829
(2) External interrupt control
Symbol Name Address
7
6
5
4
−
I2EDGE
I2LE
I1DGE
3
2
1
0
I1LE
I0EDGE
I0LE
NMIREE
0
0
0
W
IIMC0
0
Interrupt
8CH
Write
“0”.
input mode (Prohibit
control 0
RMW)
0
0
0
0
INT2EDGE INT2EDGE INT1EDGE INT1EDGE INT0EDGE INT0
0: Rising
0: Edge
0: Rising
0: Edge
0: Rising
0: Edge
1: Falling
1: Level
1: Falling
1: Level
1: Falling
1: Level
1: Operates
even on
rising +
falling edge
of NMI
INT2 level enable
0
Edge detect INT
1
H Level INT
INT1 level enable
0
Edge detect INT
1
H Level INT
INT0 level enable
0
Edge detect INT
1
H Level INT
NMI rising edge enable
0
INT request generation at falling edge
1
INT request generation at rising/falling edge
Symbol
IIMC1
Name Address
Interrupt
input
mode
control1
8DH
(Prohibit
RMW)
7
6
5
4
3
2
1
I5EDGE
I5LE
I4EDGE
I4LE
I3EDGE
I3LE
0
0
0
0
0
0
W
INT5EDGE INT5
0: Rising
0: Edge
1: Falling
1: Level
0
INT4EDGE INT4
0: Rising
0: Edge
1: Falling
1: Level
INT3EDGE INT3
0: Rising
0: Edge
1: Falling
1: Level
INT5 level enable
0
Edge detect INT
1
H Level INT
INT4 level enable
0
Edge detect INT
1
H Level INT
INT3 level enable
0
Edge detect INT
1
H Level INT
When switching IIMC0 and IIMC1 registers, first every FC registers in port which built-in INT function set to 0.
91C829-38
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TMP91C829
Setting functions on external interrupt pins
Interrupt Pin
Mode
Setting Method
Falling edge
NMI
<NMIREE> = 1
Both falling and rising edges
Rising edge
INT0
INT1
INT2
INT3
INT4
INT5
<NMIREE> = 0
<I0LE> = 0, <I0EDGE> = 0
Falling edge
<I0LE> = 0, <I0EDGE> = 1
High level
<I0LE> = 1, <I0EDGE> = 0
Low level
<I0LE> = 1, <I0EDGE> = 1
Rising edge
<I1LE> = 0, <I1EDGE> = 0
Falling edge
<I1LE> = 0, <I1EDGE> = 1
High level
<I1LE> = 1, <I1EDGE> = 0
Low level
<I1LE> = 1, <I1EDGE> = 1
Rising edge
<I2LE> = 0, <I2EDGE> = 0
Falling edge
<I2LE> = 0, <I2EDGE> = 1
High level
<I2LE> = 1, <I2EDGE> = 0
Low level
<I2LE> = 1, <I2EDGE> = 1
Rising edge
<I3LE> = 0, <I3EDGE> = 0
Falling edge
<I3LE> = 0, <I3EDGE> = 1
High level
<I3LE> = 1, <I3EDGE> = 0
Low level
<I3LE> = 1, <I3EDGE> = 1
Rising edge
<I4LE> = 0, <I4EDGE> = 0
Falling edge
<I4LE> = 0, <I4EDGE> = 1
High level
<I4LE> = 1, <I4EDGE> = 0
Low level
<I4LE> = 1, <I4EDGE> = 1
Rising edge
<I5LE> = 0, <I5EDGE> = 0
Falling edge
<I5LE> = 0, <I5EDGE> = 1
High level
<I5LE> = 1, <I5EDGE> = 0
Low level
<I5LE> = 1, <I5EDGE> = 1
(3) Interrupt request flag clear register
The interrupt request flag is cleared by writing the appropriate micro DMA start
vector, as given in Table 3.5.1, to the register INTCLR.
For example, to clear the interrupt flag INT0, perform the following register
operation after execution of the DI instruction.
INTCLR ← 0AH
Symbol Name Address
Interrupt
INTCLR clear
control
88H
(Prohibit
RMW)
7
Clears interrupt request flag INT0.
6
5
4
3
CLRV5
CLRV4
CLRV3
2
1
0
CLRV2
CLRV1
CLRV0
0
0
0
W
0
0
0
Interrupt vector
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TMP91C829
(4) Micro DMA start vector registers
These registers assign micro DMA processing to sets which source corresponds to
DMA. The interrupt source whose micro DMA start vector value matches the vector
set in one of these registers is designated as the micro DMA start source.
When the micro DMA transfer counter value reaches zero, the micro DMA transfer
end interrupt corresponding to the channel is sent to the interrupt controller, the
micro DMA start vector register is cleared, and the micro DMA start source for the
channel is cleared. Therefore, in order for micro DMA processing to continue, the
micro DMA start vector register must be set again during processing of the micro
DMA transfer end interrupt.
If the same vector is set in the micro DMA start vector registers of more than one
channel, the lowest numbered channel takes priority.
Accordingly, if the same vector is set in the micro DMA start vector registers for two
different channels, the interrupt generated on the lower-numbered channel is
executed until micro DMA transfer is complete. If the micro DMA start vector for this
channel has not been set in the channel’s micro DMA start vector register again, micro
DMA transfer for the higher-numbered channel will be commenced. (This process is
known as micro DMA chaining.)
Symbol Name
DMA0V
Address
DMA0
start
vector
7
6
5
4
3
DMA0V5
DMA0V4
DMA0V3
2
1
0
DMA0V2
DMA0V1
DMA0V0
0
0
DMA1V1
DMA1V0
0
0
DMA2V1
DMA2V0
0
0
DMA3V1
DMA3V0
0
0
R/W
80H
0
0
0
0
DMA1V5
DMA1V4
DMA1V3
DMA0 start vector
DMA1V
DMA1
start
vector
DMA1V2
R/W
81H
0
0
0
0
DMA1 start vector
DMA2V
DMA2V5
DMA2
start
vector
DMA2V4
DMA2V3
DMA2V2
R/W
82H
0
0
0
0
DMA2 start vector
DMA3V
DMA3
start
vector
DMA3V5
DMA3V4
DMA3V3
0
0
0
DMA3V2
R/W
83H
0
DMA3 start vector
(5) Specification of a micro DMA burst
Specifying the micro DMA burst function causes micro DMA transfer, once started,
to continue until the value in the transfer counter register reaches zero. Setting any of
the bits in the register DMAB which correspond to a micro DMA channel (as shown
below) to 1 specifies that any micro DMA transfer on that channel will be a burst
transfer.
Symbol Name Address
DMAR
DMAB
DMA
software
request
register
DMA
burst
register
7
6
5
89H
(Prohibit
RMW)
4
3
2
1
0
DMAR3
DMAR2
DMAR1
DMAR0
R/W
R/W
R/W
R/W
0
0
0
0
1: DMA software request
DMAB3
DMAB2
DMAB1
DMAB0
0
0
R/W
8AH
0
0
1:DMA burst request
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TMP91C829
(6) Notes
The instruction execution unit and the bus interface unit in this CPU operate
independently. Therefore if, immediately before an interrupt is generated, the CPU
fetches an instruction which clears the corresponding interrupt request flag (Note), the
CPU may execute this instruction in between accepting the interrupt and reading the
interrupt vector. In this case, the CPU will read the default vector 0008H and jump to
interrupt vector address FFFF08H.
To avoid the avobe problem, place instructions that clear interrupt request flags
after a DI instruction. And in the case of setting an interrupt enable again by EI
instruction after the execution of clearing instruction, execute EI instruction after
clearing and more than 1 instructions (ex. “NOP” * 1 time). If placed EI instruction
without waiting NOP instruction after execution of clearing instruction, interrupt will
be enable before request flag is cleared.
In the case of changing the value of the interrupt mask register <IFF2:0> by
execution of POP SR instruction, disable an interrupt by DI instruction before
execution of POP SR instruction.
In addition, take care as the following 2 circuits are exceptional and demand special
attention.
INT0 to INT5 level mode
In level mode INT0 is not an edge-triggered interrupt. Hence, in level
mode the interrupt request flip-flop for INT0 does not function. The
peripheral interrupt request passes through the S input of the flip-flop
and becomes the Q output. If the interrupt input mode is changed from
edge mode to level mode, the interrupt request flag is cleared
automatically.
(For example: In case of INT0)
If the CPU enters the interrupt response sequence as a result of INT0
going from 0 to 1, INT0 must then be held at 1 until the interrupt
response sequence has been completed. If INT0 is set to level mode
so as to release a halt state, INT0 must be held at 1 from the time
INT0 changes from 0 to 1 until the halt state is released. (Hence, it is
necessary to ensure that input noise is not interpreted as a 0, causing
INT0 to revert to 0 before the halt state has been released.)
When the mode changes from level mode to edge mode, interrupt
request flags which were set in level mode will not be cleared.
Interrupt request flags must be cleared using the following sequence.
DI
LD (IIMC0), 00H; Switches interrupt input mode from level
mode to edge mode.
LD (INTCLR), 0AH; Clears interrupt request flag.
NOP
; Wait EI instruction
EI
INTRX
The interrupt request flip-flop can only be cleared by a reset or by
reading the Serial Channel Receive Buffer. It cannot be cleared by
writing INTCLR register.
Note: The following instructions or pin input state changes are equivalent to instructions which
clear the interrupt request flag.
INT0 to INT5: Instructions which switch to level mode after an interrupt request has been
generated in edge mode.
The pin input changes from high to low after an interrupt request has been
generated in level mode. (H → L)
INTRX: Instructions which read the receive buffer.
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TMP91C829
3.6
Port Functions
The TMP91C829 features 53 bit settings which relate to the various I/O ports.
As well as general-purpose I/O port functionality, the port pins also have I/O functions which
relate to the built-in CPU and internal I/Os. Table 3.6.1 lists the functions of each port pin.
Table 3.6.2 lists the I/O registers and their specifications.
Table 3.6.1 Port Functions
Port Name
Pin Name
Number of
Pins
(R: ↑ = with programmable pull-up resistor)
Direction
R
Direction
Setting Unit
Pin Name for Internal
Function
Port 1
P10 to P17
8
I/O
−
Bit
D8 to D15
Port 2
P20 to P27
8
Output
−
Bit
A16 to A23
Port 5
P53
P54
1
1
I/O
I/O
Bit
Bit
BUSRQ
P55
1
I/O
Bit
WAIT
P56
1
I/O
Bit
INT0
P60
1
Output
−
Bit
CS0
P61
1
Output
−
Bit
CS1
P62
1
Output
−
Bit
CS2
P63
1
Output
−
Bit
CS3
P70
P71
1
1
I/O
I/O
−
−
Bit
Bit
TA0IN/INT1
TA1OUT
P72
1
I/O
−
Bit
TA3OUT/INT2
P73
1
I/O
−
Bit
TA4IN/INT3
P74
1
I/O
−
Bit
TA5OUT
P75
1
I/O
−
Bit
INT4
Port 6
Port 7
Port 8
Port 9
Port A
Port Z
BUSAK
P80
1
I/O
Bit
TXD0
P81
1
I/O
Bit
P82
1
I/O
Bit
RXD0
SCLK0/ CTS0
P83
1
I/O
Bit
STS0
P84
1
I/O
Bit
TXD1
P85
1
I/O
Bit
P86
1
I/O
Bit
RXD1
SCLK1/ CTS1
P87
1
I/O
Bit
STS1
P90
P93
1
1
I/O
I/O
−
−
Bit
Bit
INT5
TB0IN0
P94
1
I/O
−
Bit
TB0IN1
P95
1
I/O
−
Bit
TB0OUT0
P96
1
I/O
−
Bit
TB0OUT1
PA3
1
Input
−
(Fixed)
ADTRG
PA0 to PA7
7
Input
−
(Fixed)
AN0 to AN7
PZ2
PZ3
1
1
I/O
I/O
91C829-42
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Bit
HWR
2006-03-15
TMP91C829
Table 3.6.2 I/O Registers and Their Specifications (1/2)
Port
Port 1
Port 2
Port Z
Name
P10 to P17
P20 to P27
PZ2
PZ3
Port 5
P53
P54
P55
P56
Port 6
Port 7
I/O Registers
Specification
Input port
Pn
PnCR
PnFC
X
0
0
Output port
X
1
0
D8 to D15 bus
X
1
1
Output port
X
1
0
A16 to A23 output
X
1
1
Input port (without PU)
0
0
0
Input port (with PU)
1
0
0
Output port
X
1
0
HWR output
X
1
1
Input port (without PU)
0
0
Input port (with PU)
1
0
Output port
X
1
None
Input port (without PU)
0
0
0
Input port (with PU)
1
0
0
Output port
BUSRQ input (without PU)
X
1
0
0
0
1
BUSRQ input (with PU)
1
0
1
Input port (without PU)
0
0
0
Input port (with PU)
1
0
0
Output port
X
1
0
BUSAK output
X
1
1
Input port/WAIT input (without PU)
0
0
None
Input port/WAIT input (with PU)
1
0
Output port
X
1
Input port/INT0 input (without PU)
0
0
1
1
Input port/INT0 input (with PU)
1
0
Output port
X
1
X
P60
Output port
CS0 output
X
P61
CS1 output
X
P62
CS2 output
X
P63
CS3 output
X
P70 to P75
Input port
X
0
Output port
X
1
0
TA0IN input
X
0
None
INT1 input
X
0
1
P60 to P63
P70
0
0
1
None
1
1
1
0
P71
TA1OUT output
X
1
1
P72
TA3OUT output
X
1
1
P73
INT2 input
X
0
1
TA4IN input
X
0
None
INT3 input
X
0
1
P74
TA5OUT output
X
1
1
P75
INT4 input
X
0
1
X: Don’t care
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Table 3.6.3 I/O Registers and Their Specifications (2/2)
Port
Port 8
Name
P80
P81
P82
P83
P84
P85
P86
P87
Port 9
Port A
P90
Specification
I/O Registers
Pn
PnCR
PnFC
Input port (without PU)
0
0
0
Input port (with PU)
1
0
0
Output port
X
1
0
TXD0 output
X
1
1
Input port/RXD0 input (without PU)
0
0
Input port/RXD0 input (with PU)
1
0
Output port
X
1
Input port/SCLK0/CTS0 input (without PU)
0
0
0
Input port/SCLK0/CTS0 input (with PU)
1
0
0
Output port
X
1
0
SCLK0 output
X
1
1
None
Input port (without PU)
0
0
0
Input port (with PU)
1
0
0
Output port
STS0 output
X
1
0
X
1
1
Input port (without PU)
0
0
0
Input port (with PU)
1
0
0
Output port
X
1
0
TXD1 output
X
1
1
Input port/RXD1 input (without PU)
0
0
None
Input port/RXD1 input (with PU)
1
0
Output port
X
1
Input port/SCLK1/CTS1 input (without PU)
0
0
0
Input port/SCLK1/CTS1 input (with PU)
1
0
0
Output port
X
1
0
SCLK1 output
X
1
1
Input port (without PU)
0
0
0
Input port (with PU)
1
0
0
Output port
STS1 output
X
1
0
X
1
1
Input port
X
0
0
Output port
X
1
0
1
INT5 input
X
0
P93 to P96
Input port
X
0
Output port
X
1
P93
TB0IN0 input
X
0
P94
TB0IN1 input
X
0
P95
TB0OUT0 output
X
1
1
P96
TB0OUT1 output
X
1
1
PA3
Input port
ADTRG input
X
X
PA0 to PA7
Input port
X
AN0 to AN7
X
None
None
X: Don’t care
Note 1: When PA1 to PA4 are used as AD converter input channels, a 3-bit field in the AD mode control
register ADMOD1<ADCH2:0> is used to select the channel.
Note 2: When PA0 is used as the ADTRG input, ADMOD1<ADTRGE> is used to enable external trigger
input.
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After a reset the port pins listed below function as general-purpose I/O port pins.
A reset sets I/O pins which can be programmed for either input or output to be input port
pins.
Setting the port pins for internal function use must be done in software.
Note about bus release and programmable pull-up I/O port pins
When the bus is released (e.g., when BUSAK = 0), the output buffers for D0 to D15, A0 to A23,
and the control signals ( RD , WR , HWR and CS0 to CS3 ) are off and are set to
high-impedance.
However, the output of built-in programmable pull-up resistors are kept before the bus is
released. These programmable pull-up resistors can be selected on/off by programmable when
they are used as the input ports.
When they are used as output ports, they cannot be turned on/off in software.
Table 3.6.4 shows the pin states after the bus has been released.
Table 3.6.4 Pin States (after bus release)
Pin State (after bus release)
Pin Names
Used as Port
Used for Function
P10 to P17
Unchanged
(D8 to D15)
(e.g., not set to high-impedance (High-Z))
P20 to P27
Unchanged
First all bits are set high, then they are set to
(A16 to 23)
(e.g., not set to high-impedance (High-Z))
high-impedance (High-Z).
RD
WR
High-impedance (High-Z)
↑
↑
PZ2 ( HWR )
The output buffer is set to off.
↑
The programmable pull-up resistor is set to on
irrespective of the output latch.
P60 ( CS0 )
P61 ( CS1 )
P62 ( CS2 )
↑
↑
P63 ( CS3 )
91C829-45
2006-03-15
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Figure 3.6.1 shows an example external interface circuit when the bus release function is
used.
When the bus is released, neither the internal memory nor the internal I/O can be accessed.
However, the internal I/O continues to operate. As a result, the watchdog timer also continues
to run. Therefore, the bus release time must be taken into account and care must be taken when
setting the detection time for the WDT.
RD
WR
PZ2 ( HWR )
System control bus
P60 ( CS0 )
P61 ( CS1 )
P62 ( CS2 )
P63 ( CS3 )
P20 (A16)
to
P27 (A23)
Address bus (A23 to A16)
Figure 3.6.1 Interface Circuit Example (Using bus release function)
The above circuit is necessary to set the signal level when the bus is released.
A reset sets ( RD ) and ( WR ), P60 ( CS0 ), P61 ( CS1 ), P62 ( CS2 ), P63 ( CS3 ) to output, and PZ2
( HWR ) and P54 ( BUSAK ) to input with pull-up resistor.
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2006-03-15
TMP91C829
3.6.1
Port 1 (P10 to P17)
Port 1 is an 8-bit general-purpose I/O port. Each bit can be set individually for input or
output using the control register P1CR. Resetting, the control register P1CR to 0 and sets
port 1 to input mode.
In addition to functioning as a general-purpose I/O port, port 1 can also function as an
address data bus (D8 to D15).
In case of AM1 = 0, and AM = 1 (outside 16-bit data bus), port 1 always functions as the
data bus (D8 to D15) irrespective of the setting in P1CR control register.
Reset
Direction control
(on bit basis)
P1CR write
Internal data bus
Output latch
Port 1
P10 to P17
(D8 to D15)
Output buffer
P1 write
P1 Read
Figure 3.6.2 Port 1
Port 1 Register
P1
Bit symbol
(0001H) Read/Write
7
6
5
4
3
2
1
0
P17
P16
P15
P14
P13
P12
P11
P10
R/W
After reset
Data from external port (Output latch register is cleared to 0.)
Port 1 Control Register
P1CR
Bit symbol
(0004H) Read/Write
After reset
(Note)
7
6
5
4
P17C
P16C
P15C
P14C
3
2
1
0
P13C
P12C
P11C
P10C
0/1
0/1
0/1
0/1
W
0/1
0/1
0/1
Function
0/1
0: Input
1: Output
Note1: Read-modify-write is prohibited for P1CR.
Note2: It is set to “Port” or “Data bus” by AM pins state.
Port 1 I/O setting
0
Input
1
Output
Figure 3.6.3 Register for Port 1
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2006-03-15
TMP91C829
3.6.2
Port 2 (P20 to P27)
Port 2 is an 8-bit output port. In addition to functioning as a output port, port 2 can also
function as an address bus (A16 to A23).
Each bit can be set individually for address bus using the function register P2FC.
Resetting sets all bits of the function register P2FC to 1 and sets port 2 to address bus.
Reset
S
Function control
P2FC write
S
A
Output
selector
Internal data bus
(on bits basis)
latch
B
P2 write
Port 2
P20 to P27
(A16 to A23)
Output buffer
P2 read
Internal A16 to A23
Figure 3.6.4 Port 2
Port 2 Register
P2
Bit symbol
(0006H) Read/Write
After reset
7
6
5
4
P27
P26
P25
P24
3
2
1
0
P23
P22
P21
P20
1
1
1
1
R/W
1
1
1
1
Port 2 Function Register
Bit symbol
P2FC
(0009H) Read/Write
After reset
7
6
5
4
3
2
1
0
P27F
P26F
P25F
P24F
P23F
P22F
P21F
P20F
1
1
1
1
1
1
1
1
W
Function
0: Port
1: Address bus (A23 to A16)
Note: Read-modify-write is prohibited for P2FC.
Figure 3.6.5 Register for Port 2
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2006-03-15
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Port 5 (P53 to P56)
Port 5 is an 4-bit general-purpose I/O port. I/O is set using control register P5CR and
P5FC. Resetting resets all bits of the output latch P5 to 1, the control register P5CR and
the function register P5FC to 0 and sets P52 to P56 to input mode with pull-up register.
In addition to functioning as a general-purpose I/O port, port 5 also functions as I/O for
the CPU’s control/status signal.
Reset
Direction control
(on bit basis)
P5CR write
Function control
Internal data bus
3.6.3
(on bit basis)
P5FC write
P-ch (Programmable pull up)
S
Output
latch
P53 ( BUSRQ )
P5 write
Internal BUSRQ
P5 read
Figure 3.6.6 Port 53
91C829-49
2006-03-15
TMP91C829
Reset
Direction control
(on bit basis)
P5CR write
(on bit basis)
P5FC write
P-ch (Programmable pull up)
S
S
Output
latch
A
B
Selector
Internal data bus
Function control
P54( BUSAK )
Output buffer
P5 write
BUSAK
P5 read
Figure 3.6.7 Port 54
Reset
Direction control
(on bit basis)
P-ch (Programmable pull up)
Internal data bus
P5CR write
S
Output
latch
P55 ( WAIT )
Output buffer
P5 write
P5 read
Internal WAIT
Figure 3.6.8 Port 55
91C829-50
2006-03-15
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Reset
Direction control
(on bit basis)
Internal data bus
P5CR write
Function control
(on bit basis)
P5FC write
P-ch (Programmable pull up)
S
Output latch
P56 (INT0)
P5 write
Output buffer
S
B
selector
P5 write
INT0
A
Level or edge
and
Rising edge or falling edge
IIMC0<I0LE, I0EDGE>
Figure 3.6.9 Port 56
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2006-03-15
TMP91C829
Port 5 Register
7
P5
Bit symbol
(000DH) Read/Write
6
5
P56
P55
4
3
P54
P53
2
1
0
2
1
0
1
0
R/W
After reset
Data from external port
(Output latch register is set to 1.)
Function
0(Output latch register): Pull-up resistor OFF
1(Output latch register): Pull-up resistor ON
Port 5 Control Register
7
P5CR
Bit symbol
(0010H) Read/Write
6
5
P56C
P55C
4
3
P54C
P53C
0
0
W
After reset
0
0
Function
0: Input
1: Output
I/O setting
0
Input
1
Output
Port 5 Function Register
7
P5FC
Bit symbol
(0011H) Read/Write
After reset
Function
6
5
P56F
4
3
P54F
P53F
W
2
W
0
0
0: Port
1: INT0
input
0: Port
1: BUSAK
0
0: Port
1: BUSRQ
Note 1:
Read-modify-write is prohibited for register P5CR, P5FC.
Note 2:
When port 5 is used in the input mode, P5 register controls the built-in pull-up resistor. Read-modify-write is
prohibited in the input mode or the I/O mode. Setting the built-in pull-up resistor may be depended on the states of
the input pin.
Note 3:
When P55 pin is used as a WAIT pin, set P5CR<P55C> to 0 and chip select/WAIT control register <BnW2:0> to
010.
Figure 3.6.10 Register for Port 5
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Port 6 (P60 to P63)
Port 6 is a 4-bit output port. When reset, the P62 latch is cleared to 0 while the P60 to
P63 output latches are set to 1.
In addition to functioning as an output port, this port can output standard chip select
signals ( CS0 to CS3 ). These settings are made by using the P6FC register. When reset, the
P6FC register has all of its bits cleared to 0, so that the port is set for output mode.
Internal data bus
Reset
Funtion
control
(on bit basis)
P6FC write
S
S
Output
lacth
A
B Selector
Output buffer
P60 ( CS0 ),
P61 ( CS1 ),
P63 ( CS3 )
P6 write
P6 read
CS0 , CS1 , CS3
Figure 3.6.11 Port 60, 61, 63
Reset
Function control
(on bit basis)
P6FC write
S
R
Output
latch
A
B
Selector
Internal data bus
3.6.4
P62 ( CS2 )
Output buffer
P6 write
CS2
P6 read
Figure 3.6.12 Port 62
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Port 6 Register
7
6
5
4
P6
Bit symbol
(0012H) Read/Write
3
2
P63
P62
1
0
P61
P60
1
1
R/W
After reset
1
0
Port 6 Function Register
7
P6FC
6
5
4
Bit symbol
3
2
1
0
P63F
P62F
P61F
P60F
(0015H) Read/Write
W
After reset
0
0
0
0: Port 1 1: CS
Function
0
Note: Read-modify-write is prohibited for the registers P6FC.
0
Port (P60)
1
CS0
0
Port (P61)
1
CS1
0
Port (P62)
1
CS2
0
Port (P63)
1
CS3
Figure 3.6.13 Register for Port 6
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3.6.5
Port 7 (P70 to P75)
Port 7 is a 6-bit general-purpose I/O port. Each bit can be set individually for input or
output. Resetting sets port 7 to be an input port. In addition to functioning as a
general-purpose I/O port, the individual port can also have the following functions: Port 70
and 73 can function as the inputs TA0IN and TA4IN to the 8-bit timer, and port 71, 72 and
74 can function as the 8-bit timer outputs TA1OUT, TA3OUT and TA5OUT. For each of the
output pins, timer output can be enabled by writing a 1 to the corresponding bit in the port
7 function register (P7FC).
Resetting resets all bits of the registers P7CR and P7FC to 0, and sets all bits to be input
port pins.
Reset
Direction control
(on bit basis)
P7CR write
Function control
(on bit basis)
Internal data bus
P7FC write
S
Output latch
P70 (TA0IN/INT1)
P73 (TA4IN/INT3)
P75 (INT4)
S B
P7 write
Selector
INT1
INT3
INT4
P7 read
A
Level or edge
and
Rising edge or falling edge
TA0IN
IIMC0<I1LE, I1EDGE>
IIMC1<I3LE, I3EDGE>
IIMC1<I4LE, I4EDGE>
TA4IN
Figure 3.6.14 Port 70, 73, 75
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Reset
Direction control
(on bit basis)
P7CR write
Function control
(on bit basis)
Internal data bus
P7FC write
S
Output latch
A S
Selector
Timer F/F OUT
P7 write
B
TA1OUT: TMRA1
TA5OUT: TMRA5
P71 (TA1OUT)
P74 (TA5OUT)
B
Selector
P7 read
S A
Figure 3.6.15 Port 71, 74
Reset
Direction control
(on bit basis)
P7CR write
Function control
(on bit basis)
P7FC write
Internal data bus
Function control
(on bit basis)
P7FC write
S
Output latch
Timer F/F OUT
P7 write
(TA3OUT: TMRA3)
A S
Selector
P72 (TA3OUT/INT2)
B
B
Selector
P7 read
S A
INT2
Edge or level
and
Rising edge or falling edge
IIMC0<I2LE, I2EDGE>
Figure 3.6.16 Port 72
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Port 7 Register
7
6
P7
Bit symbol
(0013H) Read/Write
5
4
3
P75
P74
P73
2
1
0
P72
P71
P70
R/W
After reset
Data from external port (Output latch register is set to 1.)
Port 7 Control Register
7
P7CR
6
Bit symbol
5
4
3
2
1
0
P75C
P74C
P73C
P72C
P71C
P70C
0
0
0
0
0
0
1
0
P71F
P70F
(0016H) Read/Write
W
After reset
Function
0: Input 1: Output
Port 7 I/O setting
0
Input
1
Output
Port 6 Function Register
7
P7FC
Bit symbol
(0017H) Read/Write
After reset
Function
6
5
P72F2
P75F
W
4
3
2
P74F
P73F
P72F1
W
W
W
W
0
0
0
0
0
0
0
0: Port
0: Port
0: Port
0: Port
0: Port
0: Port
0: Port
1: INT2
1: INT4
1: TA5OUT 1: INT3
1: TA3OUT 1: TA1OUT 1: INT1
input
input
input
input
Note: Read-modify-write is prohibited for the registers
P7CR and P7FC.
Setting P71 as timer output 1
P7FC<P71F>
1
P7CR<P71C>
1
Setting P72 as timer output 3
P7FC<P72F1>
1
P7CR<P72C>
1
Setting P74 as timer output 5
P7FC<P74F>
1
P7CR<P74C>
1
Figure 3.6.17 Register for Port 7
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Port 8 (P80 to P87)
Port 80 to 87 constitute a 8-bit general-purpose I/O port. Each bit can be set
individually for input or output. Resetting sets P80 to P87 to be an input port. It also
sets all bits of the output latch register to 1.
In addition to functioning as general-purpose I/O port, P80 to P87 can also function
as the I/O for serial channels 0. These function can be enabled for I/O by writing a 1 to
the corresponding bit of the port 8 function register (P8FC).
Resetting resets all bits of the registers P8CR and P8FC to 0 and sets all bits to be
input port (with pull-up resistors).
(1) Port 80 (TXD0), 84 (TXD1)
As well as functioning as I/O port, port 80, 84 can also function as serial channel
TXD output pins.
These port feature a programmable open-drain function.
Reset
Derection control
(on bit basis)
P8CR write
P-ch (Programmable pul up)
Internal data bus
3.6.6
Function control
(on bit basis)
P8FC write
S
Output latch
A
S
Selector
P8 write
TXD0 or TXD1
B
S
B
Open-drain
possible
ODE<ODE80, 84>
output buffer
P80 (TXD0)
P84 (TXD1)
Selector
P8 read
A
Figure 3.6.18 Port 80, 84
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(2) Port 81 (RXD0), 85 (RXD1)
Port 81, 85 are I/O port and can also be used as RXD input pin for the serial
channels.
Reset
P-ch (Programmable pull up)
Internal data bus
Derection control
(on bit basis)
P8CR write
S
Output latch
S
P8 write
B
Output buffer
P81 (RXD0)
P85 (RXD1)
Selector
P8 read
A
RXD0 or RXD1
Figure 3.6.19 Port 81, 85
(3) Port 82 ( CTS0 /SCLK0), 86 ( CTS1 /SCLK1)
Port 82, 86 are I/O port and can also be used as the CTS input pins or SCLK I/O
pins for the serial channels.
Reset
Direction control
(on bit basis)
P-ch (Programmable pull up)
Internal data bus
P8CR write
Function contorl
(on bit basis)
P8FC write
S
Output latch
A
S
Selector
P8 write
SCLK0
SCLK1
B
P82 (SCLK0/ CTS0 )
P86 (SCLK1/ CTS1 )
S B
Selector
P8 read
A
SCLK0, CTS0 input
SCLK1, CTS1 input
Figure 3.6.20 Port 82, 86
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(4) Port 83 ( STS0 ), 87 ( STS1 )
Port 83, 87 are I/O port and can also be used as STS output for the received
data request signal.
Reset
Direction control
(on bit basis)
P8CR write
Internal data bus
Function control
(on bit basis)
P8FC write
S
Output latch
P8 write
P-ch (Programmable pull up)
S
A
Y
Selector
B
P83 ( STS0 )
P87 ( STS1 )
STS0 or STS1
S
P8 read
B
Selector
Y
A
Figure 3.6.21 Port 83, 87
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Port 8 Register
P8
Bit symbol
(0018H) Read/Write
7
6
5
4
P87
P86
P85
P84
3
2
1
0
P83
P82
P81
P80
R/W
After reset
Data from external port (Output latch register is set to 1.)
Function
0(Output latch register) : Pull-up resistor OFF
1(Output latch register): Pull-up resistor ON
Port 8 Control Register
P8CR
Bit symbol
(001AH) Read/Write
After reset
7
6
5
4
P87C
P86C
P85C
P84C
3
2
1
0
P83C
P82C
P81C
P80C
0
0
0
0
W
0
0
0
0
Function
0: Input 1: Output
Port 8 I/O setting
0
Input
1
Output
Port 8 Function Register
P8FC
Bit symbol
(001BH) Read/Write
After reset
Function
7
6
4
3
2
P87F
P86F
P84F
P83F
P82F
P80F
W
W
W
W
W
W
0
0
0
0
0
0
0: Port
1: STS1
output
5
0: Port
1: SCLK1
output
0: Port
1: TXD1
output
0: Port
1: STS 0
output
0: Port
1: SCLK0
output
1
0
0: Port
1: TXD0
input
To set P80, 84 for TXD0, TXD1 output
Note 1: Read-modify-write is prohibited for the registers
P8CR and P8FC.
Note 2: Writing 1 to bit0 of the ODE register sets the TXD0,
1 pin to be open drain.
No register is provided for switching between the
I/O port and RXD input functions of the P81/RXD0,
P85/RXD1 pin. Hence, when port 8 is used as an
input port, the serial data input signals received on
those pins are also input to the SIO.
P8FC<P80F><P84F>
1
P8CR<P80C><P84C>
1
To set P82, P86 for SCLK0, SCLK1 output
P8FC<P82F><P86F>
1
P8CR<P82C><P86C>
1
To set P83, P87 for STS 0 , STS1 output
P8FC<P83F><P87F>
1
P8CR<P83C><P87C>
1
Figure 3.6.22 Register for Port 8
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Port 9 (P90, P93 to P96)
Port 9 is an 8-bit general-purpose I/O port. Each bit can be set individually for input or
output, Resetting sets port 9 to be an input port, it also sets all bits in the output latch
register P9 to 1. In addtion to functioning as a general-purpose I/O port, the various pins of
port 9 can also function as the clock input for the 16-bit timer flipflop putput, on as input
INT5. These functions cn be enabled by writing a 1 to the corresponding bits in the port 9
function registers (P9FC).
(1) P90
Reset
Direction control
(on bit basis)
P9CR write
Internal data bus
3.6.7
S
Output latch
P90 (INT5)
P9 write
S
B
Selector
Y
A
P9 read
Level or edge
and
Rising edge or falling edge
INT5
P9FC<P90F>
IIMC1<I5LE/I5EDGE>
Figure 3.6.23 Port 90
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(2) P93 to P96
Reset
Direction control
(on bit basis)
P9CR write
S
Output latch
P93 (TB0IN0)
P94 (TB0IN1)
S
P9 write
B
Selector
P9 read
Internal data bus
TB0IN0
TB0IN1
A
Reset
Direction control
(on bit basis)
P9CR write
Function control
(on bit basis)
P9FC write
S
Output latch
A
P9 write
Timer F/F OUT
S
Selector
B
P95 (TB0OUT0)
P96 (TB0OUT1)
TB0OUT0: TMRB0
TB0OUT1: TMRB0
B
Selector
P9 read
S A
Figure 3.6.24 Port P93 to P96
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Port 9 Register
7
P9
Bit symbol
(0019H) Read/Write
6
5
P96
P95
After reset
4
3
2
P94
P93
1
0
P90
R/W
R/W
Data from external port
(Output latch register is set to 1.)
Data from
external port
(Output latch
register is set
to 1.)
Port 9 Control Register
7
P9CR
Bit symbol
(001CH) Read/Write
6
5
P96C
P95C
4
3
P94C
P93C
0
0
2
1
P90C
W
After reset
0
0
Function
0
W
0
0: Input
1: Output
0: Input
1: Output
Port 9 I/O setting
0
Input
1
Output
Port 9 Function Register
7
P9FC
Bit symbol
(001DH) Read/Write
After reset
Function
6
5
P96F
P95F
4
3
2
1
P90F
0
W
W
W
0
0
0
0: Port
0: Port
1: TB0OUT1 1: TB0OUT0
0: Port
1: INT5
input
To set P95 for timer 8 output
1
P9FC<P95F>
1
P9CR<P95C>
To set P96 for timer 9 output
Note: Read-modify-write is prohibited for the registers
P9CR and P9FC.
1
P9FC<P96F>
1
P9CR<P96C>
Figure 3.6.25 Register for Port 9
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3.6.8
Port A (PA0 to PA7)
Port A is an 8-bit input port and can also be used as the analog input pins for the internal
AD converter.
Internal data bus
PA0 to PA7
( ADTRG , AN0
to AN7)
Port A read
Conversion
result
register
AD read
AD
converter
Channel
selector
ADTRG
(Only PA3)
Figure 3.6.26 Port A
Port A Register
PA
Bit symbol
(0019H) Read/Write
After reset
7
6
5
4
PA7
PA6
PA5
PA4
3
2
1
0
PA3
PA2
PA1
PA0
R
Data from external port.
Note: The input channel selection of AD converter and the permission of ADTRG input are set by AD converter mode register
ADMOD1.
Figure 3.6.27 Register for Port A
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3.6.9
Port Z (PZ2, PZ3)
Port Z is a 4-bit general-purpose I/O port. I/O is set using control register PZCR and
PZFC. Resetting resets all bits of the output latch PZ to 1, the control register PZCR and
the function register PZFC to 0 and sets PZ2 and PZ3 to input mode with pull-up register.
In addition to functioning as a general-purpose I/O port. Port Z also functions as I/O for
the CPU’s control/status signal.
Reset
Direction control
(on bit basis)
PZCR write
(on bit basis)
PZFC write
P-ch (Programmable pull up)
S
S
Output
latch
A
Selector
Internal data bus
Function control
B
PZ2( HWR )
Output buffer
PZ write
HWR
PZ read
Figure 3.6.28 Port Z2
Reset
Internal data bus
Direction control
(on bit basis)
P-ch (Programmable pull up)
PZCR write
S
Output latch
PZ write
PZ3
S
Output buffer
B
Selector
PZ read
A
Figure 3.6.29 Port Z3
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Port Z Register
7
6
5
4
PZ
Bit symbol
(007DH) Read/Write
3
2
PZ3
PZ2
1
0
1
0
1
0
R/W
After reset
Data from external port
(Output latch register is
set to 1.)
Port Z Control Register
7
6
5
4
PZCR
Bit symbol
(007EH) Read/Write
3
2
PZ3
PZ2
W
After reset
0
Function
0
0: Input 1: Output
Setting port Z as I/O
0
Input
1
Output
Port Z Control Register
7
6
5
4
3
PZFC
Bit symbol
(007FH) Read/Write
2
PZ2F
W
After reset
0
Function
0: Port
1: HWR
Note: Read-modify –write is prohibited for the registers PZCR and PZFC.
Figure 3.6.30 Register for Port Z
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3.7
Chip Select/Wait Controller
On the TMP91C829, four user specifiable address areas (CS0 to CS3) can be set. The data bus
width and the number of waits can be set independently for each address area (CS0 to CS3 plus
any other).
The pins CS0 to CS3 (which can also function as P60 to P63) are the respective output pins
for the areas CS0 to CS3. When the CPU specifies an address in one of these areas, the
corresponding CS0 to CS3 pin outputs the chip select signal for the specified address area (in
ROM or SRAM). However, in order for the chip select signal to be output, the port 6 function
register P6FC must be set. External connection of ROM and SRAM is supported.
The areas CS0 to CS3 are defined by the values in the memory start address registers
MSAR0 to MSAR3 and the memory address mask registers MAMR0 to MAMR3.
The chip select/wait control registers B0CS to B3CS and BEXCS should be used to specify the
master enable/disable status the data bus width and the number of waits for each address area.
The input pin which controls these states is the bus wait request pin ( WAIT ).
3.7.1
Specifying an Address Area
The address areas CS0 to CS3 are specified using the memory start address registers
(MSAR0 to MSAR3) and the memory address mask registers (MAMR0 to MAMR3).
During each bus cycle, a compare operation is performed to determine whether or not the
address specified on the bus corresponds to a location in one of the areas CS0 to CS3. If the
result of the comparison is a match, it indicates that the corresponding CS area is to be
accessed. If so, the corresponding CS0 to CS3 pin outputs the chip select signal and the
bus cycle proceeds according to the settings in the corresponding B0CS to B3CS chip
select/wait control register. (See 3.7.2 “Chip Select/Wait Control Registers”.)
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(1) Memory start address registers
Figure 3.7.1 shows the memory start address registers. The memory start address
registers MSAR0 to MSAR3 determine the start addresses for the memory areas CS0
to CS3 respectively. The eight most significant bits (A23 to A16) of the start address
should be set in <S23:16>. The 16 least significant bits of the start address (A15 to A0)
are fixed to 0. Thus the start address can only be set to lie on a 64-Kbyte boundary,
starting from 000000H. Figure 3.7.2 shows the relationship between the value set in
the start address register and the start address.
Memory Start Address Registers (for areas CS0 to CS3)
MSAR0 (00C8H)/ Bit symbol
MSAR1 (00CAH)
Read/Write
MSAR2 (00CCH)/
After reset
MSAR3 (00CEH)
Function
7
6
5
4
3
2
1
0
S23
S22
S21
S20
S19
S18
S17
S16
1
1
1
1
1
1
1
1
R/W
Determines A23 to A16 of start address.
Sets start addresses for areas CS0 to CS3.
Figure 3.7.1 Memory Start Address Register
Start address
Address
000000H
64 Kbytes
Value in start address register (MSAR0 to MSAR3)
000000H .................... 00H
010000H .................... 01H
020000H .................... 02H
030000H .................... 03H
040000H .................... 04H
050000H .................... 05H
060000H .................... 06H
to
to
FF0000H .................... FFH
FFFFFFH
Figure 3.7.2 Relationship between Start Address and Start Address Register Value
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(2) Memory address mask registers
Figure 3.7.3 shows the memory address mask registers. The size of each of the areas
CS0 to CS3 can be set by specifying a mask in the corresponding memory address mask
register (MAMR0 to MAMR3). Each bit in a memory address mask register (MAMR0
to MAMR3) which is set to 1 masks the corresponding bit of the start address which
has been set in the corresponding memory start address register (MSAR0 to MSAR3).
The compare operation used to determine whether or not a bus address is in one of the
areas CS0 to CS3 only compares address bits for which a 0 has been set in the
corresponding bit position in the corresponding memory address mask register.
Also, the address bits which each memory address mask register can mask vary from
register to register; hence, the possible size settings for the areas CS0 to CS3 differ
accordingly.
Memory Address Mask Register (for CS0 area)
MAMR0 Bit symbol
(00C9H) Read/Write
After reset
7
6
5
4
3
2
1
0
V20
V19
V18
V17
V16
V15
V14 to 9
V8
1
1
1
1
R/W
1
1
1
Function
1
Sets size of CS0 area. 0: Used for address compare
Range of possible settings for CS0 area size: 256 bytes to 2 Mbytes.
Memory Address Mask Register (CS1)
MAMR1 Bit symbol
(00CBH) Read/Write
After reset
7
6
5
4
V21
V20
V19
V18
3
2
1
0
V17
V16
V15 to 9
V8
1
1
1
1
R/W
1
1
1
Function
1
Sets size of CS1 area. 0: Used for address compare
Range of possible settings for CS1 area size: 256 bytes to 4 Mbytes.
Memory Address Mask Register (CS2, CS3)
MAMR2 (00CDH)/ Bit symbol
MAMR3 (00CFH) Read/Write
After reset
Function
7
6
5
4
V22
V21
V20
V19
3
2
1
0
V18
V17
V16
V15
1
1
1
1
R/W
1
1
1
1
Sets size of CS2 or CS3 area. 0: Used for address compare
Range of possible settings for CS2 and CS3 area sizes: 32 Kbytes to 8 Mbytes.
Figure 3.7.3 Memory Address Mask Registers
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(3) Setting memory start addresses and address areas
Figure 3.7.4 shows an example in which CS0 is specified to be a 64-Kbyte address
area starting at 010000H.
First, MSAR0<S23:16>, the eight most significant bits of the start address register
and which correspond to the memory start address, are set to 01H. Next, based on the
desired CS0 area size, the difference between the start address and the end address
(01FFFFH) is calculated. Bits 20 to 8 of this result constitute the mask value for the
desired CS0 area size. Setting this value in MAMR0<V20:8> (Bits 20 to 8 of the
memory address mask register) sets the desired area size for CS0. In this example 07H
is set in MAMR0, specifying an area size of 64 Kbytes.
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
F
1
1
1
1
F
1
1
1
1
F
1
1
H
F
Memory
end
address
CS0 area
size
(64 Kbytes)
S23 S22 S21 S20 S19 S18 S17 S16
MSAR0
0
0
0
0
0
0
0
0
Memory
start
address
1
1
H
V20 V19 V18 V17 V16 V15
MSMR0 0
0
0
0
0
0
0
0
0
1
V14 to V9
1
1
1
1
V8
1
1
1
7
1
1
1
1
1
1
1
H
1
Memory address
mask register
setting
Setting of 07H specifies a 64-Kbyte area.
Figure 3.7.4 Example Showing How to Set the CS0 Area
A reset sets MSAR0 to MSAR3, and MAMR0 to MAMR3 to FFH. In addition,
B0CS<B0E>, B1CS<B1E> and B3CS<B3E> are reset to 0, disabling the CS0, CS1, and
CS3 areas. However, since a reset resets B2CS<B2M> to 0 and sets B2CS<B2E> to 1,
CS2 is enabled with the address range 003000H to 01F7FFH, 020000H to FFFFFFH.
When addresses outside the areas specified as CS0 to CS3 are accessed, the bus width
and number of waits specified in BEXCS are used. (See 3.7.2 “Chip Select/Wait
Controller”.)
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TMP91C829
(4) Address area size specification
Table 3.7.1 shows the valid area sizes for each CS area and indicates which method
can be used to make the size setting. A “Δ” indicates that it is not possible to set the
area size in question using the memory start address register and memory address
mask register. If an area size for a CS area marked “Δ” in the table is to be set, the start
address must either be set to 000000H or to a value that is greater than 000000H by an
integer multiple of the desired area size.
If the CS2 area is set to 16 Mbytes or if two or more areas overlap, the
lowest-numbered CS area has highest priority (e.g., CS0 has a higher priority than any
other area).
Example: To set the area size for CS0 to 128 Kbytes:
a. Valid start addresses
000000H
020000H
040000H
060000H
b.
128 Kbytes
128 Kbytes
Any of these addresses may be set as the start address.
128 Kbytes
Invalid start addresses
000000H
010000H
030000H
050000H
64 Kbytes
This is not an integer multiple of the desired area size
setting. Hence, none of these addresses can be set as the
start address.
128 Kbytes
128 Kbytes
Table 3.7.1 Valid Area Sizes for Each CS Area
Size (bytes)
CS area
CS0
CS1
CS2
CS3
256
512
32 K
64 K
128 K
256 K
512 K
1M
2M
○
○
○
○
○
○
○
○
○
Δ
Δ
Δ
Δ
Δ
Δ
Δ
Δ
Δ
Δ
Δ
Δ
Δ
Δ
Δ
Δ
Δ
Δ
Δ
Δ
Δ
Δ
Δ
Δ
Δ
○
○
91C829-72
4M
8M
2006-03-15
TMP91C829
3.7.2
Chip Select/Wait Control Registers
Figure 3.7.5 lists the chip select/wait control registers.
The master enable/disable, chip select output waveform, data bus width, and number of
wait states for each address area (CS0 to CS3 plus any other) are set in the respective chip
select/wait control registers, B0CS to B3CS or BEXCS.
Chip Select/Wait Control Register
7
B0CS
(00C0H)
Bit symbol
B0E
Read/Write
W
Readmodifywrite
instructions
are
prohibited.
After reset
B1CS
(00C1H)
Bit symbol
B1E
Read/Write
W
Readmodifywrite
instructions
are
prohibited.
After reset
B2CS
(00C2H)
Bit symbol
Readmodifywrite
instructions
are
prohibited.
After reset
B3CS
(00C3H)
Bit symbol
B3E
Read/Write
W
Readmodifywrite
instructions
are
prohibited.
After reset
BEXCS
(00C7H)
Bit symbol
Readmodifywrite
instructions
are
prohibited.
After reset
Function
Function
6
5
4
3
B0OM1
B0OM0
B0BUS
Function
1
0
B0W2
B0W1
B0W0
W
0
0: Disable
1: Enable
0
0
Chip select output
waveform selection
00: For ROM/SRAM
01:
10:
Don’t care
11:
B1OM1
0
Data bus
width
0: 16 bits
1: 8 bits
B1OM0
0
0
0
Number of waits
000: 2 waits
001: 1 wait
010: (1 + N) waits 1xx: Reserved
011: 0 waits
B1BUS
B1W2
0
0: Disable
1: Enable
0
0
Chip select output
waveform selection
00: For ROM/SRAM
01:
10:
Don’t care
11:
B2E
B2M
B2OM1
0
Data bus
width
0: 16 bits
1: 8 bits
B2OM0
B2BUS
B2W2
B2W1
B2W0
W
1
0: Disable
1: Enable
0
CS2 area
selection
0: 16-Mbyte
area
1: CS area
0
0
Chip select output
waveform selection
00: For ROM/SRAM
01:
10:
Don’t care
11:
B3OM1
B3OM0
0
Data bus
width
0: 16 bits
1: 8 bits
0
0
0
Number of waits
000: 2 waits
001: 1 wait
010: (1 + N) waits 1xx: Reserved
011: 0 waits
B3BUS
B3W2
0
0: Disable
1: Enable
0
0
Chip select output
waveform selection
00: For ROM/SRAM
01:
10:
Don’t care
11:
0
Data bus
width
0: 16 bits
1: 8 bits
CS area disable
1
CS area enable
B3W0
0
0
0
Number of waits
000: 2 waits
001: 1 wait
010: (1 + N) waits 1xx: Reserved
011: 0 waits
BEXBUS
BEXW2
BEXW1
BEXW0
W
0
Data bus
width
0: 16 bits
1: 8 bits
0
0
0
Number of waits
000: 2 waits
001: 1 wait
010: (1 + N) waits 1xx: Reserved
011: 0 waits
Chip select output
waveform selection
Master enable bit
0
B3W1
W
Function
Number of address area waits
(See 3.7.2 (3) “Wait control”.)
00 For ROM/SRAM
01
10 Don’t care
11
CS2 area selection
1
B1W0
0
0
0
Number of waits
000: 2 waits
001: 1 wait
010: (1 + N) waits 1xx: Reserved
011: 0 waits
Read/Write
0
B1W1
W
Read/Write
Function
2
16-Mbyte area
Specified address area
Data bus width selection
0
16-bit data bus
1
8-bit data bus
Figure 3.7.5 Chip Select/Wait Control Registers
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TMP91C829
(1) Master enable bits
Bit7 (<B0E>, <B1E>, <B2E>, or <B3E>) of a chip select/wait control register is the
master bit which is used to enable or disable settings for the corresponding address
area. Writing 1 to this bit enables the settings. A reset disables <B0E>, <B1E> and
<B3E> (e.g., sets them to 0) and enables <B2E> (e.g., sets it to 1). Hence after a reset
only the CS2 area is enabled.
(2) Data bus width selection
Bit3 (<B0BUS>, <B1BUS>, <B2BUS>, <B3BUS>, or <BEXBUS>) of a chip
select/wait control register specifies the width of the data bus. This bit should be set to
0 when memory is to be accessed using a 16-bit data bus, and to 1 when an 8-bit data
bus is to be used.
This process of changing the data bus width according to the address being accessed
is known as dynamic bus sizing. For details of this bus operation see Figure 3.7.2.
Table 3.7.2 Dynamic Bus Sizing
Operand Data Operand Start Memory Data
Bus Width
Address
Bus Width
8 bits
2n + 0
(Even number)
2n + 1
(Odd number)
16 bits
2n + 0
(Even number)
2n + 1
(Odd number)
2n + 0
(Even number)
2n + 1
(Odd number)
CPU Data
D15 to D8
D7 to D0
8 bits
2n + 0
xxxxx
b7 to b0
16 bits
2n + 0
xxxxx
b7 to b0
8 bits
2n + 1
xxxxx
b7 to b0
16 bits
2n + 1
b7 to b0
xxxxx
8 bits
2n + 0
xxxxx
b7 to b0
2n + 1
xxxxx
b15 to b8
16 bits
2n + 0
b15 to b8
b7 to b0
8 bits
2n + 1
xxxxx
b7 to b0
2n + 2
xxxxx
b15 to b8
2n + 1
b7 to b0
xxxxx
2n + 2
xxxxx
b15 to b8
2n + 0
xxxxx
b7 to b0
2n + 1
xxxxx
b15 to b8
16 bits
32 bits
CPU Address
8 bits
2n + 2
xxxxx
b23 to b16
2n + 3
xxxxx
b31 to b24
16 bits
2n + 0
b15 to b8
b7 to b0
2n + 2
b31 to b24
b23 to b16
8 bits
2n + 1
xxxxx
b7 to b0
2n + 2
xxxxx
b15 to b8
2n + 3
xxxxx
b23 to b16
2n + 4
xxxxx
b31 to b24
16 bits
2n + 1
b7 to b0
xxxxx
2n + 2
b23 to b16
b15 to b8
2n + 4
xxxxx
b31 to b24
Input data in bit positions marked xxxxx is ignored during a read. During a write,
the bus lines corresponding to these bit positions go high-impedance and the write
strobe signal for the bus remains inactive.
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TMP91C829
(3) Wait control
Bits 0 to 2 (<B0W0:2>, <B1W0:2>, <B2W0:2>, <B3W0:2>, or <BEXW0:2>) of a chip
select/wait control register specify the number of waits that are to be inserted when
the corresponding memory area is accessed.
The following types of wait operation can be specified using these bits. Bit settings
other than those listed in the table should not be made.
Table 3.7.3 Wait Operation Settings
<BxW2:0>
Number of Waits
000
2 waits
001
1 wait
010
(1 + N) waits
011
0 waits
1xx
Reserved
Wait Operation
Inserts a wait of two states, irrespective of the WAIT pin state.
Inserts a wait of one state, irrespective of the WAIT pin state.
Inserts one wait state, then continuously samples the state of the
WAIT pin. While the WAIT pin remains low, the wait continues; the
bus cycle is prolonged until the pin goes high.
Ends the bus cycle without a wait, regardless of the WAIT pin state.
Do not set.
A reset sets these bits to 000 (2 waits).
(4) Bus width and wait control for an area other than CS0 to CS3
The chip select/wait control register BEXCS controls the bus width and number of
waits when memory locations which are not in one of the four user-specified address
areas (CS0 to CS3) are accessed. The BEXCS register settings are always enabled for
areas other than CS0 to CS3.
(5) Selecting 16-Mbyte area/specified address area
Setting B2CS<B2M> (bit6 of the chip select/wait control register for CS2) to 0
designates the 16-Mbyte area 001800H to 01F7FFH, 020000H to FFFFFFH as the CS2
area. Setting B2CS<B2M> to 1 designates the address area specified by the start
address register MSAR2 and the address mask register MAMR2 as CS2 (e.g., if
B2CS<B2M> = 1, CS2 is specified in the same manner as CS0, CS1, and CS3).
A reset clears this bit to 0, specifying CS2 as a 16-Mbyte address area.
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2006-03-15
TMP91C829
(6) Procedure for setting chip select/wait control
When using the chip select/wait control function, set the registers in the following
order:
a.
Set the memory start address registers MSAR0 to MSAR3.
Set the start addresses for CS0 to CS3.
b.
Set the memory address mask registers MAMR0 to MAMR3.
Set the sizes of CS0 to CS3.
c.
Set the chip select/wait control registers B0CS to B3CS.
Set the chip select output waveform, data bus width, number of waits and
master enable/disable status for CS0 to CS3 .
The CS0 to CS3 pins can also function as pins P60 to P63. To output a chip
select signal using one of these pins, set the corresponding bit in the port 6
function register P6FC to 1.
If a CS0 to CS3 address is specified which is actually an internal I/O, RAM or
ROM area address, the CPU accesses the internal address area and no chip select
signal is output on any of the CS0 to CS3 pins.
Example:
In this example CS0 is set to be the 64-Kbyte area 010000H to 01FFFFH. The bus
width is set to 16 bits and the number of waits is set to 0.
MSAR0 = 01H ............Start address: 010000H
MAMR0 = 07H...........Address area: 64 Kbytes
B0CS = 83H ...............ROM/SRAM, 16-bit data bus, zero waits, CS0 area settings
enabled.
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TMP91C829
3.7.3
Connecting External Memory
Figure 3.7.6 shows an example of how to connect external memory to the TMP91C829.
In this example the ROM is connected using a 16-bit bus. The RAM and I/O are
connected using an 8-bit bus.
TMP91C829
CS0
CS1
Address bus
CS2
A0
to
A23
CS
CS
Upper byte
ROM
OE
CS
Lower byte
ROM
OE
CS
8-bit
RAM
OE WE
8-bit
I/O
OE WE
D8
to
D15
D0
to
D7
RD
WR
Figure 3.7.6 Example of External Memory Connection
(ROM uses 16-bit bus; RAM and I/O use 8-bit bus.)
A reset clears all bits of the port 4 control register P6CR and the port 6 function register
P6FC to 0 and disables output of the CS signal. To output the CS signal, the appropriate bit
must be set to 1.
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3.8
8-Bit Timers (TMRA)
The TMP91C829 features six built-in 8-bit timers.
These timers are paired into three modules: TMRA01, TMRA23 and TMRA45. Each module
consists of two channels and can operate in any of the following four operating modes.
•
8-bit interval timer mode
•
16-bit interval timer mode
•
8-bit programmable square wave pulse generation output mode (PPG − Variable duty cycle
with variable period)
•
8-bit pulse width modulation output mode (PWM − Variable duty cycle with constant
period)
Figure 3.8.1 to 3.8.3 show block diagrams for TMRA01, TMRA23 and TMRA45.
Each channel consists of an 8-bit up counter, an 8-bit comparator and an 8-bit timer register.
In addition, a timer flip-flop and a prescaler are provided for each pair of channels.
The operation mode and timer flip-flops are controlled by five control SFRs (Special function
registers).
Each of the four modules (TMRA01, TMRA23, and TMRA45) can be operated independently.
All modules operate in the same manner; hence only the operation of TMRA01 is explained
here.
Table 3.8.1 Registers and Pins for Each Module
Module
Input pin for external
External
Pin
SFR
clock
Output pin for timer
TMRA01
TA0IN
(Shared with P70)
TMRA23
No
TMRA45
TA4IN
(Shared with P73)
TA1OUT
TA3OUT
TA5OUT
flip-flop
(Shared with P71)
(Shared with P72)
(Shared with P74)
Timer run register
TA01RUN (0100H)
TA23RUN (0108H)
TA45RUN (0110H)
TA0REG (0102H)
TA2REG (010AH)
TA4REG (0112H)
TA1REG (0103H)
TA3REG (010BH)
TA5REG (0113H)
TA01MOD (0104H)
TA23MOD (010CH)
TA45MOD (0114H)
TA1FFCR (0105H)
TA3FFCR (010DH)
TA5FFCR (0115H)
Timer register
(address) Timer mode register
Timer flip-flop control
register
91C829-78
2006-03-15
External input
clock: TA0IN
91C829-79
φT256
Internal data bus
Register buffer 0
8-bit timer register
TA0REG
8-bit up counter
(UC1)
TA01RUN<TA1RUN>
TMRA0
match output:
TA0TRG
TA1FFCR
Timer
flip-flop
TA1FF
Timer flip-flop
output: TA1OUT
Internal data bus TMRA1
interrupt output: INTTA1
8-bit timer
register TA1REG
Match
8-bit comparator detect
(CP1)
TA01MOD
<TA1CLK1:0>
TA01MOD
<TA01M1:0>
TA0TRG
TMRA0
interrupt output:
INTTA0
Match
detect
TA01MOD
<PWM01:00>
8-bit up counter
(CP0)
TA01MOD
<TA0CLK1:0>
n
φT1
φT16
φT256
Selector
Run/clear TA01RUN
<TA01PRUN>
overflow
2
8-bit up counter
(UC0)
TA01RUN<TA0RUN>
φT16
8 16 32 64 128 256 512
φT4
TA01RUN
<TA0RDE>
φT1
φT4
φT16
4
Selector
φT1
2
Prescaler
3.8.1
Prescaler
clock: φT0
TMP91C829
Block Diagrams
Figure 3.8.1 TMRA01 Block Diagram
2006-03-15
Prescaler
clock: φT0
φT4
91C829-80
TA23RUN
<TA2RDE>
Internal data bus
Register buffer 2
8-bit timer register
TA2REG
8-bit up counter
(UC3)
TA23RUN<TA3RUN>
TA3FFCR
Timer
flip-flop
TA3FF
Timer flip-flop
output: TA3OUT
TMRA2
Internal data bus TMRA3
match output:
interrupt output: INTTA3
TA2TRG
8-bit timer
register TA3REG
Match
8-bit comparator detect
register (CP3)
TA23MOD
<TA3CLK1:0>
φT1
φT16
φT256
TA23MOD
<TA23M1:0>
TA2TRG
TMRA2
interrupt output:
INTTA2
Match
8-bit comparator detect
(CP2)
TA23MOD
<PWM21:20>
2
overflow
n
8-bit up counter
(UC2)
Selector
Run/clear TA23RUN
<TA23PRUN>
φT256
TA23RUN<TA2RUN>
φT16
8 16 32 64 128 256 512
TA23MOD
<TA2CLK1:0>
φT1
φT4
φT16
4
Selector
φT1
2
Prescaler
TMP91C829
Figure 3.8.2 TMRA23 Block Diagram
2006-03-15
External input
clock: TA4IN
Prescaler
clock: φT0
φT4
91C829-81
TA45RUN
<TA4RDE>
Internal data bus
Register buffer 4
8-bit timer
register TA4REG
8-bit comparator
(CP4)
8-bit up counter
(UC5)
TA45RUN<TA5RUN>
TMRA4
match output:
TA4TRG
TA5FFCR
Timer
flip-flop
TA5FF
Timer flip-flop
output: TA5OUT
Internal data bus TMRA5
interrupt output: INTTA5
8-bit timer register
TA5REG
Match
8-bit comparator detect
(CP5)
TA45MOD
<TA5CLK1:0>
φT1
φT16
φT256
TA45MOD
<TA45M1:0>
TA4TRG
TMRA4
interrupt output:
INTTA4
Match
detect
TA45MOD
<PWM41:40>
2
overflow
n
8-bit up counter
(UC4)
Selector
Run/clear TA45RUN
<TA45PRUN>
φT256
TA45RUN<TA4RUN>
φT16
8 16 32 64 128 256 512
TA45MOD
<TA4CLK1:0>
φT1
φT4
φT16
4
Selector
φT1
2
Prescaler
TMP91C829
Figure 3.8.3 TMRA45 Block Diagram
2006-03-15
TMP91C829
3.8.2
Operation of Each Circuit
(1) Prescalers
A 9-bit prescaler generates the input clock to TMRA01.
The clock φT0 is divided by 4 and input to this prescaler. φT0 can be either fFPH or
fc/16 and is selected using the prescaler clock selection register SYSCR0<PRCK1:0>.
The prescaler’s operation can be controlled using TA01RUN<TA0PRUN> in the
timer control register. Setting <TA0PRUN> to 1 starts the count; setting <TA0PRUN>
to 0 clears the prescaler to zero and stops operation. Table 3.8.2 shows the various
prescaler output clock resolutions.
Table 3.8.2 Prescaler Output Clock Resolution
at fc = 36 MHz
Prescaler
Clock Selection
<PRCK1:0>
000 (fc)
001 (fc/2)
(fFPH)
10
(fc/16 clock)
Prescaler Output Clock Resolution
Gear Value
<GEAR2:0>
φT1
φT4
3
5
4
6
2 /fc (0.22 μs) 2 /fc (0.9 μs)
2 /fc (0.4 μs)
2 /fc (1.8 μs)
5
2 /fc (3.6 μs)
6
2 /fc (7.1 μs)
010 (fc/4)
2 /fc (0.9 μs)
011 (fc/8)
2 /fc (1.8 μs)
2 /fc (228 μs)
10
2 /fc (455 μs)
11
2 /fc (910 μs)
11
2 /fc (910 μs)
2 /fc (28 μs)
2 /fc (14 μs)
2 /fc (3.6 μs)
2 /fc (114 μs)
9
2 /fc (7.1 μs)
8
7
XXX
2 /fc (57 μs)
8
2 /fc (14 μs)
2 /fc (14 μs)
2 /fc (3.6 μs)
φT256
7
2 /fc (3.6 μs)
7
7
100 (fc/16)
φT16
9
2 /fc (57 μs)
9
2 /fc (57 μs)
11
12
13
14
15
15
xxx: Don’t care
(2) Up counters (UC0 and UC1)
These are 8-bit binary counters which count up the input clock pulses for the clock
specified by TA01MOD.
The input clock for UC0 is selectable and can be either the external clock input via
the TA0IN pin or one of the three internal clocks φT1, φT4, or φT16. The clock setting is
specified by the value set in TA01MOD<TA01CLK1:0>.
The input clock for UC1 depends on the operation mode. In 16-bit timer mode, the
overflow output from UC0 is used as the input clock. In any mode other than 16-bit
timer mode, the input clock is selectable and can either be one of the internal clocks
φT1, φT16, or φT256, or the comparator output (The match detection signal) from
TMRA0.
For each interval timer the timer operation control register bits
TA01RUN<TA0RUN> and TA01RUN<TA1RUN> can be used to stop and clear the up
counters and to control their count. A reset clears both up counters, stopping the
timers.
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(3) Timer registers (TA0REG and TA1REG)
These are 8-bit registers which can be used to set a time interval. When the value set
in the timer register TA0REG or TA1REG matches the value in the corresponding up
counter, the comparator match detect signal goes active. If the value set in the timer
register is 00H, the signal goes active when the up counter overflows.
The TA0REG are double buffer structure, each of which makes a pair with register
buffer.
The setting of the bit TA01RUN<TA0RDE> determines whether TA0REG’s double
buffer structure is enabled or disabled. It is disabled if <TA0RDE> = 0 and enabled if
<TA0RDE> = 1.
When the double buffer is enabled, data is transferred from the register buffer to the
timer register when a 2noverflow occurs in PWM mode, or at the start of the PPG cycle
in PPG mode. Hence the double buffer cannot be used in timer mode.
A reset initializes <TA0RDE> to 0, disabling the double buffer. To use the double
buffer, write data to the timer register, set <TA0RDE> to 1, and write the following
data to the register buffer. Figure 3.8.4 shows the configuration of TA0REG.
Selector
Timer registers 0 (TA0REG)
B
Y
Shift trigger
Matching detection in PPG cycle
n
2 overflow of PWM
A
Write to TA0REG
Register buffers 0
S
Write
Internal data bus
TA01RUN<TA0RDE>
Figure 3.8.4 Configuration of TA0REG
Note: The same memory address is allocated to the timer register and the register buffer. When
<TA0RDE> = 0, the same value is written to the register buffer and the timer register; when
<TA0RDE> = 1, only the register buffer is written to.
The address of each timer register is as follows.
TA0REG: 000102H
TA1REG: 000103H
TA2REG: 00010AH
TA3REG: 00010BH
TA4REG: 000112H
TA5REG: 000113H
All these registers are write only and cannot be read.
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(4) Comparator (CP0)
The comparator compares the value in an up counter with the value set in a timer
register. If they match, the up counter is cleared to zero and an interrupt signal
(INTTA0 or INTTA1) is generated. If timer flip-flop inversion is enabled, the timer
flip-flop is inverted at the same time.
(5) Timer flip-flop (TA1FF)
The timer flip-flop (TA1FF) is a flip-flop inverted by the match detect signal (8-bit
comparator output) of each interval timer.
Whether inversion is enabled or disabled is determined by the setting of the bit
TA1FFCR<TA1FFIE> in the timer flip-flop control register.
A reset clears the value of TA1FF to 0. Writing 01 or 10 to TA1FFCR<TA1FFC1:0>
sets TA1FF to 0 or 1. Writing 00 to these bits inverts the value of TA1FF (This is
known as software inversion).
The TA1FF signal is output via the TA1OUT pin (which can also be used as P71).
When this pin is used as the timer output, the timer flip-flop should be set beforehand
using the port 7 function register P7FC.
Note: When the double buffer is enabled for an 8-bit timer in PWM or PPG mode, caution is required
as explained below.
If new data is written to the register buffer immediately before an overflow occurs by a
match between the timer register value and the up-counter value, the timer flip-flop may
output an unexpected value.
For this reason, make sure that in PWM mode new data is written to the register buffer by
six cycles (fSYS × 6) before the next overflow occurs by using an overflow interrupt.
In the case of using PPG mode, make sure that new data is written to the register buffer by
six cycles before the next cycle compare match occurs by using a cycle compare match
interrupt.
Example when using PWM mode
Match between
TA0REG and up-counter
n
2 overflow interrupt
(INTTA0)
TA1OUT
tPWM
(PWM cycle)
Desired PWM cycle
change point
Write new data to the register buffer
before the next overflow occurs by
using an overflow interrupt
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3.8.3
SFRs
TMRA01 Run Register
7
TA01RUN Bit symbol
(0100H) Read/Write
5
4
3
2
1
0
I2TA01
TA01PRUN
TA1RUN
TA0RUN
0
0
R/W
After reset
Function
6
TA0RDE
R/W
0
0
Double
IDLE2
8-bit timer run/stop control
0
buffer
0: Stop
0: Stop and clear
0: Disable
1: Operate
1: Run (Count up)
1: Enable
TA0REG double buffer control
0
Disable
1
Enable
Timer run/stop control
0
Stop and clear
1
Run (Count up)
I2TA01: Operation in IDLE2 mode
TA01PRUN: Run prescaler
TA1RUN: Run TMRA1
TA0RUN: Run TMRA0
Note: The values of bits 4 to 6 of TA01RUN are undefined when read.
TMRA23 Run Register
7
TA23RUN Bit symbol
(0108H) Read/Write
5
4
TA2RDE
3
2
I2TA23
TA23PRUN
R/W
After reset
Function
6
1
0
TA3RUN
TA2RUN
0
0
R/W
0
0
Double
IDLE2
8-bit timer run/stop control
0
buffer
0: Stop
0: Stop and clear
0: Disable
1: Operate
1: Run (Count up)
1: Enable
TA2REG double buffer control
Timer run/stop control
0
Disable
0
Stop and clear
1
Enable
1
Run (Count up)
I2TA23: Operation in IDLE2 mode
TA23PRUN: Run prescaler
TA3RUN: RunTMRA3
TA2RUN: Run TMRA2
Note: The values of bits 4 to 6 of TA23RUN are undefined when read.
Figure 3.8.5 TMRA Registers
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TMRA45 Run Register
7
TA45RUN Bit symbol
(0110H) Read/Write
5
4
TA4RDE
3
2
I2TA45
TA45PRUN
R/W
After reset
Function
6
1
0
TA5RUN
TA4RUN
0
0
R/W
0
0
0
Double
IDLE2
8-bit timer run/stop control
buffer
0: Stop
0: Stop and clear
0: Disable
1: Operate
1: Run (Count up)
1: Enable
TA4REG double buffer control
Timer run/stop control
0
Disable
0
Stop and clear
1
Enable
1
Run (Count up)
I2TA45: Operation during IDLE2 mode
TA45PRUN: Run for prescaler
TA5RUN: Run TMRA5
TA4RUN: Run TMRA4
Note: The values of bits 4 to 6 of TA45RUN are undefined when read.
Figure 3.8.6 TMRA Registers
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TA01MOD Bit symbol
(0104H) Read/Write
After reset
Function
TMRA01 Mode Register
5
4
7
6
TA01M1
TA01M0
PWM01
PWM00
3
2
1
0
TA1CLK1
TA1CLK0
TA0CLK1
TA0CLK0
0
0
0
0
R/W
0
0
0
0
Operation mode
PWM cycle
Source clock for TMRA1
Source clock for TMRA0
00: 8-bit timer mode
00: Reserved
00: TA0TRG
00: TA0IN pin
01: 16-bit timer mode
01: 2
6
01: φT1
01: φT1
10: 8-bit PPG mode
10: 2
7
10: φT16
10: φT4
11: 8-bit PWM mode
11: 2
8
11: φT256
11: φT16
TMRA0 source clock selection
00
TA0IN (External input)
01
φT1 (Prescaler)
10
φT4 (Prescaler)
11
φT16 (Prescaler)
TMRA1 source clock selection
TA01MOD
<TA01M1:0> ≠ 01
Comparator output from
00
TMRA0
01
φT1
10
φT16
11
φT256
TA01MOD
<TA01M1:0> = 01
Overflow output from
TMRA0
(16-bit timer mode)
PWM cycle selection
00
Reserved
01
2 × source clock
10
2 × source clock
11
2 × source clock
6
7
8
TMRA01 operation mode selection
00
Two 8-bit timers
01
16-bit timer
10
8-bit PPG
11
8-bit PWM (TMRA0), 8-bit timer (TMRA1)
Figure 3.8.7 TMRA Registers
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TMRA23 Mode Register
TA23MOD Bit symbol
(010CH)
7
6
5
4
3
2
1
0
TA23M1
TA23M0
PWM21
PWM20
TA3CLK1
TA3CLK0
TA2CLK1
TA2CLK0
0
0
0
0
0
0
0
0
Read/Write
After reset
Function
R/W
Operation mode
PWM cycle
TMRA3 clock for TMRA3 TMRA2 clock for TMRA2
00: 8-bit timer mode
00: Reserved
01: 16-bit timer mode
01: 2
10: 8-bit PPG mode
10: 2
11: 8-bit PWM mode
11: 2
00: TA2TRG
00: Reserved
6
01: φT1
01: φT1
7
10: φT16
10: φT4
8
11: φT256
11: φT16
TMRA2 source clock selection
00
Do not set
01
φT1 (Prescaler)
10
φT4 (Prescaler)
11
φT16 (Prescaler)
TMRA3 source clock selection
TA23MOD
<TA23M1:0> ≠ 01
Comparator output from
00
TMRA2
01
φT1
10
φT16
11
φT256
TA23MOD
<TA23M1:0> = 01
Overflow output from
TMRA2
(16-bit timer mode)
PWM cycle selection
00
Reserved
01
2 × source clock
10
2 × source clock
11
2 × source clock
6
7
8
TMRA23 operation mode selection
00
Two 8-bit timers
01
16-bit timer
10
8-bit PPG
11
8-bit PWM (TMRA0), 8-bit timer (TMRA3)
Figure 3.8.8 TMRA Registers
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TMRA45 Mode Register
TA45MOD Bit symbol
(0114H)
7
6
5
4
3
2
1
0
TA45M1
TA45M0
PWM41
PWM40
TA5CLK1
TA5CLK0
TA4CLK1
TA4CLK0
0
0
0
0
0
0
0
0
Read/Write
After reset
Function
R/W
Operation mode
PWM cycle
Source clock for TMRA5
Source clock for TMRA4
00: 8-bit timer mode
00: Reserved
01: 16-bit timer mode
01: 2
10: 8-bit PPG mode
10: 2
11: 8-bit PWM mode
11: 2
00: TA4TRG
00: TA4IN pin
6
01: φT1
01: φT1
7
10: φT16
10: φT4
8
11: φT256
11: φT16
Source clock for TMRA4
00
TA4IN (External input)
01
φT1 (Prescaler)
10
φT4 (Prescaler)
11
φT16 (Prescaler)
Source clock for TMRA5
TA45MOD
<TA45M1:0> ≠ 01
Comparator output from
00
TMRA4
01
φT1
10
φT16
11
φT256
TA45MOD
<TA45M1:0> = 01
Overflow output from
TMRA4
(16-bit timer mode)
PWM cycle
00
Reserved
01
2 × source clock
10
2 × source clock
11
2 × source clock
6
7
8
Operation mode for TMRA45
00
Two 8-bit timers
01
16-bit timer
10
8-bit PPG
11
8-bit PWM (TMRA4), 8-bit timer (TMRA5)
Figure 3.8.9 TMRA Registers
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TMRA1 Flip-flop Control Register
7
TA1FFCR
Bit symbol
(0105H)
Read/Write
6
5
4
3
TA1FFC1
1
TA1FFC0
TA1FFIE
R/W
After reset
Read-
2
1
Function
0
TA1FFIS
R/W
1
0
0
00: Invert TA1FF
TA1FF
TA1FF
modify-write
01: Set TA1FF
control for
inversion
instructions
10: Clear TA1FF
inversion
select
are
11: Don’t care
0: Disable
0: TMRA0
1: Enable
1: TMRA1
prohibited.
Inverse signal for timer flip-flop 1 (TA1FF)
(Don’t care except in 8-bit timer mode)
0
Inversion by TMRA0
1
Inversion by TMRA1
Inversion of TA1FF
0
Disabled
1
Enabled
Control of TA1FF
00
Inverts the value of TA1FF
01
Sets TA1FF to 1
10
Clears TA1FF to 0
11
Don’t care
Figure 3.8.10 TMRA Registers
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TMRA3 Flip-flop Control Register
7
TA3FFCR
Bit symbol
(010DH)
Read/Write
6
5
4
3
TA3FFC1
1
TA3FFC0
TA3FFIE
R/W
After reset
Read-
2
1
Function
0
TA3FFIS
R/W
1
0
0
00: Invert TA3FF
TA3FF
TA3FF
modify-write
01: Set TA3FF
control for
inversion
instructions
10: Clear TA3FF
inversion
select
are
11: Don’t care
0: Disable
0: TMRA2
1: Enable
1: TMRA3
prohibited.
Inverse signal for timer flip-flop 3 (TA3FF)
(Don’t care except in 8-bit timer mode)
0
Inversion by TMRA2
1
Inversion by TMRA3
Inversion of TA3FF
0
Disabled
1
Enabled
Control of TA3FF
00
Inverts the value of TA3FF
01
Sets TA3FF to 1
10
Clears TA3FF to 0
11
Don’t care
Figure 3.8.11 TMRA Registers
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TMRA5 Flip-flop Control Register
7
TA5FFCR
Bit symbol
(0115H)
Read/Write
6
5
4
3
TA5FFC1
1
TA5FFC0
TA5FFIE
R/W
After reset
Read-
2
1
Function
0
TA5FFIS
R/W
1
0
0
00: Invert TA5FF
TA5FF
TA5FF
modify-write
01: Set TA5FF
control for
inversion
instructions
10: Clear TA5FF
inversion
select
are
11: Don’t care
0: Disable
0: TMRA4
1: Enable
1: TMRA5
prohibited.
Inverse signal for timer flip-flop 5 (TA5FF)
(Don’t care except in 8-bit timer mode)
0
Inversion by TMRA4
1
Inversion by TMRA5
Inversion of TA5FF
0
Disabled
1
Enabled
Control of TA5FF
00
Inverts the value of TA5FF
01
Sets TA5FF to 1
10
Clears TA5FF to 0
11
Don’t care
Figure 3.8.12 TMRA Registers
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TMRA register
7
6
5
4
3
TA0REG
bit Symbol
−
(0102H)
Read/Write
W
After reset
Undefined
TA1REG
bit Symbol
−
(0103H)
Read/Write
W
After reset
Undefined
bit Symbol
−
TA2REG
(010AH)
Read/Write
W
After reset
Undefined
TA3REG
bit Symbol
−
(010BH)
Read/Write
W
After reset
Undefined
TA4REG
bit Symbol
−
(0112H)
Read/Write
W
After reset
Undefined
TA5REG
bit Symbol
−
(0113H)
Read/Write
W
After reset
Undefined
2
1
0
Note: The above registers are prohibited read-modify-write instruction.
Figure 3.8.13 TMRA Registers
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3.8.4
Operation in Each Mode
(1) 8-bit timer mode
Both TMRA0 and TMRA1 can be used independently as 8-bit interval timers.
a.
Generating interrupts at a fixed interval (Using TMRA1)
To generate interrupts at constant intervals using TMRA1 (INTTA1), first stop
TMRA1 then set the operation mode, input clock and a cycle to TA01MOD and
TA1REG register, respectively. Then, enable the interrupt INTTA1 and start
TMRA1 counting.
Example: To generate an INTTA1 interrupt every 8.8 μs at fc = 36 MHz, set each register
as follows:
* Clock state
System clock:
High frequency (fc)
Prescaler clock: fFPH
MSB
TA01RUN
←
7
–
TA01MOD
←
0
LSB
6
–
5
X
4
X
3
–
2
–
1
0
0
–
0
X
X
1
0
X
X
Stop TMRA1 and clear it to 0.
Select 8-bit timer mode and select φT1
((2 /fc) μs at fc = 36 MHz) as the input clock.
3
TA1REG
←
0
0
1
0
1
0
0
0
Set TA1REG to 8.8 μs ÷ φT1 (2 /fc) = 40 = 28H
INTETA01
←
X
1
0
1
–
–
–
–
Enable INTTA1 and set it to level 5.
TA01RUN
←
–
X
X
X
–
1
1
–
Start TMRA1 counting.
3
X: Don’t care, −: No change
Select the input clock using Table 3.8.4
Note:
The input clocks for TMRA0 and TMRA1 differ as follows:
TMRA0: Uses TA0IN input and can be selected from φT1, φT4, or φT16.
TMRA1: Match output of TMRA0 and can be selected from φT1, φT16, φT256.
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b.
Generating a 50% duty ratio square wave pulse
The state of the timer flip-flop (TA1FF) is inverted at constant intervals and its
status output via the timer output pin (TA1OUT).
Example: To output a 1.32 μs square wave pulse from the TA1OUT pin at fc = 36 MHz, use the
following procedure to make the appropriate register settings. This example uses
TMRA1; however, either TMRA0 or TMRA1 may be used.
* Clock state
System clock:
High frequency (fc)
Clock gear:
1 (fc)
Prescaler clock: fFPH
TA01RUN
←
7
–
6
X
5
X
4
X
3
–
2
–
1
0
0
–
TA01MOD
←
0
0
X
X
0
1
–
–
Stop TMRA1 and clear it to 0.
Select 8-bit timer mode and select φT1
((2 /fc)s at fc = 36 MHz) as the input clock.
3
TA1REG
←
0
0
0
0
0
0
1
1
Set the timer register to 1.32 μs ÷ φT1(2 /fc)s ÷ 2 = 3
TA1FFCR
←
X
X
X
X
1
0
1
1
Clear TA1FF to 0 and set it to invert on the match detect
P7CR
←
X
X
–
–
–
–
1
–
P7FC
←
X
X
–
–
X
–
1
X
TA01RUN
←
–
X
X
X
–
1
1
–
3
signal from TMRA1.
Set P71 to function as the TA1OUT pin.
Start TMRA1 counting.
X: Don’t care, −: No change
φT1
TA01RUN
<TA1RUN>
Bit7 to 2
Up counter
Bit1
Bit0
0
1
2
3
0
1
2
3
0
1
2
3
0
Comparator
timing
Comparator output
(Match detect)
INTTA1
UC1 clear
TA1FF
TA1OUT
0.67μs at fc = 36 MHz
Figure 3.8.14 Square Wave Output Timing Chart (50% duty)
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c.
Making TMRA1 count up on the match signal from the TMRA0 comparator
Select 8-bit timer mode and set the comparator output from TMRA0 to be the input
clock to TMRA1.
Comparator output
(TMRA0 match)
TMRA0 up counter
(when TA0REG = 5)
1
TMRA1 up counter
(when TA1REG = 2)
2
3
4
5
1
2
1
3
4
5
1
2
2
3
1
TMRA1 match output
Figure 3.8.15 TMRA1 Count Up on Signal from TMRA0
(2) 16-bit timer mode
A 16-bit interval timer is configured by pairing the two 8-bit timers TMRA0 and
TMRA1.
To make a 16-bit interval timer in which TMRA0 and TMRA1 are cascaded together,
set TA01MOD<TA01M1:0> to 01.
In 16-bit timer mode, the overflow output from TMRA0 is used as the input clock for
TMRA1, regardless of the value set in TA01MOD<TA01CLK1:0>. Table 3.8.4 shows
the relationship between the timer (Interrupt) cycle and the input clock selection.
Setting example: To generate an INTTA1 interrupt every 0.22 seconds at fc = 36 MHz, set the
timer registers TA0REG and TA1REG as follows:
* Clock state
System clock: High frequency (fc)
Clock gear:
1 (fc)
Prescaler clock: fFPH
If φT16 ((27/fc)s at 36 MHz) is used as the input clock for counting, set the following value in
the registers:
0.22 s ÷ (27/fc)s ≈ 62500 = F424H
(e.g., set TA1REG to F4H and TA0REG to 24H).
As a result, INTTA1 interrupt can be generated every 0.23 [s].
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The comparator match signal is output from TMRA0 each time the up counter UC0
matches TA0REG, where the up counter UC0 is not be cleared.
In the case of the TMRA1 comparator, the match detect signal is output on each
comparator pulse on which the values in the up counter UC1 and TA1REG match.
When the match detect signal is output simultaneously from both the comparators
TMRA0 and TMRA1, the up counters UC0 and UC1 are cleared to 0 and the interrupt
INTTA1 is generated. Also, if inversion is enabled, the value of the timer flip-flop
TA1FF is inverted.
Example: When TA1REG = 04H and TA0REG = 80H
Value of up counter
(UC1, UC0)
0080H
0180H
0280H
0380H
0480H
0080H
TMRA0 comparator match
detect signal
TMRA0 comparator match
detect signal
INTTA0
INTTA1
TA1OUT
Inversion
Figure 3.8.16 Timer Output by 16-Bit Timer Mode
(3) 8-bit PPG (Programmable pulse generation) output mode
Square wave pulses can be generated at any frequency and duty ratio by TMRA0.
The output pulses may be active-low or active-high. In this mode TMRA1 cannot be
used.
TMRA0 outputs pulses on the TA1OUT pin (which can also be used as P71).
tH
tL
When <TA1FFC1:0>=”10”
t
tL
tH
When <TA1FFC1:0>=”01”
t
Example when <TA1FFC1:0>=”01”
TA0REG and UC0 match
(Interrupt INTTA0)
TA1REG and UC0 match
(Interruput INTTA1)
TA1OUT
TA0REG
TA1REG
Figure 3.8.17 8-Bit PPG Output Waveforms
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In this mode a programmable square wave is generated by inverting the timer
output each time the 8-bit up counter (UC0) matches the value in one of the timer
registers TA0REG or TA1REG.
The value set in TA0REG must be smaller than the value set in TA1REG.
Although the up counter for TMRA1 (UC1) is not used in this mode,
TA01RUN<TA1RUN> should be set to 1 so that UC1 is set for counting.
Figure 3.8.18 shows a block diagram representing this mode.
TA1OUT
TA0IN
φT1
φT4
φT16
TA01RUN<TA0RUN>
Selector
8-bit
up counter (UC 0)
TA1FF
TA1FFCR<TA1FFIE>
Inversion
TA01MOD<TA0CLK1:0>
INTTA0
Comparator
Selector
Comparator
INTTA1
TA0REG
Shift trigger
TA0REG-WR
Register buffer
TA1REG
TA01RUN<TA0RDE>
Internal data bus
Figure 3.8.18 Block Diagram of 8-Bit PPG Output Mode
If the TA0REG double buffer is enabled in this mode, the value of the register buffer
will be shifted into TA0REG each time TA1REG matches UC0.
Use of the double buffer facilitates the handling of low-duty waves (when duty is
varied).
Match with TA0REG
and up counter
(Up counter = Q1)
(Up countner = Q2)
Match with TA1REG
TA0REG
(Value to be compared)
Register buffer
Shift from register buffer
Q2
Q1
Q2
Q3
TA0REG (Register buffer)
write
Figure 3.8.19 Operation of Register Buffer
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Example: To generate 1/4 duty 50kHz pulses (at fc = 36 MHz):
20 μs
* Clock state
System clock:
Clock gear:
Prescaler clock:
High frequency (fc)
1 (fc)
fFPH
Calculate the value which should be set in the timer register.
To obtain a frequency of 50kHz, the pulse cycle t should be:
t = 1/50 kHz = 20 μs
φT1 = (23/fc)s (at 36 MHz);
20 μs ÷ (23/fc)s ≈ 90
Therefore set TA1REG to 90 (5AH)
The duty is to be set to 1/4: t × 1/4 = 20 μs × 1/4 = 5 μs
5 μs ÷ (23/fc)s ≈ 22
Therefore, set TA0REG = 22 = 16H.
TA01RUN
TA01MOD
TA0REG
TA1REG
TA1FFCR
P7CR
P7FC
TA01RUN
←
←
←
←
←
←
←
←
7
0
6
X
5
X
4
X
3
–
2
0
1
0
0
0
1
0
X
X
X
X
0
1
0
0
0
1
0
1
1
0
0
1
0
1
1
0
1
0
X
X
X
X
0
1
1
X
X
X
–
–
–
–
1
–
X
X
–
–
X
–
1
X
1
X
X
X
–
1
1
1
Stop TMRA0 and TMRA01 and clear it to 0.
Set the 8-bit PPG mode, and select φT1 as input clock.
Write 16H.
Write 5AH.
Set TA1FF, enabling both inversion and the double buffer.
10 generates a negative logic pulse.
Set P71 as the TA1OUT pin.
Start TMRA0 and TMRA01 counting.
X: Don’t care, −: No change
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2006-03-15
TMP91C829
(4) 8-bit PWM output mode
This mode is only valid for TMRA0. In this mode, a PWM pulse with the maximum
resolution of 8 bits can be output.
When TMRA0 is used the PWM pulse is output on the TA1OUT pin (which is also
used as P71). TMRA1 can also be used as an 8-bit timer.
The timer output is inverted when the up counter (UC0) matches the value set in the
timer register TA0REG or when 2n counter overflow occurs (n = 6, 7, or 8 as specified by
TA01MOD<PWM01:00>). The up counter UC0 is cleared when 2ncounter overflow
occurs.
The following conditions must be satisfied before this PWM mode can be used.
Value set in TA0REG < Value set for 2n counter overflow
Value set in TA0REG ≠ 0
TA0REG and
UC0 match
n
2
overflow
(INTTA0 interrupt)
TA1OUT
tPWM
(PWM cycle)
Figure 3.8.20 8-Bit PWM Waveforms
Figure 3.8.21 shows a block diagram representing this mode.
TA01RUN<TA0RUN>
TA0IN
φT1
φT4
φT16
8-bit up counter
(UC 0)
Selector
Clear
TAFF1
control
TA1FFCR
<TA1FFIE>
Invert
n
2
overflow
TA01MOD<TA0CLK1:0>
TA1OUT
TA01MOD
<PWM01:00>
Overflow
Comparator
INTTA0
TA0REG
Selector
Shift trigger
TA0REG-WR
Register buffer
TA01RUN<TA0RDE>
Internal data bus
Figure 3.8.21 Block Diagram of 8-Bit PWM Mode
91C829-100
2006-03-15
TMP91C829
In this mode the value of the register buffer will be shifted into TA0REG if 2n
overflow is detected when the TA0REG double buffer is enabled.
Use of the double buffer facilitates the handling of low duty ratio waves.
Match with TA0REG
Up counter = Q1
Up counter = Q2
n
2 overflow
Shift into TA0REG
Q2
TA0REG
Q1
(Value to be compared)
Register buffer
Q3
Q2
TA0REG (Register buffer)
write
Figure 3.8.22 Register Buffer Operation
Example: To output the following PWM waves on the TA1OUT pin at fc = 36 MHz:
16.0 μs
28.4 μs
* Clock state
System clock: High frequency (fc)
Clock gear:
1 (fc)
Prescaler clock: fFPH
To achieve a 28.4 μs PWM cycle by setting φT1 to (23/fc)s (at fc = 36 MHz):
28.4 μs ÷ (23/fc)s ≈ 128 = 2n
Therefore n should be set to 7.
Since the low-level period is 16.0 μs when φT1 = (23/fc)s,
set the following value for TA0REG:
16.0 μs ÷ (23/fc)s ≈ 72 = 48H
MSB
TA01RUN
TA01MOD
TA0REG
TA1FFCR
P7CR
P7FC
TA01RUN
LSB
0
0
1
7
–
1
6
X
1
5
X
1
4
X
0
3
–
–
2
–
–
1
–
0
←
←
0
1
0
0
1
0
0
0
X
X
X
X
1
0
1
X
←
←
←
X
X
–
–
–
–
1
–
X
X
–
–
X
–
1
X
1
X
X
X
–
1
1
1
←
←
Stop TMRA0 and clear it to 0.
7
Select 8-bit PWM mode (Cycle: 2 ) and select φT1 as the
input clock.
Write 48H.
Clear TA1FF to 0, enable the inversion and double buffer.
Set P71 and the TA1OUT pin.
Start TMRA0 counting.
X: Don’t care, −: No change
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TMP91C829
Table 3.8.3 PWM Cycle
at fc = 36 MHz
Select Prescaler
Clock
<PRCK1:0>
00
(fFPH)
10
(fc/16 clock)
PWM Cycle
Gear Value
<GEAR2:0>
2
6
28
2
φT1
φT4
φT16
φT1
φT4
φT16
φT1
φT4
φT16
000 (fc)
14.2 μs
56.8 μs
227 μs
28.4 μs
113μs
455 μs
56.8 μs
227 μs
910 μs
001 (fc/2)
28.4 μs
113 μs
455 μs
56.8 μs
227 μs
910 μs
113 μs
455 μs
1820 μs
10 (fc/4)
56.8 μs
227 μs
910 μs
113 μs
455 μs
1820 μs
227 μs
910 μs
3640 μs
011 (fc/8)
113 μs
455 μs
1820 μs
227 μs
910 μs
3640 μs
455 μs
1820 μs
7281 μs
00 (fc/16)
227 μs
910 μs
3640 μs
455 μs
1820 μs 7281 μs
910 μs
3640 μs 14563 μs
XXX
227 μs
910 μs
3640 μs
455 μs
1820 μs 7281 μs
910 μs
3640 μs 14563 μs
XXX: Don’t care
(5) Settings for each mode
Table 3.8.4 shows the SFR settings for each mode.
Table 3.8.4 Timer Mode Setting Registers
Register Name
TA01MOD
TA1FFCR
<Bit Symbol>
<TA01M1:0>
<PWM01:00>
<TA1CLK1:0>
<TA0CLK1:0>
TA1FFIS
Function
Timer Mode
PWM Cycle
Upper Timer
Input Clock
Lower Timer
Input Clock
Timer F/F Invert
Signal Select
8-bit timer × 2 channels
00
−
Lower timer match
φT1, φT16, φT256
(00, 01, 10, 11)
φT1, φT4, φT16
(00, 01, 10, 11)
External clock
0: Lower timer output
1: Upper timer output
External clock
16-bit timer mode
01
−
−
φT1, φT4, φT16
(00, 01, 10, 11)
8-bit PPG × 1 channel
10
−
−
φT1, φT4, φT16
(00, 01, 10, 11)
8-bit PWM × 1 channel
11
2 ,2 ,2
(01, 10, 11)
−
φT1, φT4, φT16
(00, 01, 10, 11)
−
8-bit timer × 1 channel
11
−
φT1, φT16, φT256
(01, 10, 11)
−
Output disabled
−
External clock
6
7
−
External clock
8
−: Don’t care
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TMP91C829
3.9
16-Bit Timer/Event Counters (TMRB)
The TMP91C829 incorporates multifunctional 16-bit timer/event counter (TMRB0) which
has the following operation modes:
•
16-bit interval timer mode
•
16-bit event counter mode
•
16-bit programmable pulse generation (PPG) mode
The timer/event counter channel consists of a 16-bit up counter, two 16-bit timer registers
(One of them with a double-buffer structure), two 16-bit capture registers, two comparators, a
capture input controller, a timer flip-flop and a control circuit.
The timer/event counter is controlled by an 11-byte control SFR.
This chapter consists of the following items:
Table 3.9.1 Differences between TMRB0
Channel
TMRB0
Spec
External clock/capture trigger
External
Pins
TB0IN0 (Also used as P93)
input pins
TB0IN1 (Also used as P94)
Timer flip-flop output pins
TB0OUT0 (Also used as P95)
Timer run register
TB0RUN (0180H)
TB0OUT1 (Also used as P96)
Timer mode register
TB0MOD (0182H)
Timer flip-flop control register
TB0FFCR (0183H)
TB0RG0L (0188H)
SFR
TB0RG0H (0189H)
Timer register
TB0RG1L (018AH)
(address)
TB0RG1H (018BH)
TB0CP0L (018CH)
Capture register
TB0CP0H (018DH)
TB0CP1L (018EH)
TB0CP1H (018FH)
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2006-03-15
TA1OUT
(from TMRA01)
TB0IN0
TB0IN1
Prescaler clock: φT0
φT4
8
Capture,
external INT
input control
4
TB0MOD
<TB0CP0I>
φT16
91C829-104
TB0RUN
<TB0RDE>
Internal data bus
Register buffer 0
16-bit timer register
TB0RG0H/L
16-bit comparator
(CP0)
TB0MOD<TB0CLK1:0>
Match
detection
Intenal data bus
16-bit time register
TB0RG1H/L
TB0FF1
TB0FF0
Match detection
Timer
flip-flop
control
Timer
flip-flop
Register 0 Register 1
INTTB00 INTTB01
16-bit comparator
(CP1)
TB0RUN<TB0RUN>
TB0MOD<TB0CLE>
Caputure register 1
TB0CP1H/L
Internal data bus
16-bit up counter
(UC0)
Capture register 0
TB0CP0H/L
Selector
TB0MOD
Count
<TB0CPM1:0> φT1
clock
φT4
φT16
φT1
2
Run/
clear TB0RUN
16 32
<TB0PRUN>
Internal data bus
Over flow INT
INTTBOF1
TB0OUT1
TB0OUT0
Timer flip-flop
output
3.9.1
INT output
TMP91C829
Block Diagrams
Figure 3.9.1 Block Diagram of TMRB0
2006-03-15
TMP91C829
3.9.2
Operation of Each Block
(1) Prescaler
The 5-bit prescaler generates the source clock for TMRB0. The prescaler clock (φT0)
is divided clock (divided by 4) from selected clock by the register SYSCR0<PRCK1:0> of
clock gear.
This prescaler can be started or stopped using TB0RUN<TB0RUN>. Counting starts
when <TB0RUN> is set to 1; the prescaler is cleared to zero and stops operation when
<TB0RUN> is set to 0.
Table 3.9.2 Prescaler Clock Resolution
at fc = 36 MHz
Prescaler Clock Resolution
Prescaler Clock Selection Clock Gear Value
<PRCK1:0>
<GEAR2:0>
00
(fFPH)
10
(fc/16 clock)
φT1
φT4
φT16
000 (fc)
2 /fc (0.2 μs)
2 /fc (0.9 μs)
2 /fc
001 (fc/2)
2 /fc (0.4 μs)
2 /fc (1.8 μs)
2 /fc
010 (fc/4)
2 /fc (0.9 μs)
2 /fc (3.6 μs)
2 /fc (14.2 μs)
011 (fc/8)
2 /fc (1.8 μs)
2 /fc (7.1 μs)
2 /fc (28.4 μs)
100 (fc/16)
2 /fc (3.6 μs)
2 /fc (14.2 μs)
2 /fc (56.9 μs)
XXX
2 /fc (3.6 μs)
2 /fc (14.2 μs)
2 /fc (56.9 μs)
3
4
5
6
7
7
5
6
7
8
9
9
7
(3.6 μs)
8
(7.1 μs)
9
10
11
11
xxx: Don’t care
(2) Up counter (UC0)
UC0 is a 16-bit binary counter which counts up pulses input from the clock specified
by TB0MOD<TB0CLK1:0>.
Any one of the prescaler internal clocks φT1, φTB0 and φT16 or an external clock
input via the TB0IN0 pin can be selected as the input clock. Counting or stopping and
clearing of the counter is controlled by TB0RUN<TB0RUN>.
When clearing is enabled, the up counter UC0 will be cleared to zero each time its
value matches the value in the timer register TB0RG1H/L. Clearing can be enabled or
disabled using TB0MOD<TB0CLE>.
If clearing is disabled, the counter operates as a free-running counter.
A timer overflow interrupt (INTTBOF0) is generated when UC0 overflow occurs.
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TMP91C829
(3) Timer registers (TB0RG0H/L and TB0RG1H/L)
These two 16-bit registers are used to set the interval time. When the value in the up
counter UC0 matches the value set in this timer register, the comparator match detect
signal will go active.
Setting data for both upper and lower registers is always needed. For example,
either using 2-byte data transfer instruction or using 1 byte date transfer instruction
twice for lower 8 bits and upper 8 bits in order.
The TB0RG0 timer register has a double-buffer structure, which is paired with
register buffer. The value set in TB0RUN<TB0RDE> determines whether the
double-buffer structure is enabled or disabled: it is disabled when <TB0RDE> = 0, and
enabled when <TB0RDE> = 1.
When the double buffer is enabled, data is transferred from the register buffer to the
timer register when the values in the up counter (UC0) and the timer register TB0RG1
match.
After a reset, TB0RG0 and TB0RG1 are undefined. If the 16-bit timer is to be used
after a reset, data should be written to it beforehand.
On a reset TB0RUN<TB0RDE> is initialized to 0, disabling the double buffer. To use
the double buffer, write data to the timer register, set <TB0RDE> to 1, then write data
to the register buffer as shown below.
TB0RG0 and the register buffer both have the same memory addresses (000188H
and 000189H) allocated to them. If <TB0RDE> = 0, the value is written to both the
timer register and the register buffer. If <TB0RDE> = 1, the value is written to the
register buffer only.
The addresses of the timer registers are as follows:
TMRB0
TB0RG0
TB0RG1
Upper 8 bits
(TB0RG0H)
Lower 8 bits
(TB0RG0L)
Upper 8 bits
(TB0RG1H)
Lower 8 bits
(TB0RG1L)
000189H
000188H
00018BH
00018AH
The timer registers are write-only registers and thus cannot be read.
(4) Capture registers (TB0CP0H/L and TB0CP1H/L)
These 16-bit registers are used to latch the values in the up counter UC0.
Data in the capture registers should be read all 16 bits. For example, using a 2-byte
data load instruction or two 1-byte data load instructions. The least significant byte is
read first, followed by the most significant byte.
The addresses of the capture registers are as follows:
TMRB0
TB0CP0
TB0CP1
Upper 8 bits
(TB0CP0H)
Lower 8 bits
(TB0CP0L)
Upper 8 bits
(TB0CP1H)
Lower 8 bits
(TB0CP1L)
00018DH
00018CH
00018FH
00018EH
The capture registers are read-only registers and thus cannot be written to.
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TMP91C829
(5) Capture input control
This circuit controls the timing to latch the value of up counter UC0 into TB0CP0,
TB0CP1. The latch timing for the capture register is determined by
TB0MOD<TB0CPM1:0>.
In addition, the value in the up counter can be loaded into a capture register by
software. Whenever 0 is written to TB0MOD<TB0CP0I>, the current value in the up
counter is loaded into capture register TB0CP0. It is necessary to keep the prescaler in
run mode (e.g., TB0RUN<TB0PRUN> must be held at a value of 1).
Note:
As described above, whenever 0 is written to TB0MOD<TB0CP0I>, the current
value in the up counter is loaded into capture register TB0CP0. However, note that
the current value in the up counter is also loaded into capture register TB0CP0
when 1 is written to TB0MOD<TB0CP0I> while this bit is holding 0.
Note
Write to TBnMOD
register
“0” WR
“0” WR
“1” WR
“1” WR
Capture
Capture
Capture
NOP
TBnMOD
<TBnCP0I>
Capture
operation
(6) Comparators (CP0 and CP1)
CP0 and CP1 are 16-bit comparators which compare the value in the up counter UC0
with the value set in TB0RG0 or TB0RG1 respectively, in order to detect a match. If a
match is detected, the comparator generates an interrupt (INTTB00 or INTTB01
respectively).
(7) Timer flip-flops (TB0FF0 and TB0FF1)
These flip-flops are inverted by the match detect signals from the comparators and
the latch signals to the capture registers. Inversion can be enabled and disabled for
each element using TB0FFCR<TB0C1T1, TB0C0T1, TB0E1T1, TB0E0T1>. After a
reset the value of TB0FF0 is undefined. If 00 is written to TB0FFCR<TB0FF0C1:0> or
<TB0FF1C1:0>, TB0FF0 will be inverted. If 01 is written to the capture registers, the
value of TB0FF0 will be set to 1. If 10 is written to the capture registers, the value of
TB0FF0 will be set to 0. The values of TB0FF0 and TB0FF1 can be output via the timer
output pins TB0OUT0 (which is shared with P95) and TB0OUT1 (which is shared with
P96). Timer output should be specified using the port 9 function register.
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TMP91C829
3.9.3
SFRs
TMRB0 Run Register
TB0RUN Bit symbol
(0180H) Read/Write
After reset
Function
7
6
3
2
TB0RDE
−
I2TB0
TB0PRUN
TB0RUN
R/W
R/W
R/W
R/W
R/W
0
0
0
5
4
0
0
1
0
Double
Always write
IDLE2
16-bit timer run/stop control
buffer
“0”.
0: Stop
0: Stop and clear
1: Operate
1: Run (Count up)
0: Disable
1: Enable
Count operation
0
Stop and clear
1
Count
I2TB0:
Operation during IDLE2 mode
TB0PRUN: Operation of prescaler
Note: The 1, 4 and 5 of TB0RUN are read as undefined value.
TB0RUN: Operation of TMRB0
Figure 3.9.2 Register for TMRB
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2006-03-15
TMP91C829
TMRB0 Run Register
7
TB0MOD
Bit symbol
(0182H)
Read/Write
After reset
Function
TB0CT1
6
5
4
3
2
1
0
TB0ET1
TB0CP0I
TB0CPM1
TB0CPM0
TB0CLE
TB0CLK1
TB0CLK0
0
0
W*
R/W
0
0
1
R/W
0
0
0
TB0FF1 inversion
Execute
Capture timing
Control up
TMRB0 source clock
Read
0: Disable trigger
software
00: Disable
counter
00: TB0IN0 pin
-modify
1: Enable trigger
capture
01: TB0IN0 ↑ TB0IN1 ↑
0: Disable
01: φT1
-write
clearing
Invert when Invert when 0: Execute 10: TB0IN0 ↑ TB0IN1 ↓
1: Undefined 11: TA1OUT ↑ TA1OUT ↓ 1: Enable
the UC
the UC
10: φT4
instruction
is prohibited
11: φT16
clearing
value is
value
captured to
matches the
TB0CP1.
value in
TB0RG1.
TMRB0 source clock
00
TB0IN0 pin
01
φT1
10
φT4
11
φT16
Up counter clear control
0
Disable
1
TB0RG1 clearing on match with TB0RG1.
Capture
Capture control
00
01
10
11
Disable
CAP0 at TB0IN0 rising
CAP1 at TB0IN1 rising
CAP0 at TB0IN0 rising
CAP1 at TB0IN1 rising
CAP0 at TA1OUT rising
CAP1 at TA1OUT falling
Software capture
Note:
0
The value in the up counter is captured to TB0CP0.
1
Undefined (Note)
Whenever writing “0” to TB0MOD<TB0CP0I> bit, present value of up counter is received to capture register
TB0CP0. But write “1” to TB0MOD<TB0CP0I> in condition of written “0” to TB0MOD<TB0CP0I> bit,
present value of up counter is received to capture register TB0CP0. Therefore you must to regard.
Figure 3.9.3 Register for TMRB
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2006-03-15
TMP91C829
TMRB0 Flip-flop Control Register
7
TB0FFCR Bit symbol
(0183H) Read/Write
After reset
Function
TB0FF1C1
6
5
4
TB0FF1C0
TB0C1T1
TB0C0T1
W*
0
3
2
1
TB0E1T1
TB0E0T1
TB0FF0C1
1
0
TB0FF0C0
W*
R/W
0
0
0
0
0
0
Control TB0FF1
TB0FF0 inversion trigger
Control TB0FF0
Read
00: Invert
0: Disable trigger
00: Invert
-modify
01: Set
1: Enable trigger
01: Set
-write
10: Clear
Invert when Invert when Invert when Invert when
10: Clear
instruction
11: Don’t care
* Always read as “11”.
the UC value the UC value the UC value the UC value 11: Don’t care
is loaded in is loaded in matches the matches the * Always read as “11”.
is
prohibited
to TB0CP1. to TB0CP0. value in
TB0RG1.
value in
TB0RG0.
TB0FF0 control
Invert
00
01
Set to 11
10
Clear to 0
11
Don’t care
Inverted when the UC value is loaded in to TB0CP1.
0
Disable trigger
1
Enable trigger
Inverted when the UC value is loaded in to TB0CP0.
0
Disable trigger
1
Enable trigger
Inverted when the UC value matches the valued in TB0RG1.
0
Disable trigger
1
Enable trigger
Inverted when the UC value matches the valued in TB0RG0.
0
Disable trigger
1
Enable trigger
Figure 3.9.4 Register for TMRB
91C829-110
2006-03-15
TMP91C829
7
TB0RG0L
(0188H)
bit Symbol
6
TMRB0 Register
5
4
3
2
1
0
–
Read/Write
W
After reset
Undefined
TB0RG0H
bit Symbol
–
(0189H)
Read/Write
W
After reset
Undefined
TB0RG1L
bit Symbol
–
(018AH)
Read/Write
W
After reset
Undefined
TB0RG1H
bit Symbol
–
(018BH)
Read/Write
W
After reset
Undefined
Note: The above registers are prohibited read-modify-write instruction.
Figure 3.9.5 TMRB Registers
91C829-111
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TMP91C829
3.9.4
Operation in Each Mode
(1) 16-bit interval timer mode
Generating interrupts at fixed intervals
In this example, the interrupt INTTB01 is set to be generated at fixed intervals. The
interval time is set in the timer register TB0RG1.
TB0RUN
←
7
0
6
0
5
X
4
X
3
–
2
0
1
X
0
0
Stop TMRB0.
INTETB01
←
X
1
0
0
X
0
0
0
Enable INTTB01 and set interrupt level 4. Disable
TB0FFCR
←
1
1
0
0
0
0
1
1
TB0MOD
←
0
0
1
0
0
1
* *
(** = 01, 10, 11)
Select internal clock for input and
TB0RG1
←
*
*
*
*
*
*
*
*
Set the interval time (16 bits).
←
*
0
*
0
*
X
*
X
*
–
*
1
*
X
*
1
Start TMRB0.
INTTB00.
TB0RUN
←
Disable the trigger.
disable the capture function.
X: Don’t care, −: No change
(2) 16-bit event counter mode
As described above, in 16-bit timer mode, if the external clock (TB0IN0 pin input) is
selected as the input clock, the timer can be used as an event counter. To read the
value of the counter, first perform software capture once, then read the captured value.
TB0RUN
←
P8CR
INTETB01
←
7
0
6
0
5
X
4
X
3
–
2
0
1
X
0
0
Stop TMRB0.
–
–
–
–
0
–
–
–
Set P93 input mode.
X
1
0
0
X
0
0
0
Enable INTTB01 and set interrupt level 4. Disable
INTTB00.
TB0FFCR
←
1
1
0
0
0
0
1
1
Disable the trigger.
TB0MOD
←
0
0
1
0
0
1
0
0
Select TB0IN0 as the input clock.
TB0RG1
←
*
*
*
*
*
*
*
*
Set the number of counts (16 bits).
←
*
0
*
0
*
X
*
X
*
–
*
1
*
X
*
1
Start TMRB0.
TB0RUN
←
X: Don’t care, −: No change
When the timer is used as an event counter, set the prescaler in run mode
(e.g., with TB0RUN<TB0PRUN> = 1).
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(3) 16-bit programmable pulse generation (PPG) output mode
Square wave pulses can be generated at any frequency and duty ratio. The output
pulse may be either low-active or high-active.
The PPG mode is obtained by inversion of the timer flip-flop TB0FF0 that is to be
enabled by the match of the up counter UC0 with timer register TB0RG0 or TB0RG1
and to be output to TB0OUT0. In this mode the following conditions must be satisfied.
(Value set in TB0RG0) < (Value set in TB0RG1)
Match with TB0RG0
(INTTB00 inerrupt)
Match with TB0RG1
(INTTB01 interrupt)
TB0OUT0 pin
Figure 3.9.5 Programmable Pulse Generation (PPG) Output Waveforms
When the TB0RG0 double buffer is enabled in this mode, the value of register buffer
0 will be shifted into TB0RG0 at match with TB0RG1. This feature facilitates the
handling of low-duty waves.
Match with TB0RG0
Up counter = Q1
Up counter = Q2
Match with TB0RG1
TB0RG0
(Value to be compared)
Register buffer
Shift into theTB0RG1
Q1
Q2
Q2
Q3
Write into the TB0RG0
Figure 3.9.6 Operation of Register Buffer
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The following block diagram illustrates this mode.
TB0RUN<TB0RUN>
TB0OUT0 (PPG output)
Selector
TB0IN0
φT1
φT4
φT16
16-bit up counter
UC0
16-bit comparator
Match
Clear
F/F
(TB0FF0)
16-bit comparator
TB0RG0
Selector
TB0RG0-WR
Register buffer 0
TB0RG1
TB0RUN<TB0RDE>
Internal data bus
Figure 3.9.7 Block Diagram of 16-Bit Mode
The following example shows how to set 16-bit PPG output mode:
TB0RUN
←
7
0
6
0
5
X
4
X
3
–
2
0
1
X
0
0
TB0RG0
←
*
*
*
*
*
*
*
*
TB0RG1
←
TB0RUN
←
*
1
*
0
*
X
*
X
*
–
*
0
*
X
*
0
TB0FFCR
←
X
X
0
0
1
1
1
0
TB0MOD
←
0
0
1
P9CR
←
–
–
1
–
–
-
–
–
P9FC
←
X
–
1
X
X
X
X
-
TB0RUN
←
1
0
X
X
–
1
X
1
0 0 1 * *
(** = 01, 10, 11)
Disable the TB0RG0 double buffer and stop TMRB0.
Set the duty ratio (16 bits).
Set the frequency (16 bits).
Enable the TB0RG0 double buffer.
(The duty and frequency are changed on an INTTB01
interrupt.)
Set the mode to invert TB0FF0 at the match with
TB0RG0/TB0RG1. Set TB0FF0 to 0.
Select the internal clock as the input clock and disable
the capture function.
Set P95 to function as TB0OUT0.
Start TMRB0.
X: Don’t care, −: No change
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3.10 Serial Channel
TMP91C829 includes one serial I/O channel. Either UART mode (Asynchronous
transmission) or I/O interface mode (Synchronous transmission) can be selected.
•
•
I/O interface mode
Mode 0: For transmitting and receiving I/O data using the
synchronizing signal SCLK for extending I/O.
Mode 1: 7-bit data
Mode 2: 8-bit data
Mode 3: 9-bit data
UART mode
In mode 1 and mode 2 a parity bit can be added. Mode 3 has a wakeup function for making the
master controller start slave controllers via a serial link (A multi-controller system).
Figure 3.10.2 and Figure 3.10.3 are block diagrams.
Table 3.10.1 Channels 0 and 1
Channel 0
Pin Name
Channel 1
TXD0 (P80)
TXD1 (P84)
RXD0 (P81)
CTS0 /SCLK0 (P82)
RXD1 (P85)
CTS0 /SCLK1 (P86)
STS0 (P83)
STS1 (P87)
• Mode 0 (I/O interface mode)
Bit0
1
2
3
4
5
6
7
Transfer direction
• Mode 1 (7-bit UART mode)
No parity
Start
Bit0
1
2
3
4
5
6
Stop
Parity
Start
Bit0
1
2
3
4
5
6
Parity Stop
• Mode 2 (8-bit UART mode)
No parity
Start
Bit0
1
2
3
4
5
6
7
Stop
Parity
Start
Bit0
1
2
3
4
5
6
7
Parity Stop
• Mode 3 (9-bit UART mode)
Wakeup function
Start
Bit0
1
2
3
4
5
6
7
8
Stop
Start
Bit0
1
2
3
4
5
6
7
Bit8
Stop
When Bit8 = 1, address (Select code) is denoted.
When Bit8 = 0, data is denoted.
Figure 3.10.1 Data Formats
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STS0 and STS1 pins are built in port P83 and P87. STS0 and STS1 are the request signal for
the next data send to the CPU. P8CR sets port as output mode, P8FC sets STS using mode, and
bit 0 of SC0MOD1 (SC1MOD1) register sets low level. Then STS is enable to start to transfer
the data.
When SCLK signal is exactly falling edge, STS is disable.
And when it is ended to transfer 8-bits data, the STS can be set to enable and request the next
data.
In SCLK output mode, the STS function can’t be used.
RESIO
S
IOBUS
D
WR
CK
STS output
Q
SCLK
IPH
S
D
CK
Q
D
Q
CK
SCLK input
SCLK
TXD
STS
STS is H level, when SCLK is falling edge timing.
REG WR by programming
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3.10.1
Block Diagrams
Figure 3.10.2 is a block diagram representing serial channel 0.
Prescaler
2 4 8 16 32 64
φT0
φT2 φT8 φT32
Serial clock generation circuit
BR0CR
<BR0CK1:0>
TA0TRG
(from TMRA0)
BR0CR
<BR0ADDE>
Baud rate
generator
SC0MOD0
<SC1:0>
Selector
fSYS
÷2
SCLK0
Shared
with P82
SCLK0
Shared
with P82
UART
mode
Selector
Selector
Selector
φT0
φT2
φT8
φT32
BR0ADD
<BR0K3:0>
Prescaler
BR0CR
<BR0S3:0>
SIOCLK
SC0MOD0
<SM1:0>
I/O
interface mode
SC0CR
<IOC>
I/O interface Mode
Receive
counter
(Only UART ÷ 16)
INT request
INTRX0
INTTX0
SC0MOD0 Serial channel
interrupt
<WU>
control
RXDCLK
SC0MOD0
<RXE>
Transmision
counter
(Only UART ÷ 16)
TXDCLK
Receive
control
Transmission
control
SC0CR
<PE> <EVEN>
SC0MOD0
<CTSE>
Parity control
RXD0
Shared
with P81
CTS0
Shared
with P82
Receive buffer 1 (Shift register)
RB8
Receive buffer 2 (SC0BUF)
Error flag
TB8
Transmission buffer
SC0CR
<OERR><PERR><FERR>
TXD0
Shared
with P80
Internal data bus
Figure 3.10.2 Block Diagram of the Serial Channel 0
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Prescaler
2 4 8 16 32 64
φT0
φT2 φT8 φT32
Serial clock generation circuit
BR1CR
<BR0CK1:0>
TA0TRG
(from TMRA0)
BR1CR
<BR1ADDE>
Baud rate
generator
SC1MOD0
<SC1:0>
Selector
fSYS
÷2
SCLK1
Shared
with P86
SCLK1
Shared
with P86
UART
mode
Selector
Selector
Selector
φT0
φT2
φT8
φT32
BR1ADD
<BR1K3:0>
Prescaler
BR1CR
<BR1S3:0>
SIOCLK
SC1MOD0
<SM1:0>
I/O
interface mode
SC1CR
<IOC>
I/O interface Mode
Receive
counter
(Only UART ÷ 16)
INT request
INTRX1
INTTX1
SC1MOD0 Serial channel
interrupt
<WU>
control
RXDCLK
SC1MOD0
<RXE>
Transmision
counter
(Only UART ÷ 16)
TXDCLK
Receive
control
Transmission
control
SC1CR
<PE> <EVEN>
SC1MOD0
<CTSE>
Parity control
RXD1
Shared
with P85
CTS1
Shared
with P86
Receive buffer 1 (Shift register)
RB8
Receive buffer 2 (SC1BUF)
Error flag
TB8
Transmission buffer
SC1CR
<OERR><PERR><FERR>
TXD1
Shared
with P84
Internal data bus
Figure 3.10.3 Block Diagram of the Serial Channel 1
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3.10.2
Operation of Each Circuit
(1) Prescaler, prescaler clock select
There is a 6-bit prescaler for waking serial clock. The clock selected using
SYSCR<PRCK1:0> is divided by 4 and input to the prescaler as φT0. The prescaler can
be run by selecting the baud rate generator as the waking serial clock.
Table 3.10.2 shows prescaler clock resolution into the baud rate generator.
Table 3.10.2 Prescaler Clock Resolution to Baud Rate Generator
Select Prescaler Clock
<PRCK1:0>
00
(fFPH)
10
(fc/16 clock)
Gear Value
<GEAR2:0>
Prescaler Output Clock Resolution
φT0
φT2
2
2 /fc
3
2 /fc
4
2 /fc
5
2 /fc
2 /fc
5
2 /fc
6
2 /fc
7
2 /fc
8
2 /fc
8
2 /fc
000 (fc)
2 /fc
001 (fc/2)
2 /fc
010 (fc/4)
2 /fc
011 (fc/8)
2 /fc
100 (fc/16)
2 /fc
6
2 /fc
−
2 /fc
XXX
φT8
4
φT32
6
2 /fc
8
7
2 /fc
8
2 /fc
9
2 /fc
10
2 /fc
10
2 /fc
9
10
11
12
12
X: Don’t care, −: Cannot be used
The baud rate generator selects between 4 clock inputs: φT0, φT2, φT8, and φT32
among the prescaler outputs.
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(2) Baud rate generator
The baud rate generator is a circuit which generates transmission and receiving
clocks which determine the transfer rate of the serial channels.
The input clock to the baud rate generator, φT0, φT2, φT8 or φT32, is generated by
the 6-bit prescaler which is shared by the timers. One of these input clocks is selected
using the BR0CR<BR0CK1:0> field in the baud rate generator control register.
The baud rate generator includes a frequency divider, which divides the frequency
by 1 or N + (16 − K ) to 16 values, determining the transfer rate.
16
The transfer rate is determined by the settings of BR0CR<BR0ADDE, BR0S3:0>
and BR0ADD<BR0K3:0>.
•
In UART mode
(1) When BR0CR<BR0ADDE> = 0
The settings BR0ADD<BR0K3:0> are ignored. The baud rate generator divides
the selected prescaler clock by N, which is set in BR0CK<BR0S3:0> (N = 1, 2, 3 …
16).
(2) When BR0CR<BR0ADDE> = 1
The N + (16 – K)/16 division function is enabled. The baud rate generator
divides the selected prescaler clock by N + (16 – K)/16 using the value of N set in
BR0CR<BR0S3:0> (N = 2, 3 … 15) and the value of K set in BR0ADD<BR0K3:0>
(K = 1, 2, 3 … 15).
Note: If N = 1 or N = 16, the N + (16 − K)/16 division function is disabled. Set
BR0CR<BR0ADDE> to 0.
•
In I/O interface mode
The N + (16 – K)/16 division function is not available in I/O interface mode. Set
BR0CR<BR0ADDE> to 0 before dividing by N.
The method for calculating the transfer rate when the baud rate generator is
used is explained below.
•
In UART mode
Baud rate =
•
In I/O interface mode
Baud rate =
•
Input clock of baud rate generator
÷ 16
Frequency divider for baud rate generator
Input clock of baud rate generator
÷2
Frequency divider for baud rate generator
Integer divider (N divider)
For example, when the source clock frequency (fc) = 12.288 MHz, the input clock
frequency = φT2 (fc/16), the frequency divider N (BR0CR<BR0S3:0>) = 5, and
BR0CR<BR0ADDE> = 0, the baud rate in UART mode is as follows:
* Clock state
System clock:
High frequency (fc)
Clock gear:
1 (fc)
Prescaler clock: System clock
Baud rate =
fc/16
÷ 16
5
= 12.288 × 106 ÷ 16 ÷ 5 ÷ 16 = 9600 (bps)
Note: The N + (16 − K)/16 division function is disabled and setting BR0ADD<BR0K3:0>
is invalid.
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•
N + (16 − K)/16 divider (Only UART mode)
Accordingly, when the source clock frequency (fc) = 4.8 MHz, the input clock
frequency = φT0, the frequency divider N (BR0CR<BR0S3:0>) = 7, K
(BR0ADD<BR0K3:0>) = 3, and BR0CR<BR0ADDE> = 1, the baud rate in UART
mode is as follows:
* Clock state
System clock:
High frequency (fc)
Clock gear:
1 (fc)
Prescaler clock: System clock
Baud rate =
Fc/4
7 + (16 − 3)/16
÷16
= 4.8 × 106 ÷ 4 ÷ (7 + 13/16) ÷ 16 = 9600 (bps)
Table 3.10.3 and 3.10.4 show examples of UART mode transfer rates.
Additionally, the external clock input is available in the serial clock. (Serial
channels 0 and 1). The method for calculating the baud rate is explained below:
•
In UART mode
Baud rate = external clock input frequency ÷ 16
It is necessary to satisfy (External clock input cycle) ≥ 4/fc
•
In I/O interface mode
Baud rate = external clock input frequency
It is necessary to satisfy (External clock input cycle) ≥ 16/fc
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Table 3.10.3 Transfer Rate Selection (when baud rate generator is used and BR0CR<BR0ADDE> = 0)
Unit (kbps)
Input Clock
φT0
φT2
φT8
φT32
2
76.800
19.200
4.800
1.200
4
38.400
9.600
2.400
0.600
↑
8
19.200
4.800
1.200
0.300
↑
0
9.600
2.400
0.600
0.150
12.288000
5
38.400
9.600
2.400
0.600
fc [MHz]
Frequency Divider N
(BR0CR<BR0S3:0>)
9.830400
↑
↑
A
19.200
4.800
1.200
0.300
14.745600
2
115.200
28.800
7.200
1.800
↑
3
76.800
19.200
4.800
1.200
↑
6
38.400
9.600
2.400
0.600
↑
C
19.200
4.800
1.200
0.300
19.6608
1
307.200
76.800
19.200
4.800
↑
2
153.600
38.400
93.600
2.400
↑
4
76.800
19.10
4.800
1.200
↑
8
38.400
9.600
2.400
0.600
↑
10
19.200
4.800
1.200
0.300
22.1184
3
115.200
28.800
7.200
1.800
24.576
1
384.000
96.000
24.000
6.000
↑
2
192.000
48.000
12.000
3.000
↑
4
96.000
24.000
6.000
1.500
↑
5
76.800
19.200
4.800
1.200
↑
8
48.000
12.000
3.000
0.750
↑
A
38.400
9.600
2.400
0.600
↑
10
24.000
6.000
1.500
0.375
27.0336
B
38.400
9.600
2.400
0.600
29.4912
1
460.800
115.200
28.800
7.200
↑
3
153.600
38.400
9.600
2.400
↑
4
115.200
28.800
7.200
1.800
↑
6
76.800
19.200
4.800
1.200
↑
9
51.200
12.800
3.200
1.800
↑
C
38.400
9.600
2.400
1.600
↑
F
30.720
7.680
1.920
1.480
↑
10
28.800
7.200
1.800
0.450
31.9488
D
38.400
9.600
2.400
0.600
34.4064
7
76.800
19.200
4.800
1.200
Note 1: Transfer rates in I/O interface mode are eight times faster than the values given above.
Note 2: The values in this table are calculated for when fc is selected as the system clock, the clock
gear is set for fc and the system clock is the prescaler clock input.
Timer out clock (TA0TRG) can be used for source clock of UART mode only.
Calculation method the frequency of TA0TRG
Frequency of TA0TRG =
Baud rate × 16
Note 1: The TMRA0 match detects signal cannot be used as the transfer clock in I/O interface mode.
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(3) Serial clock generation circuit
This circuit generates the basic clock for transmitting and receiving data.
•
In I/O interface mode
In SCLK output mode with the setting SC0CR<IOC> = 0, the basic clock is
generated by dividing the output of the baud rate generator by 2, as described
previously.
In SCLK input mode with the setting SC0CR<IOC> = 1, the rising edge or falling
edge will be detected according to the setting of the SC0CR<SCLKS> register to
generate the basic clock.
•
In UART mode
The SC0MOD0<SC1:0> setting determines whether the baud rate generator
clock, the internal system clock fSYS, the match detect signal from timer TMRA0 or
the external clock (SCLK0) is used to generate the basic clock SIOCLK.
(4) Receiving counter
The receiving counter is a 4-bit binary counter used in UART mode which counts up
the pulses of the SIOCLK clock. It takes 16 SIOCLK pulses to receive 1 bit of data;
each data bit is sampled three times – on the 7th, 8th, and 9th clock cycles.
The value of the data bit is determined from these three samples using the majority
rule.
For example, if the data bit is sampled respectively as 1, 0 and 1 on 7th, 8th, and 9th
clock cycles, the received data bit is taken to be 1. A data bit sampled as 0, 0 and 1 is
taken to be 0.
(5) Receiving control
•
In I/O interface mode
In SCLK output mode with the setting SC0CR<IOC> = 0, the RXD0 signal is
sampled on the rising or falling edge of the shift clock which is output on the
SCLK0 pin, according to the SC0CR<SCLKS> setting.
In SCLK input mode with the setting SC0CR<IOC> = 1, the RXD0 signal is
sampled on the rising or falling edge of the SCLK0 input, according to the
SC0CR<SCLKS> setting.
•
In UART mode
The receiving control block has a circuit which detects a start bit using the
majority rule. Received bits are sampled three times; when two or more out of
three samples are 0, the bit is recognized as the start bit and the receiving
operation commences.
The values of the data bits that are received are also determined using the
majority rule.
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(6) The receiving buffers
To prevent overrun errors, the receiving buffers are arranged in a double-buffer
structure.
Received data is stored one bit at a time in receiving buffer 1 (which is a shift
register). When 7 or 8 bits of data have been stored in receiving buffer 1, the stored
data is transferred to receiving buffer 2 (SC0BUF); this causes an INTRX0 interrupt
to be generated. The CPU only reads receiving buffer 2 (SC0BUF). Even before the
CPU has finished reading the contents of receiving buffer 2 (SC0BUF), more data can
be received and stored in receiving buffer 1. However, if receiving buffer 2 (SC0BUF)
has not been read completely before all the bits of the next data item are received by
receiving buffer 1, an overrun error occurs. If an overrun error occurs, the contents of
receiving buffer 1 will be lost, although the contents of receiving buffer 2 and
SC0CR<RB8> will be preserved.
SC0CR<RB8> is used to store either the parity bit − added in 8-bit UART mode − or
the most significant bit (MSB) − in 9-bit UART mode.
In 9-bit UART mode the wakeup function for the slave controller is enabled by
setting SC0MOD0<WU> to 1; in this mode INTRX0 interrupts occur only when the
value of SC0CR<RB8> is 1.
(7) Transmission counter
The transmission counter is a 4-bit binary counter which is used in UART mode and
which, like the receiving counter, counts the SIOCLK clock pulses; a TXDCLK pulse is
generated every 16 SIOCLK clock pulses.
SIOCLK
15
16
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
1
2
TXDCLK
Figure 3.10.4 Generation of the Transmission Clock
(8) Transmission controller
•
In I/O interface mode
In SCLK output mode with the setting SC0CR<IOC> = 0, the data in the
transmission buffer is output one bit at a time to the TXD0 pin on the rising edge
or falling edge of the shift clock which is output on the SCLK0 pin, according to the
SC0CR<SCLKS> setting.
In SCLK input mode with the setting SC0CR<IOC> = 1, the data in the
transmission buffer is output one bit at a time on the TXD0 pin on the rising or
falling edge of the SCLK0 input, according to the SC0CR<SCLKS> setting.
•
In UART mode
When transmission data sent from the CPU is written to the transmission buffer,
transmission starts on the rising edge of the next TXDCLK, generating a
transmission shift clock TXDSFT.
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Handshake function
Use of CTS0 pin allows data can be sent in units of one frame; thus, overrun
errors can be avoided. The handshake functions is enabled or disabled by the
SC0MOD<CTSE> setting.
When the CTS0 pin goes high on completion of the current data send, data
transmission is halted until the CTS0 pin goes low again. However, the INTTX0
interrupt is generated, it requests the next data send to the CPU. The next data is
written in the transmission buffer and data sending is halted.
Although there is no RTS pin, a handshake function can easily be configured by
assigning any port to perform the RTS function. The RTS should be output high to
request send data halt after data receive is completed by software in the RXD
interrupt routine.
TMP91C829
TMP91C829
RXD
TXD
RTS (Any port)
CTS0
Sender
Receiver
Figure 3.10.5 Handshake Function
Timing to writing to the
transmission buffer
CTS
Send is suspended
from (1) and (2).
(1)
13
(2)
14
15
16
1
2
3
14
15
16
1
2
3
SIOCLK
TXDCLK
Start bit
TXD
Note 1:
Bit0
If the CTS signal goes high during transmission, no more data will be sent after completion of the current
transmission.
Note 2:
Transmission starts on the first falling edge of the TXDCLK clock after the CTS signal has fallen.
Figure 3.10.6 CTS (Clear to send) Timing
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(9) Transmission buffer
The transmission buffer (SC0BUF) shifts out and sends the transmission data
written from the CPU, in order one bit at a time starting with the least significant bit
(LSB) and finishing with the most significant bit (MSB). When all the bits have been
shifted out, the empty transmission buffer generates an INTTX0 interrupt.
(10) Parity control circuit
When SC0CR<PE> in the serial channel control register is set to 1, it is possible to
transmit and receive data with parity. However, parity can be added only in 7-bit
UART mode or 8-bit UART mode. The SC0CR<EVEN> field in the serial channel
control register allows either even or odd parity to be selected.
In the case of transmission, parity is automatically generated when data is written
to the transmission buffer SC0BUF. The data is transmitted after the parity bit has
been stored in SC0BUF<TB7> in 7-bit UART mode or in SC0MOD0<TB8> in 8-bit
UART mode. SC0CR<PE> and SC0CR<EVEN> must be set before the transmission
data is written to the transmission buffer.
In the case of receiving, data is shifted into receiving buffer 1, and the parity is
added after the data has been transferred to receiving buffer 2 (SC0BUF), and then
compared with SC0BUF<RB7> in 7-bit UART mode or with SC0CR<RB8> in 8-bit
UART mode. If they are not equal, a parity error is generated and the SC0CR<PERR>
flag is set.
(11) Error flags
Three error flags are provided to increase the reliability of data reception.
1. Overrun error <OERR>
If all the bits of the next data item have been received in receiving buffer 1 while
valid data still remains stored in receiving buffer 2 (SC0BUF), an overrun error is
generated.
Following shows the overrun generating process flow example.
(Receiving interrupts routine)
(1) Read of receiving buffer
(2) Read of error flag
(3) If <OERR> = “1”
Then
A)
B)
C)
D)
E)
F)
Set to receiving enable write “0” to <RXE>
Wait end of now flame
Read of receiving buffer
Read of error flag
Set to receiving enable write “1” to <RXE>
Request transmission again
(4) Other process
2. Parity error <PERR>
The parity generated for the data shifted into receiving buffer 2 (SC0BUF) is
compared with the parity bit received via the RXD pin. If they are not equal, a parity
error is generated.
3. Framing error <FERR>
The stop bit for the received data is sampled three times around the center. If the
majority of the samples are 0, a framing error is generated.
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TMP91C829
(12) Timing generation
a. In UART mode
Receiving
Mode
Interrupt timing
Framing error timing
8 Bits, 7 Bits + Parity, 7 Bits
Center of last bit
Center of last bit
(Bit8)
(Parity bit)
Center of stop bit
Center of stop bit
Center of stop bit
Center of last bit
Center of stop bit
Parity error timing
Overrun error timing
8 Bits + Parity
(Note)
9 Bits
(Note)
−
Center of stop bit
(Parity bit)
Center of last bit
Center of last bit
(Bit8)
(Parity bit)
Center of stop bit
Note: In 9-bit mode and 8 bits + parity mode, interrupts coincide with the 9th bit pulse.
Thus, when servicing the interrupt, it is necessary to allow a 1-bit period to elapse (So
that the stop bit can be transferred) in order to allow proper framing error checking.
Transmitting
Mode
Interrupt timing
b.
9 Bits
8 Bits + Parity
8 Bits, 7 Bits + Parity, 7 Bits
Just before stop bit is
Just before last data
Just before last data bit is
transmitted
bit is transmitted
transmitted
I/O interface
Transmission
SCLK output mode
Immediately after the last bit. (See Figure 3.10.19)
interrupt
SCLK input mode
Immediately after rise of last SCLK signal rising mode, or
SCLK output mode
Timing used to transfer received to data receive buffer 2 (SC0BUF)
SCLK input mode
Timing used to transfer received data to receive buffer 2 (SC0BUF)
timing
Receiving
interrupt
timing
immediately after fall in falling mode. (See Figure 3.10.20)
(e.g., immediately after last SCLK). (See Figure 3.10.21)
(e.g., immediately after last SCLK). (See Figure 3.10.22)
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TMP91C829
3.10.3
SFRs
SC0MOD0 Bit symbol
(0202H)
Read/Write
After reset
Function
7
6
5
4
3
2
1
0
TB8
CTSE
RXE
WU
SM1
SM0
SC1
SC0
0
0
0
0
0
0
0
0
R/W
Transfer
Hand shake Receive
Wakeup
Serial transmission mode Serial transmission clock
data bit8
0: CTS
function
function
00: I/O interface Mode
(UART)
0: Receive
0: Disable
01: 7-bit UART mode
00: TMRA0 trigger
1: Enable
10: 8-bit UART mode
01: Baud rate generator
disable
1: CTS
enable
disable
1: Receive
11: 9-bit UART mode
enable
10: Internal clock fSYS
11: External clcok
(SCLK0 input)
Serial transmission clock source (UART)
00
01
10
Timer TMRA0 match detect signal
Baud rate generator
Internal clock fSYS
11
External clock (SCLK0 input)
Note: The clock selection for the I/O interface mode is
controlled by the serial control register (SC0CR).
Serial transmission mode
00
01
10
11
I/O interface mode
UART
7-bit mode
8-bit mode
9-bit mode
Wakeup function
0
1
9-Bit UART
Other modes
Interrupt generated when
data is received
Don’t care
Interrupt generated only
when SC0CR<RB8> = 1
Receiving function
0
1
Receive disabled
Receive enabled
Handshake function ( CTS pin)
0
1
Disabled (Always transferable)
Enabled
Transmission data bit8
Figure 3.10.7 Serial Mode Control Register (Channel 0, SC0MOD0)
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SC1MOD0 Bit symbol
(020AH)
Read/Write
After reset
Function
7
6
5
4
TB8
CTSE
RXE
WU
3
2
1
0
SM1
SM0
SC1
SC0
0
0
0
0
R/W
0
0
0
0
Transfer
Hand shake Receive
Wakeup
Serial transmission mode Serial transmission clock
data bit8
0: CTS
function
function
00: I/O interface mode
(UART)
0: Receive
0: Disable
01: 7-bit UART mode
00: TMRA0 trigger
1: Enable
10: 8-bit UART mode
01: Baud rate generator
11: 9-bit UART mode
10: Internal clock fSYS
disable
1: CTS
enable
disable
1: Receive
enable
11: External clcok
(SCLK1 input)
Serial transmission clock source (UART)
00
01
10
Timer TMRA0 match detect signal
Baud rate generator
Internal clock fSYS
11
External clock (SCLK1 input)
Note: The clock selection for the I/O interface mode is
controlled by the serial control register (SC1CR).
Serial transmission mode
00
01
10
11
I/O interface mode
UART
7-bit mode
8-bit mode
9-bit mode
Wakeup function
0
1
9-Bit UART
Other modes
Interrupt generated when
data is received
Don’t care
Interrupt generated only
when SC1CR<RB8> = 1
Receiving function
0
1
Receive disabled
Receive enabled
Handshake function ( CTS pin)
0
1
Disabled (Always transferable)
Enabled
Transmission data bit8
Figure 3.10.8 Serial Mode Control Register (Channel 1, SC1MOD0)
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SC0CR
(0201H)
7
6
Bit symbol
RB8
EVEN
Read/Write
R
After reset
Function
Undefined
0
Received
Parity
data bit8
0: Odd
1: Even
5
4
3
2
1
PE
OERR
PERR
FERR
SCLKS
R/W
R (Cleared to 0 when read.)
0
Parity
addition
0: Disable
1: Enable
0
0
0
IOC
R/W
0
0
0
0: Baud rate
generator
0: SCLK0
1: Error
1: SCLK0
Overrun
Parity
Framing
pin input
1: SCLK0
I/O interface input clock selection
0
1
Baud rate generator
SCLK0 pin input
Edge selection for SCLK pin
0
1
Transmits and receivers
data on rising edge of SCLK0.
Transmits and receivers
data on falling edge SCLK0.
Framing error flag
Parity error flag
Cleared to 0 when read.
Overrun error flag
Parity addition enable
0
1
Disabled
Enabled
Even parity addition/check
0
1
Odd parity
Even parity
Received data bit8
Note:
As all error flags are cleared after reading. Do not test only a single bit with a bit testing instruction.
Figure 3.10.9 Serial Control Register (Channel 0, SC0CR)
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SC1CR
(0209H)
7
6
Bit symbol
RB8
EVEN
Read/Write
R
After reset
Function
Undefined
0
Received
Parity
data bit8
0: Odd
1: Even
5
4
3
2
1
PE
OERR
PERR
FERR
SCLKS
R/W
R (Cleared to 0 when read.)
0
Parity
addition
0: Disable
1: Enable
0
0
0
IOC
R/W
0
0
0
0: Baud rate
generator
0: SCLK1
1: Error
1: SCLK1
Overrun
Parity
Framing
pin input
1: SCLK1
I/O interface input clock selection
0
1
Baud rate generator
SCLK0 pin input
Edge selection for SCLK pin
0
1
Transmits and receivers
data on rising edge of SCLK1.
Transmits and receivers
data on falling edge SCLK1.
Framing error flag
Parity error flag
Cleared to 0 when read.
Overrun error flag
Parity addition enable
0
1
Disabled
Enabled
Even parity addition/check
0
1
Odd parity
Even parity
Received data bit8
Note:
As all error flags are cleared after reading. Do not test only a single bit with a bit testing instruction.
Figure 3.10.10 Serial Control Register (Channel 1, SC1CR)
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TMP91C829
BROCR
(0203H)
Bit symbol
7
6
5
4
−
BR0ADDE
BR0CK1
0
0
BR0CK0
BR0S3
R/W
Read/Write
After reset
0
Function
0
Received
+(16 − K)/16 00: φT0
data bit8
division
01: φT2
0: Disable
10: φT8
1: Enable
11: φT32
+(16 − K)/16 division enable
3
0
00
Internal clock φT0
1
Enable
01
Internal clock φT2
Bit symbol
(0204H)
Read/Write
0
BR0S2
BR0S1
BR0S0
0
0
0
Setting the input clock of baud rate generator
Disable
7
1
Setting of the divided frequency
0
BR0ADD
2
6
10
Internal clock φT8
11
Internal clock φT32
5
4
3
2
BR0K3
BR0K2
1
0
BR0K1
BR0K0
0
0
R/W
After reset
0
0
Function
Sets frequency divisor K
(divided by N = (16 − K)/16)
Sets baud rate generator frequency divisor
BR0CR<BR0ADDE> = 1
BR0CR
<BR0S3:0>
DR0ADD
<BR0K3:0>
0000
0000 (N = 16)
0000 (N = 2)
or
or
0001 (N = 1)
1111 (N = 15)
Disable
Disable
Disable
Divided by
N + 16 − K
0001 (K = 1)
to
1111 (K = 15)
BR0CR<BR0ADDE> = 0
0001 (N = 1) (Only UART)
to
1111 (N = 15)
0000 (N = 16)
Divided by N
16
Note1:Availability of +(16-K)/16 division function
N
UART mode
I/O mode
2 to 15
○
×
1 , 16
×
×
The baud rate generator can be set “1” in UART mode and disable +(16-K)/16 division function.Don’t use in
I/O interface mode.
Note2:Set BR0CR <BR0ADDE> to 1 after setting K (K = 1 to 15) to BR0ADD<BR0K3:0> when +(16-K)/16 division
function is used. Writes to unused bits in the BR0ADD register do not affext operation, and undefined data is
read from these unused bits.
Figure 3.10.11 Baud Rate Generator Control (Channel 0, BR0CR, BR0ADD)
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TMP91C829
BR1CR
(020BH)
Bit symbol
7
6
5
−
BR1ADDE
BR1CK1
4
0
0
Read/Write
After reset
0
Function
0
Received
+(16 − K)/16 00: φT0
data bit8
division
01: φT2
0: Disable
10: φT8
1: Enable
11: φT32
+(16 − K)/16 division enable
3
BR1CK0
BR1S3
R/W
0
00
01
Internal clock φT2
10
Internal clock φT8
11
Internal clock φT32
(020CH)
Read/Write
0
0
0
Internal clock φT0
Disable
Enable
7
0
BR1S0
Setting the input clock of baud rate generator
0
Bit symbol
1
BR1S1
Setting of the divided frequency
1
BR1ADD
2
BR1S2
6
5
4
3
2
1
0
BR1K3
BR1K2
BR1K1
BR1K0
0
0
0
0
R/W
After reset
Function
Sets frequency divisor K
(divided by N = (16 − K)/16)
Sets baud rate generator frequency divisor
BR0CR<BR1ADDE> = 1
BR1CR
<BR1S3:0>
DR1ADD
<BR1K3:0>
0000
0000 (N = 16)
0000 (N = 2)
or
or
0001 (N = 1)
1111 (N = 15)
Disable
Disable
0001 (K = 1)
to
Divided by
Disable
1111 (K = 15)
N + 16 − K
BR1CR<BR1ADDE> = 0
0001 (N = 1) (Only UART)
to
1111 (N = 15)
0000 (N = 16)
Divided by N
16
Note1:Availability of +(16-K)/16 division function
N
UART mode
I/O mode
2 to 15
○
×
1 , 16
×
×
The baud rate generator can be set “1” in UART mode and disable +(16-K)/16 division function.Don’t use in
I/O interface mode.
Note2:Set BR1CR <BR1ADDE> to 1 after setting K (K = 1 to 15) to BR1ADD<BR1K3:0> when +(16-K)/16 division
function is used. Writes to unused bits in the BR1ADD register do not affext operation, and undefined data is
read from these unused bits.
Figure 3.10.12 Baud Rate Generator Control (Channel 1, BR1CR, BR1ADD)
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7
6
5
4
3
2
1
0
TB7
TB6
TB5
TB4
TB3
TB2
TB1
TB0
7
6
5
4
3
2
1
0
RB7
RB6
RB5
RB4
RB3
RB2
RB1
RB0
SC0BUF
(0200H)
(Transmission)
(Receiving)
Note: Prohibit read-modify-write for SC0BUF.
Figure 3.10.13 Serial Transmission/Receiving Buffer Registers (Channel 0, SC0BUF)
SC0MOD1 Bit symbol
(0205H)
Read/Write
After reset
Function
7
6
I2S0
FDPX0
R/W
R/W
0
5
4
3
2
1
0
STSEN0
W
0
1
IDLE2
Duplex
STS0
0: Stop
0: Half
0: Enable
1: Run
1: Full
1: Disable
Figure 3.10.14 Serial Mode Control Register 1 (Channel 0, SC0MOD1)
7
6
5
4
3
2
1
0
TB7
TB6
TB5
TB4
TB3
TB2
TB1
TB0
7
6
5
4
3
2
1
0
RB7
RB6
RB5
RB4
RB3
RB2
RB1
RB0
SC1BUF
(0208H)
(Transmission)
(Receiving)
Note: Prohibit read-modify-write for SC1BUF.
Figure 3.10.15 Serial Transmission/Receiving Buffer Registers (Channel 1, SC1BUF)
SC1MOD1 Bit symbol
(020DH)
Read/Write
After reset
Function
7
6
I2S1
FDPX1
5
4
3
2
1
R/W
R/W
STSEN1
W
0
0
0
1
IDLE2
Duplex
STS1
0: Stop
0: Half
0:Enable
1: Run
1: Full
1:Disable
Figure 3.10.16 Serial Mode Control Register 1 (Channel 1, SC1MOD1)
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TMP91C829
3.10.4
Operation in Each Mode
(1) Mode 0 (I/O interface mode)
This mode allows an increase in the number of I/O pins available for transmitting
data to or receiving data from an external shift register.
This mode includes the SCLK output mode to output synchronous clock SCLK and
SCLK input external synchronous clock SCLK.
Output extension
TMP91C829
TXD
Input extension
Shift register
SI
SCLK
SCK
Port
RCK
TMP91C829
A
B
C
D
E
F
G
H
RXD
SCLK
Port
Shift register
QH
CLOCK
S/ L
A
B
C
D
E
F
G
H
TC74HC165 or equivalent
TC74HC595 or equivalent
Figure 3.10.17 Example of SCLK Output Mode Connection
Output extension
TMP91C829
TXD
Input extension
Shift register
SI
SCLK
SCK
Port
RCK
A
B
C
D
E
F
G
H
TMP91C829
RXD
SCLK
Port
QH
CLOCK
S/ L
A
B
C
D
E
F
G
H
TC74HC165 or equivalent
TC74HC595 or equivalent
External clock
Shift register
External clock
Figure 3.10.18 Example of SCLK Input Mode Connection
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a.
Transmission
In SCLK output mode 8-bit data and a synchronous clock are output on the
TXD0 and SCLK0 pins respectively each time the CPU writes the data to the
transmission buffer.
When all the data has been output, INTES0<ITX0C> is set to 1, causing an
INTTX0 interrupt to be generated.
Timing to write
transmission data
SCLK0 output
(<SCLKS>=0
Rising edge mode)
(Internal clock
timing)
SCLK0 output
(<SCLKS>=1
Falling edge mode)
Bit1
Bit0
TXD0
Bit6
Bit7
ITX0C
(INTTX0
Interrupt request)
Figure 3.10.19 Transmitting Operation in I/O Interface Mode (SCLK0 output mode)
(Channel 0)
In SCLK input mode, 8-bit data is output on the TXD0 pin when the SCLK0
input becomes active after the data has been written to the transmission buffer by
the CPU.
When all the data has been output, INTES0<ITX0C> is set to 1, causing an
INTTX0 interrupt to be generated.
SCLK0input
(<SCLKS> = 0
Rising edge mode)
SCLK0 input
(<SCLKS> = 1
Falling edge mode)
TXD0
Bit0
Bit1
Bit5
Bit6
Bit7
ITX0C
(INTTX0
Interrupt request)
Figure 3.10.20 Transmitting Operation in I/O Interface Mode (SCLK0 input mode)
(Channel 0)
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b.
Receiving
In SCLK output mode the synchronous clock is output on the SCLK0 pin and
the data is shifted to receiving buffer 1. This is initiated when the receive
interrupt flag INTES0<IRX0C> is cleared as the received data is read. When 8-bit
data is received, the data is transferred to receiving buffer 2 (SC0BUF) following
the timing shown below and INTES0<IRX0C> is set to 1 again, causing an
INTRX0 interrupt to be generated.
Setting SC0MOD0<RXE>to 1 initiates SCLK0 output.
IRX0C
(INTRX0
interrupt request)
SCLK0 output
(<SCLKS>=0
Rising edge mode)
SCLK0 output
(<SCLKS>=1
Fallingf edge mode)
RXD0
Bit1
Bit0
Bit6
Bit7
Figure 3.10.21 Receiving Operation in I/O Interface Mode (SCLK0 output mode)
(Channel 0)
In SCLK input mode the data is shifted to receiving buffer 1 when the SCLK
input goes active. The SCLK input goes active when the receive interrupt flag
INTES0<IRX0C> is cleared as the received data is read. When 8-bit data is
received, the data is shifted to receiving buffer 2 (SC0BUF) following the timing
shown below and INTES0<IRX0C> is set to 1 again, causing an INTRX0 interrupt
to be generated.
SCLK0 input
(<SCLKS> = 0:
Rising edge mode)
SCLK0 input
(<SCLKS> = 1:
Falling edge mode)
RXD0
Bit0
Bit1
Bit5
Bit6
Bit7
IRX0C
(INTRX0 )
Figure 3.10.22 Receiving Operation in I/O Interface Mode (SCLK0 input mode)
(Channel 0)
Note: The system must be put in the receive enable state (SCMOD0<RXE> = 1) before data can
be received.
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c.
Transmission and receiving (Full duplex mode)
When full duplex mode is used, set the receive interrupt level to 0 and set
enable the level of transmit interrupt. Ensure that the program which transmits
the interrupt reads the receiving buffer before setting the next transmit data.
The following is an example of this:
Example: Channel 0, SCLK output
Baud rate = 9600 bps
fc = 14.7456 MHz
* Clock state
System clock:
High frequency (fc)
Clock gear:
1 (fc)
Prescaler clock: fFPH
Main routine
INTES0
7
0
6
0
5
0
4
1
3
0
2
0
1
0
0
0
P8CR
–
–
–
–
–
1
0
1
Set the INTTX0 level to 1.
Set the INTRX0 level to 0.
Set P80, P81, and P82 to function as the TXD0,
RXD0, and SCLK0 pins respectively.
P8FC
–
–
–
–
–
1
–
1
SC0MOD0 0
0
0
0
0
0
0
0
Select I/O interface mode.
SC0MOD1 1
1
0
0
0
0
0
0
Select full duplex mode.
SC0CR
0
0
0
0
0
0
0
0
SCLK_out, transmit on negative edge, receive on
positive edge.
BR0CR
Baud rate = 9600 bps.
0
0
1
1
0
0
1
1
SC0MOD0 0
0
1
0
0
0
0
0
Enable receiving.
*
*
*
*
*
*
*
*
Set the transmit data and start.
X
–
1
X
X
SC0BUF
INTTX0 interrupt routine
Acc SC0BUF
SC0BUF
–
–
X
Read the receiving buffer.
Set the next transmit data.
X: Don’t care, −: No change
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(2) Mode 1 (7-bit UART mode)
7-bit UART mode is selected by setting the serial channel mode register
SC0MOD0<SM1:0> field to 01.
In this mode a parity bit can be added. Use of a parity bit is enabled or disabled by
the setting of the serial channel control register SC0CR<PE> bit; whether even parity
or odd parity will be used is determined by the SC0CR<EVEN> setting when
SC0CR<PE> is set to 1 (Enabled).
Setting example: When transmitting data of the following format, the control registers
should be set as described below. This explanation applies to channel
0.
Start
Bit0
1
2
3
4
5
Even
parity Stop
6
Transmission direction (Transmission rate: 2400 bps at fc = 12.288 MHz)
* Clock state
P8CR
P8FC
SC0MOD
SC0CR
BR0CR
INTES0
SC0BUF
←
←
←
←
←
←
←
System clock: High frequency (fc)
Clock gear:
1 (fc)
Prescaler clock: System clock
7 6 5 4 3 2 1 0
− − − − − − 1
− − − − − − 1
0 − X 0 1 0 1
1 1 X X X 0 0
0 1 0 0 1 0 1
1 0 0 − − − −
−
−
X
X
0
1
Set P80 to function as the TXD0 pin.
Select 7-bit UART mode.
Add even parity.
Set the transfer rate to 2400 bps.
Enable the INTTX0 interrupt and set it to interrupt level 4.
Set data for transmission.
* * * * * * * *
X: Don’t care, −: No change
(3) Mode 2 (8-bit UART mode)
8-bit UART mode is selected by setting SC0MOD0<SM1:0> to 10. In this mode a
parity bit can be added (Use of a parity bit is enabled or disabled by the setting of
SC0CR<PE>); whether even parity or odd parity will be used is determined by the
SC0CR<EVEN> setting when SC0CR<PE> is set to 1 (Enabled).
Setting example: When receiving data of the following format, the control registers
should be set as described below.
Start
Bit0
1
2
3
4
5
6
7
Odd
parity Stop
Transmission direction (Transmission rate: 9600 bps at fc = 12.288 MHz)
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* Clock state
System clock: High frequency (fc)
Clock gear:
1 (fc)
Prescaler clock: System clock
Main settings
P8CR
SC0MOD
SC0CR
BR0CR
INTES0
←
←
←
←
←
7 6 5 4 3 2 1
− − − − − − 0
− 0 1 X 1 0 0
X 0 1 X X X 0
0 0 0 1 0 1 0
− − − − 1 1 0
0
−
1
0
1
0
Interrupt processing
Acc
← SC0CR AND 00011100
if Acc
≠ 0 then ERROR
Acc
← SC0BUF
Set P80 to function as the TXD0 pin.
Enable receiving in 8-bit UART mode.
Add even parity.
Set the transfer rate to 9600 bps.
Enable the INTTX0 interrupt and set it to interrupt level 4.
Check for errors.
Read the received data.
X: Don’t care, −: No change
(4) Mode 3 (9-bit UART mode)
9-bit UART mode is selected by setting SC0MOD0<SM1:0> to 11. In this mode
parity bit cannot be added.
In the case of transmission the MSB (9th bit) is written to SC0MOD0<TB8>. In the
case of receiving it is stored in SC0CR<RB8>. When the buffer is written and read, the
MSB is read or written first, before the rest of the SC0BUF data.
Wakeup function
In 9-bit UART mode, the wakeup function for slave controllers is enabled by
setting SC0MOD0<WU> to 1. The interrupt INTRX0 can only be generated when
<RB8> = 1.
TXD
RXD
Master
Note:
TXD
RXD
TXD
Slave 1
RXD
Slave 2
TXD
RXD
Slave 3
The TXD pin of each slave controller must be in open-drain output mode.
Figure 3.10.23 Serial Link Using Wakeup Function
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Protocol
a. Select 9-bit UART mode on the master and slave controllers.
b. Set the SC0MOD0<WU> bit on each slave controller to 1 to enable data receiving.
c. The master controller transmits data one frame at a time. Each frame includes an 8-bit
select code which identifies a slave controller. The MSB (Bit8) of the data (<TB8>) is set
to 1.
Start
Bit0
1
2
3
4
5
6
7
Select code of slave controller
8
Stop
1
d. Each slave controller receives the above frame. Each controller checks the above select
code against its own select code. The controller whose code matches clears its WU bit to 0.
e. The master controller transmits data to the specified slave controller (The controller
whose SC0MOD<WU> bit has been cleared to 0). The MSB (Bit8) of the data (<TB8>) is
cleared to 0.
Start
Bit0
1
2
3
4
5
Data
6
7
Bit8
Stop
0
f. The other slave controllers (Whose <WU> bits remain at 1) ignore the received data
because their MSBs (Bit8 or <RB8>) are set to 0, disabling INTRX0 interrupts.
The slave controller whose WU bit = 0 can also transmit to the master controller. In this
way it can signal the master controller that the data transmission from the master
controller has been completed.
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Setting example:
TXD
To link two slave controllers serially with the master controller
using the internal clock fSYS as the transfer clock.
RXD
TXD
Master
RXD
TXD
RXD
Slave 1
Slave 2
Select code
00000001
Select code
00001010
Since serial channels 0 and 1 operate in exactly the same way, channel 0 only is
used for the purposes of this explanation.
•
Setting the master controller
Main
INTES0
← − − − − − − 0 1
← − − − − − − X 1
← 1 1 0 0 1 1 0 1
SC0MOD0
← 1 0 1 0 1 1 1 0
Set P80 and P81 to function as the TXD0 and RXD0 pins
respectively.
Enable the INTTX0 interrupt and set it to interrupt level 4.
Enable the INTRX0 interrupt and set it to interrupt level 5.
Set fSYS as the transmission clock for 9-bit UART mode.
SC0BUF
← 0 0 0 0 0 0 0 1
Set the select code for slave controller 1.
P8CR
P8FC
INTTX0 interrupt
SC0MOD0
SC0BUF
•
← 0 − − − − − − −
← * * * * * * * *
Set TB8 to TB0.
Set data for transmission.
Setting the slave controller
Main
P8CR
P8FC
ODE
INTES0
SC0MOD0
←
←
←
←
←
−
−
X
1
0
−
−
X
1
0
−
−
X
0
1
−
−
X
1
1
−
−
X
1
1
−
−
X
1
1
0 1
X 1
− 1
1 0
1 0
Select P81 and P80 to function as the RXD0 and TXD0 pins
respectively (Open-drain output).
Enable INTRX0 and INTTX0.
Set <WU> to 1 in 9-bit UART transmission mode using fSYS as
the transfer clock.
INTRX0 interrupt
Acc ← SC0BUF
if Acc = Select code
then SC0MOD0 ← − − − 0 − − − −
Clear<WU> to 0.
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3.11 Analog/Digital Converter
The TMP91C829 incorporates a 10-bit successive approximation type analog/digital
converter (AD converter) with 8-channel analog input.
Figure 3.11.1 is a block diagram of the AD converter. The 8-channel analog input pins (AN0 to
AN7) are shared with the input-only port, port A and can thus be used as an input port.
Note: When IDLE2, IDLE1 or STOP mode is selected, so as to reduce the power, with some timings
the system may enter a standby mode even though the internal comparator is still enabled.
Therefore be sure to check that AD converter operations are halted before a HALT instruction
is executed.
Internal data bus
AD mode control register 0
ADMOD0
<EOCF><ADBF><ITM0><REPEAT><SCAN><ADS>
Scan
Decoder
AD mode control register 1 ADMOD1
ADMOD1
<ADTRGE>
<ADCH2:0>
<VREFON>
Repeat
Interrupt
ADTRG
Busy
End
Analog input
Start
AD converter control
Channel select
circuit
AN7 (PA7)
INTAD
interrupt
AN6 (PA6)
AN4 (PA4)
AN3 (PA3)
AN2 (PA2)
AN1 (PA1)
Multiplexer
AN5 (PA5)
AD conversion result
Sample and
hold
+
−
AN0 (PA0)
register
ADREG04L to ADREG37L
ADREG04H to ADREG37H
Comparator
ADTRG (PA3)
VREFH
DA converter
VREFL
Figure 3.11.1 Block Diagram of AD Converter
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3.11.1
Analog/Digital Converter Registers
The AD converter is controlled by the two AD mode control registers: ADMOD0 and
ADMOD1. The eight AD conversion data upper and lower registers (ADREG04H/L,
ADREG15H/L, ADREG26H/L, and ADREG37H/L) store the results of AD conversion.
Figure 3.11.2 shows the registers related to the AD converter.
AD Mode Control Register 0
7
ADMOD0 Bit symbol
(02B0H)
EOCF
Read/Write
5
4
3
ADBF
−
−
ITM0
R
After reset
Function
6
2
1
0
REPEAT
SCAN
ADS
R/W
0
0
AD
0
AD
0
Always
Always
Interrupt
Repeat mode Scan mode
AD
conversion
conversion
write “0”.
write “0”.
specification
specification specification
conversion
end flag
busy flag
channel fixed
stopped
conversion
repeat mode 1: Repeat
1: Conversion 1: Conversion
complete
0
in conversion 0: Single
0: Conversion 0: Conversion
in progress
0
0: Every
in progress
0
0
0: Conversion start
channel
0: Don’t care
fixed mode
1: Start
conversion 1: Conversion
conversion
mode
1: Every
conversion
channel
Always “0”
scan mode
when read.
fourth
conversion
AD conversion start
0
Don’t care
1
Start AD conversion
Note: Always read as 0.
AD scan mode setting
0
AD conversion channel fixed mode
1
AD conversion channel scan mode
AD repeat mode setting
0
AD single conversion mode
1
AD repeat conversion mode
Specify AD conversion interrupt for channel fixed repeat
conversion mode
Channel fixed repeat conversion mode
<SCAN> = 0, <REPEAT> = 1
0
Generates interrupt every conversion.
1
Generates interrupt every fourth conversion.
AD conversion busy flag
0
AD conversion stopped
1
AD conversion in progress
AD conversion end flag
0
Before or during AD conversion
1
AD conversion complete
Figure 3.11.2 AD Converter Related Register
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AD Mode Control Register 1
ADMOD1 Bit symbol
(02B1H) Read/Write
After reset
Function
7
6
5
4
3
2
ADTRGE
ADCH2
1
0
VREFON
I2AD
R/W
R/W
ADCH1
ADCH0
0
0
0
0
VREF
IDLE2
AD external Analog input channel selection.
application
0: Stop
trigger start
control
1: Operate
control
R/W
0
0
0: OFF
0: Disable
1: ON
1: Enable
Analog input channel selection
<SCAN>
0
1
Channel
Channel
<ADCH2:0>
fixed
scanned
000
AN0
AN0
001
AN1
AN0 → AN1
010
AN2
AN0 → AN1 → AN2
011
AN3
AN0 → AN1 → AN2 → AN3
100
AN4
AN4
101
AN5
AN4 → AN5
110
AN6
AN4 → AN5 → AN6
111
AN7
AN4 → AN5 → AN6 → AN7
AD conversion start control by external trigger
( ADTRG input)
0
Disabled
1
Enabled
IDLE2 control
0
Stopped
1
In operation
Control of application of reference voltage to AD
converter
0
OFF
1
ON
Before starting conversion (before writing 1 to
ADMOD0<ADS>), set the <VREFON> bit to 1.
AD Mode Control Register 2
ADMOD2
Bit symbol
(2B2H)
Read/Write
After reset
7
6
5
4
3
2
1
0
ADM27
ADM26
ADM25
ADM24
ADM23
ADM22
ADM21
ADM20
0
0
0
1
0
0
0
1
R/W
Function
Please write 1E
AD Mode Control Register 3
ADMOD3
Bit symbol
(2B3H)
Read/Write
After reset
Function
7
6
5
4
3
2
1
0
ADM37
ADM36
ADM35
ADM34
ADM33
ADM32
ADM31
ADM30
1
1
0
0
1
1
1
1
R/W
Please write CF
Figure 3.11.3 AD Converter Related Register
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AD Conversion Data Lower Register 0/4
7
ADREG04L Bit symbol
(02A0H)
6
ADR01
5
4
3
2
1
ADR00
ADR0RF
Read/Write
R
After reset
Undefined
0
Stores lower 2 bits of AD
AD
conversion
data storage
flag
1: Conversion
result
stored
Function
R
conversion result.
AD Conversion Data Upper Register 0/4
6
5
4
3
7
ADREG04H Bit symbol
(02A1H)
ADR09
ADR08
ADR07
ADR06
Read/Write
1
0
ADR03
ADR02
Stores upper 8 bits AD conversion result.
AD Conversion Data Lower Register 1/5
6
5
4
3
7
ADR11
2
1
ADR10
Read/Write
R
After reset
Undefined
Function
2
ADR04
Undefined
Function
ADREG15L Bit symbol
ADR05
R
After reset
(02A2H)
R
0
AD
conversion
result flag
1: Conversion
result
stored
Stores lower 2 bits of AD
7
ADREG15H Bit symbol
ADR19
0
ADR1RF
conversion result.
(02A3H)
0
AD Conversion Data Upper Register 1/5
6
5
4
3
ADR18
ADR17
ADR16
Read/Write
ADR15
2
1
0
ADR14
ADR13
ADR12
R
After reset
Undefined
Function
Stores upper 8 bits AD conversion result.
9
8
7
6
5
4
3
2
1
0
Channel x
conversion result
ADREGxH
7
6
ADREGxL
5
4
3
2
1
0
7
6
5
4
3
2
1
0
• Bits 5 to 1 are always read as 1.
• Bit0 is the AD conversion data storage flag <ADRxRF>. When the
AD conversion result is stored, the flag is set to 1. When either of the
registers (ADREGxH, ADREGxL) is read, the flag is cleared to 0.
Figure 3.11.4 AD Converter Related Registers
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AD Conversion Result Lower Register 2/6
7
ADREG26L Bit symbol
(02A4H)
6
ADR21
4
3
2
1
ADR20
Read/Write
R
After reset
Undefined
Function
5
ADR2RF
R
0
AD
conversion
data storage
flag
1: Conversion
result
stored
Stores lower 2 bits of AD
conversion result.
AD Conversion Data Upper Register 2/6
6
5
4
3
7
ADREG26H Bit symbol
(02A5H)
ADR29
ADR28
ADR27
ADR26
Read/Write
2
1
0
ADR24
ADR23
ADR22
Undefined
Function
Stores upper 8 bits of AD conversion result.
AD Conversion Data Lower Register 3/7
6
5
4
3
7
(02A6H)
ADR25
R
After reset
ADREG37H Bit symbol
ADR31
2
1
ADR30
0
ADR3RF
Read/Write
R
After reset
Undefined
0
Stores lower 2 bits of AD
AD date
storage
1: Conversion
result
stored
Function
R
conversion result.
7
ADREG37H Bit symbol
(02A7H)
0
ADR39
AD Conversion Result Upper Register 3/7
6
5
4
3
ADR38
ADR37
ADR36
ADR35
Read/Write
R
After reset
Undefined
Function
2
1
0
ADR34
ADR33
ADR32
Stores upper 8 bits of AD conversion result.
9
8
7
6
5
4
3
2
1
0
Channel x
conversion result
ADREGxH
7
6
ADREGxL
5
4
3
2
1
0
7
6
5
4
3
2
1
0
• Bits 5 to 1 are always read as 1.
• Bit0 is the AD conversion data storage flag <ADRxRF>. When the
AD conversion result is stored, the flag is set to 1. When either of the
registers (ADREGxH, ADREGxL) is read, the flag is cleared to 0.
Figure 3.11.5 AD Converter Related Registers
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3.11.2
Description of Operation
(1) Analog reference voltage
A high-level analog reference voltage is applied to the VREFH pin; a low-level analog
reference voltage is applied to the VREFL pin. To perform AD conversion, the reference
voltage, the difference between VREFH and VREFL, is divided by 1024 using string
resistance. The result of the division is then compared with the analog input voltage.
To turn off the switch between VREFH and VREFL, write a 0 to
ADMOD1<VREFON> in AD mode control register 1. To start AD conversion in the off
state, first write a 1 to ADMOD1<VREFON>, wait 3 μs until the internal reference
voltage stabilizes (This is not related to fc.), then set ADMOD0<ADS> to 1.
(2) Analog input channel selection
The analog input channel selection varies depends on the operation mode of the AD
converter.
•
In analog input channel fixed mode (ADMOD0<SCAN> = 0)
Setting ADMOD1<ADCH2:0> selects one of the input pins AN0 to AN7 as the
input channel.
•
In analog input channel scan mode (ADMOD0<SCAN> = 1)
Setting ADMOD1<ADCH2:0> selects one of the eight scan modes.
Table 3.11.1 illustrates analog input channel selection in each operation mode.
On a reset, ADMOD0<SCAN> is set to 0 and ADMOD1<ADCH2:0> is initialized to
000. Thus pin AN0 is selected as the fixed input channel. Pins not used as analog input
channels can be used as standard input port pins.
Table 3.11.1 Analog Input Channel Selection
<ADCH2:0>
Channel Fixed
<SCAN> = 0
Channel Scan
<SCAN> = 1
000
AN0
AN0
001
AN1
AN0 → AN1
010
AN2
AN0 → AN1 → AN2
011
AN3
AN0 → AN1 → AN2 → AN3
100
AN4
AN4
101
AN5
AN4 → AN5
110
AN6
AN4 → AN5 → AN6
111
AN7
AN4 → AN5 → AN6 → AN7
(3) Starting AD conversion
To start AD conversion, write a 1 to ADMOD0<ADS> in AD mode control register 0
or ADMOD1<ADTRGE> in AD mode control register 1, pull the ADTRG pin input
from high to low. When AD conversion starts, the AD conversion busy flag
ADMOD0<ADBF> will be set to 1, indicating that AD conversion is in progress.
Writing a 1 to ADMOD0<ADS> during AD conversion restarts conversion. At that
time, to determine whether the AD conversion results have been preserved, check the
value of the conversion data storage flag ADREGxL<ADRxRF>.
During AD conversion, a falling edge input on the ADTRG pin will be ignored.
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(4) AD conversion modes and the AD conversion end interrupt
The four AD conversion modes are:
•
Channel fixed single conversion mode
•
Channel scan single conversion mode
•
Chanel fixed repeat conversion mode
•
Channel scan repeat conversion mode
The ADMOD0<REPEAT> and ADMOD0<SCAN> settings in AD mode control
register 0 determine the AD mode setting.
Completion of AD coversion triggers an INTAD AD conversion end interrupt request.
Also, ADMOD0<EOCF> will be set to 1 to indicate that AD conversion has been
completed.
a.
Channel fixed single conversion mode
Setting ADMOD0<REPEAT> and ADMOD0<SCAN> to 00 selects conversion
channel fixed single conversion mode.
In this mode data on one specified channel is converted once only. When the
conversion has been completed, the ADMOD0<EOCF> flag is set to 1,
ADMOD0<ADBF> is cleared to 0, and an INTAD interrupt request is generated.
b.
Channel scan single conversion mode
Setting ADMOD0<REPEAT> and ADMOD0<SCAN> to 01 selects conversion
channel scan single conversion mode.
In this mode data on the specified scan channels is converted once only. When
scan conversion has been completed, ADMOD0<EOCF> is set to 1,
ADMOD0<ADBF> is cleared to 0, and an INTAD interrupt request is generated.
c.
Channel fixed repeat conversion mode
Setting ADMOD0<REPEAT> and ADMOD0<SCAN> to 10 selects conversion
channel fixed repeat conversion mode.
In this mode data on one specified channel is converted repeatedly. When
conversion has been completed, ADMOD0<EOCF> is set to 1 and
ADMOD0<ADBF> is not cleared to 0 but held at 1. INTAD interrupt request
generation timing is determined by the setting of ADMOD0<ITM0>.
Setting <ITM0> to 0 generates an interrupt request every time an AD
conversion is completed.
Setting <ITM0> to 1 generates an interrupt request on completion of every
fourth conversion.
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d.
Channel scan repeat conversion mode
Setting ADMOD0<REPEAT> and ADMOD0<SCAN> to 11 selects conversion
channel scan repeat conversion mode.
In this mode data on the specified scan channels is converted repeatedly. When
each scan conversion has been completed, ADMOD0<EOCF> is set to 1 and an
INTAD interrupt request is generated. ADMOD0<ADBF> is not cleared to 0 but
held at 1.
To stop conversion in a repeat conversion mode (e.g., in cases of c and d), write a
0 to ADMOD0<REPEAT>. After the current conversion has been completed, the
repeat conversion mode terminates and ADMOD0<ADBF> is cleared to 0.
Switching to a halt state (IDLE2 mode with ADMOD1<I2AD> cleared to 0,
IDLE1 mode or STOP mode) immediately stops operation of the AD converter
even when AD conversion is still in progress. In repeat conversion modes (e.g., in
cases of c and d), when the halt is released, conversion restarts from the beginning.
In single conversion modes (e.g., in cases of a and b), conversion does not restart
when the halt is released (The converter remains stopped).
Table 3.11.2 shows the relationship between the AD conversion modes and interrupt
requests.
Table 3.11.2 Relationship between AD Conversion Modes and Interrupt Requests
Mode
Channel fixed single
conversion mode
Channel scan single
conversion mode
ADMOD0
Interrupt Request Generation
<ITM0>
<REPEAT>
<SCAN>
After completion of conversion
X
0
0
After completion of scan conversion
X
0
1
1
0
1
1
Channel fixed repeat
Every conversion
0
conversion mode
Every forth conversion
1
Channel scan repeat
After completion of every scan
conversion mode
conversion
X
X: Don’t care
(5) AD conversion time
84 states (4.7 μs at fFPH = 36 MHz) are required for the AD conversion of one
channel.
(6) Storing and reading the results of AD conversion
The AD conversion data upper and lower registers (ADREG04H/L to ADREG37H/L)
store the results of AD conversion. (ADREG04H/L to ADREG37H/L are read-only
registers.)
In channel fixed repeat conversion mode, the conversion results are stored
successively in registers ADREG04H/L to ADREG37H/L. In other modes the AN0 and
AN4, AN1 and AN5, AN2 and AN6, AN3 and AN7 conversion results are stored in
ADREG04H/L, ADREG15H/L, ADREG26H/L, and ADREG37H/L respectively.
Table 3.11.3 shows the correspondence between the analog input channels and the
registers which are used to hold the results of AD conversion.
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Table 3.11.3 Correspondence between Analog Input Channels and AD Conversion Result Registers
AD Conversion Result Register
Analog Input Channel
(Port A)
Conversion Modes
Other than at Right
AN0
Channel Fixed Repeat
Conversion Mode
(every 4 th conversion)
ADREG04H/L
ADREG04H/L
AN4
AN1
ADREG15H/L
ADREG15H/L
AN5
AN2
ADREG26H/L
ADREG26H/L
ADREG37H/L
ADREG37H/L
AN6
AN3
AN7
<ADRxRF>, bit0 of the AD conversion data lower register, is used as the AD
conversion data storage flag. The storage flag indicates whether the AD conversion
result register has been read or not. When a conversion result is stored in the AD
conversion result register, the flag is set to 1. When either of the AD conversion result
registers (ADREGxH or ADREGxL) is read, the flag is cleared to 0.
Reading the AD conversion result also clears the AD conversion end flag
ADMOD0<EOCF> to 0.
Setting example:
a.
Convert the analog input voltage on the AN3 pin and write the result, to memory
address 0800H using the AD interrupt (INTAD) processing routine.
Main routine:
7 6 5 4 3 2 1 0
INTE0AD
ADMOD1
ADMOD0
← X 1 0 0 - - - ← 1 1 X X 0 0 1 1
← X X 0 0 0 0 0 1
Enable INTAD and set it to interrupt level 4.
Set pin AN3 to be the analog input channel.
Start conversion in channel fixed single conversion mode.
Interrupt routine processing example:
WA
← ADREG37
Read value of ADREG37L and ADREG37H into 16-bit
general-purpose register WA.
WA
>>6
Shift contents read into WA six times to right and zero fill upper
bits.
(0800H)
b.
← WA
Write contents of WA to memory address 0800H.
This example repeatedly converts the analog input voltages on the three pins AN0,
AN1, and AN2, using channel scan repeat conversion mode.
INTE0AD
ADMOD1
ADMOD0
← X 0 0 0 - - - ← 1 1 X X 0 0 1 0
← X X 0 0 0 1 1 1
Disable INTAD.
Set pins AN0 to AN2 to be the analog input channels.
Start conversion in channel scan repeat conversion mode.
X: Don’t care, −: No change
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3.12 Watchdog Timer (Runaway detection timer)
The TMP91C829 features a watchdog timer for detecting runaway.
The watchdog timer (WDT) is used to return the CPU to normal state when it detects that the
CPU has started to malfunction (Runaway) due to causes such as noise. When the watchdog
timer detects a malfunction, it generates a non-maskable interrupt INTWD to notify the CPU of
the malfunction.
Connecting the watchdog timer output to the reset pin internally forces a reset. (The level of
external RESET pin is not changed.)
3.12.1
Configuration
Figure 3.12.1 is a block diagram of the watchdog timer (WDT).
WDMOD<RESCR>
RESET
Internal reset
Reset control
WDTI interrupt
WDMOD
<WDTP1:0>
Selector
15
2
fSYS
(fFPH/2)
17
2
21
219 2
Binary counter
Q
(22 Stage)
R
S
Reset
Internal reset
Write
4EH
Write
B1H
WDMOD<WDTE>
WDT control register WDCR
Internal data bus
Figure 3.12.1 Block Diagram of Watchdog Timer
Note:
The watchdog timer cannot operate by disturbance noise in some case.
Take care when design the device.
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The watchdog timer consists of a 22-stage binary counter which uses the system clock
(fSYS) as the input clock. The binary counter can output fSYS/215, fSYS/217, fSYS/219 and
fSYS/221.
WDT counter
Overflow
n
0
WDT interrupt
Clear write code
WDT clear
(Soft ware)
Figure 3.12.2 Normal Mode
The runaway is detected when an overflow occurs, and the watchdog timer can reset
device. In this case, the reset time will be between 22 and 29 states (19.6 to 25.8 μs at fFPH
= 36MHz, fOSCH = 2.25 state) is fFPH/2, where fFPH is generated by dividing the high-speed
oscillator clock (fOSCH) by sixteen through the clock gear function.
Overflow
WDT counter
n
WDT interrupt
Internal reset
(19.6 to 25.8 μs
22 to 29 states
at fOSCH = 36 MHz, fFPH = 2.25 MHz)
Figure 3.12.3 Reset Mode
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3.12.2
Control Registers
The watchdog timer WDT is controlled by two control registers WDMOD and WDCR.
(1) Watchdog timer mode register (WDMOD)
a.
Setting the detection time for the watchdog timer in <WDTP>
This 2-bit register is used for setting the watchdog timer interrupt time used
when detecting runaway. On a reset this register is initialized to
WDMOD<WDTP1:0> = 00.
The detection times for WDT are shown in Figure 3.12.4.
b.
Watchdog timer enable/disable control register <WDTE>
On a reset WDMOD<WDTE> is initialized to 1, enabling the watchdog timer.
To disable the watchdog timer, it is necessary to set this bit to 0 and to write the
disable code (B1H) to the watchdog timer control register <WDCR>. This makes it
difficult for the watchdog timer to be disabled by runaway.
However, it is possible to return the watchdog timer from the disabled state to
the enabled state merely by setting <WDTE> to 1.
c.
Watchdog timer out reset connection <RESCR>
This register is used to connect the output of the watchdog timer with the
RESET terminal internally. Since WDMOD<RESCR>is initialized to 0 on a reset,
a reset by the watchdog timer will not be performed.
(2) Watchdog timer control register (WDCR)
This register is used to disable and clear the binary counter for the watchdog timer.
•
Disable control
The watchdog timer can be disabled by clearing WDMOD<WDTE> to 0 and then
writing the disable code (B1H) to the WDCR register.
WDMOD
WDCR
•
← 0 - - - - - - ← 1 0 1 1 0 0 0 1
Clear WDMOD<WDTE> to 0.
Write the disable code (B1H).
Enable control
Set WDMOD<WDTE> to 1.
•
Watchdog timer clear control
To clear the binary counter and cause counting to resume, write the clear code
(4EH) to the WDCR register.
WDCR
← 0 1 0 0 1 1 1 0
Write the clear code (4EH).
Note1: If it is used disable control, set the disable code (B1H) to WDCR after write the clear code (4EH) once. (Please
refer to setting example.)
Note2: If it is changed Watchdog timer setting, change setting after set to disable condition once.
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WDMOD
(0300H)
7
6
Bit symbol
WDTE
WDTP1
Read/Write
R/W
After reset
1
Function
5
4
3
2
WDTP0
I2WDT
R/W
0
1
0
−
RESCR
R/W
0
R/W
0
WDT control Select detecting time
15
1: Enable
00: 2 /fSYS
IDLE2
0: Stop
1: Operate
17
01: 2 /fSYS
19
10: 2 /fSYS
21
11: 2 /fSYS
0
0
1: Internally Always
connects write “0”.
WDL out
to the
reset pin
Watchdog timer out control
−
0
1
Connects WDT out to a reset
IDLE2 control
0
Stop
1
Operation
fc = 36 MHz
Watchdog timer detection time
SYSCR1
Gear Value
<GEAR2:0>
Watchdog Timer Detection Time
WDMOD<WDTP1:0>
00
01
000 (fc)
1.82 ms
7.28 ms
001 (fc/2)
3.64 ms
010 (fc/4)
7.28 ms
10
11
29.13 ms
116.51 ms
14.56 ms
58.25 ms
233.02 ms
29.13 ms
116.51 ms
466.03 ms
011 (fc/8)
14.56 ms
58.25 ms
232.02 ms
932.07 ms
100 (fc/16)
29.13 ms
116.51 ms
466.03 ms
1864.14 ms
Watchdog timer enable/disable control
0
Disabled
1
Enabled
Figure 3.12.4 Watchdog Timer Mode Register
7
WDCR
(0301H)
5
4
3
Bit symbol
−
Read/Write
W
Read
After reset
-modify
Function
-write
6
2
1
0
−
B1H: WDT disable code
4EH: WDT clear code
instruction
is prohibited
Disable/clear WDT
B1H
Disable code
4EH
Clear code
Others
Don’t care
Figure 3.12.5 Watchdog Timer Control Register
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3.12.3
Operation
The watchdog timer generates an INTWD interrupt when the detection time set in the
WDMOD<WDTP1:0> has elapsed. The watchdog timer must be zero cleared in software
before an INTWD interrupt will be generated. If the CPU malfunctions (e.g., if runaway
occurs) due to causes such as noise, but does not execute the instruction used to clear the
binary counter, the binary counter will overflow and an INTWD interrupt will be generated.
The CPU will detect malfunction (Runaway) due to the INTWD interrupt and in this case it
is possible to return to the CPU to normal operation by means of an anti-mulfunction
program. By connecting the watchdog timer out pin to a peripheral device’s reset input, the
occurrence of a CPU malfunction can also be relayed to other devices.
The watch dog timer works immediately after reset.
The watchdog timer does not operate in IDLE1 or STOP mode, as the binary counter
continues counting during bus release (When BUSAK goes low).
When the device is in IDLE2 mode, the operation of WDT depends on the
WDMOD<I2WDT> setting. Ensure that WDMOD<I2WDT> is set before the device enters
IDLE2 mode.
Example: a. Clear the binary counter.
WDCR
← 0 1 0 0 1 1 1 0
Write the clear code (4EH).
b. Set the watchdog timer detection time to 217/fSYS.
WDMOD
← 1 0 1 - - - - -
c. Disable the watchdog timer.
WDMOD
WDCR
← 0 - - - - - X X
← 1 0 1 1 0 0 0 1
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Write the disable code (B1H).
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3.13 Multi Vector Control
3.13.1
Multi Vector Controller
(1) Outline
By rewriting the value of multi vector control register (MVEC0 and MVEC1), a
vector table is arbitrarily movable.
(2) Control register
The amount of 228 bytes become an interruption vector area from the value set as
vector control register (MVEC0 and MVEC1).
Vector control register composition
MVEC0 Bit symbol
(00AEH) Read/Write
After reset
7
6
5
4
3
2
1
0
VEC7
VEC6
VEC5
VEC4
VEC3
VEC2
VEC1
VEC0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
1
1
1
1
1
1
1
1
Function
MVEC1 Bit symbol
(00AFH) Read/Write
After reset
Vector address A15 to A8
7
6
5
4
3
2
1
0
VEC15
VEC14
VEC13
VEC12
VEC11
VEC10
VEC9
VEC8
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
1
1
1
1
1
1
1
1
Function
Circuit composition
Vector address A23 to A16
CPU OUTPUT address AL23 to AL8
AL23 to AL8
CS circuit
from FFFF28H
to FFFFFFH
CS
AL8
Register
(MVEC0)
Register
(MVEC1)
S
A
Y
<VEC0>
A8
Internal address
A23 to A8
B
AL23
<VEC15>
A23
Note: Write MVEC1, MVEC0 after making an interruption prohibition state.
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3.13.2
Multi Boot Mode
(1) Outline
The TMP91C829 has multi boot mode available as an on-board programming
operation mode. When in multi boot mode, the boot ROM is mapped into memory space.
This boot ROM is a mask ROM that contains a program to rewrite the flash memory on
board.
Rewriting is accomplished by connecting the TMP91C829’s SIO and the
programming tool (Controller) and then sending commands from the controller to the
target board.
The boot program included in the boot ROM only has the function of a loader for
transferring program data from an external source into the device’s internal RAM.
Rewriting can be performed by UART. From 1000H to 105FH in device’s internal
RAM is work area of boot program. Don’t transfer program data in this work area.
Figure 3.12.1 shows an example of how to connect the programming controller and
the target board (when ROM has 16-bit data bus).
UART
3 pin
Programming
controller
TXD0 (Output)
RXD0 (Input)
RTS0 (P83) (Output)
CS2
CS
RD
OE
WR
WE
TMP91C829
D0 to D15
Boot/normal
ROM
D0 to D15
BOOT
A1 to A16
AD0 to AD15
Figure 3.13.1 Example for Connecting Units for On-board Programming
(2) Mode setting
To execute on-board programming, start the TMP91C829 in multi boot mode.
Settings necessary to start up in multi boot mode are shown below.
BOOT
=
RESET
=
L
After setting the BOOT pin each to the above conditions and a RESET , the
TMP91C829 start up in multi boot mode.
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(3) Memory map
Figure 3.12.2 shows memory maps for multi chip and multi boot modes. When start
up in multi boot mode, internal boot ROM is mapped in FFF800H address, the boot
program starts up.
When start up in multi chip mode, internal boot ROM is mapped in 1F800H address,
it can be made to operate arbitrarily by the user. Program starting address is 1F800H.
Multi chip mode
000000H
000100H
Multi boot mode
000000H
Internal I/O
(4 Kbytes)
000100H
001000H
Internal I/O
(4 Kbytes)
Direct area (n)
001000H
Internal RAM
(8 Kbytes)
Internal RAM
(8 Kbytes)
003000H
003000H
External memory
01F800H
Internal boot ROM
(2 Kbytes)
16-Mbyte area
(r32)
(−r32)
01FFFFH
External memory
(r32+)
(r32 + d8/16)
(r32 + r8/16)
(nnn)
External memory
FFFF00H
FFFFFFH
FFF800H
FFFEFFH
Internal boot ROM
(2 Kbytes)
FFFF00H
FFFFFFH
Vector table
(256 bytes)
Vector table
(256 bytes)
(
= Internal area)
Figure 3.13.2 TMP91C829 Memory Map
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(4) SIO interface specifications
The following shows the SIO communication format in multi boot mode.
Before on-board programming can be executed, the communication format on the
programming controller side must also be setup in the same way as for the
TMP91C829.
Note that although the default baud rate is 9600 bps, it can be changed to other
values as shown in Table 3.13.3.
Serial transfer mode:
Data length:
Parity bit:
STOP bit:
Handshake:
Baud rate (Default):
UART (Asynchronous communication) mode,
full-duplex communication.
8 bits.
None.
1 bit.
Microcontroller (P83) → Programming controller.
9600 bps.
(5) SIO data transfer format
Table 3.13.1 through 3.13.6 show supported frequencies, data transfer format, baud
rate modification commands, operation commands, version management information,
and frequency measurement result with data store location, respectively.
Also refer to the description of boot program operation in the latter pages of this
manual as you read these tables.
Table 3.13.1 Supported Frequencies
16.000 MHz
20.000 MHz
22.579 MHz
25.000 MHz
32.000 MHz
33.868 MHz
36.000 MHz
Table 3.13.2 Transfer Format
Number of Bytes
Transferred
Boot
ROM
Transfer Data from
Controller to TMP91C829
Baud Rate
− (Frequency measurement and baud
rate auto set)
OK: Echo back data (5AH)
Error: Nothing transmitted
1st byte
Matching data (5AH)
9600 bps
2nd byte
−
9600 bps
3rd byte
:
6th byte
−
9600 bps
Version management information
(See Table 3.13.5)
7th byte
−
9600 bps
Frequency information (See Table 3.13.6)
8th byte
9th byte
Baud rate modification command
(See Table 3.13.3)
9600 bps
9600 bps
−
OK: Echo back data
Error: Error code X 3
−
10th byte
:
n’th − 4 byte
User program
extended Intel Hex format (Binary)
Changed new baud rate Error: Operation stop by checksum error
n’th − 3 byte
−
Changed new baud rate OK: SUM (High)
(See (6) (iii) Notes on SUM)
n’th − 2 byte
−
Changed new baud rate OK: SUM (Low)
n’th − 1 byte
User program start command (C0H)
(See Table 3.13.4)
Changed new baud rate −
Changed new baud rate OK: Echo back data (C0H)
Error: Error code X 3
n’th byte
RAM
Transfer Data from
TMP91C829 to Controller
−
−
JUMP to user program start address
Error code X 3 means sending an error code three times. Example, when error code is 62H, TMP91C829 sends 62H three
times. About error code, see (6)(b) Error code.
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Table 3.13.3 Baud Rate Modification Command
Baud Rate (bps)
9600
19200
38400
57600
115200
Modification Command
28H
18H
07H
06H
03H
Table 3.13.4 Operation Command
Operation Command
Operation
C0H
Start user program
Table 3.13.5 Version Management Information
Version Information
ASCII code
FRM1
46H, 52H, 4DH, 31H
Table 3.13.6 Frequency Measurement Result Data
Frequency of Resonator
(MHz)
16.000
20.000
22.579
25.000
32.000
33.868
36.000
1000H
(RAM store address)
00H
01H
02H
03H
04H
05H
06H
(6) Description of SIO boot program operation
When you start the TMP91C829 in multi BOOT mode, the boot program starts up.
The boot program provides the RAM loader function described below.
RAM loader
The RAM loader transfers the data sent from the controller in extended Intel Hex
format into the internal RAM. When the transfer has terminated normally, the RAM
loader calculates the SUM and sends the result to the controller before it starts
executing the user program. The execution start address is the first address received.
This RAM loader function provides the user’s own way to control on-board
programming.
To execute on-board programming in the user program, you need to use the flash
memory command sequence to be connected. (Must be matched to the flash memory
addresses in multi boot mode.)
a. Operational procedure of RAM loader
1. Connect the serial cable. Make sure to perform connection before resetting the
microcontroller.
2. Set the BOOT pin to “boot” and reset the microcontroller.
3. The receive data in the 1st byte is the matching data. When the boot program
starts in multi boot mode, it goes to a state in which it waits for the matching data
to receive. Upon receiving the matching data, it automatically adjusts the serial
channels’ initial baud rate to 9600 bps. The matching data is 5AH.
4. The 2nd byte is used to echo back 5AH to the controller upon completion of the
automatic baud rate setting in the 1st byte. If the device fails in automatic baud
rate setting, it goes to an idle state.
5. The 3rd byte through 6th byte are used to send the version management
information of the boot program in ASCII code. The controller should check that
the correct version of the boot program is used.
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6. The 7th byte is used to send information of the measured frequency.
The controller should check that the frequency of the resonator is measured
correctly.
7. The receive data in the 8th byte is the baud rate modification data. The five kinds
of baud rate modification data shown in Table 3.13.3 are available. Even when you
do not change the baud rate, be sure to send the initial baud rate data (28H; 9600
bps). Baud rate modification becomes effective after the echo back transmission is
completed.
8. The 9th byte is used to echo back the received data to the controller when the data
received in the 8th byte is one of the baud rate modification data corresponding to
the device’s operating frequency. Then the baud rate is changed. If the received
baud rate data does not correspond to the device’s operating frequency, the device
goes to an idle state after sending 3 bytes of baud rate modification error code
(62H).
9. The receive data in the 10th byte through n’th – 4 byte is received as binary data
in extended Intel Hex format. No received data is echoed back to the controller.
The RAM loader processing routine ignores the received data until it receives the
start mark (3AH for “:”) in extended Intel Hex format. Nor does it send error code
to the controller. After receiving the start mark, the routine receives a range of
data from the data length to checksum and writes the received data to the
specified RAM addresses successively.
After receiving one record of data from start mark to checksum, the routine goes
to a start mark waiting state again.
If a receive error or checksum error of extended Intel Hex format occurs, the
device goes to an idle state without returning error code to the controller.
Because the RAM loader processing routine executes a SUM calculation routine
upon detecting the end record, the controller should be placed in a SUM waiting
state after sending the end record to the device.
10. The n’th – 3 byte and the n’th – 2 byte are the SUM value that is sent to the
controller in order of upper byte and lower byte. For details on how to calculate
the SUM, refer to “Notes on SUM” in the latter page of this manual. The SUM
calculation is performed only when no write error, receive error, or extended Intel
Hex format error has been encountered after detecting the end record. Soon after
calculation of SUM, the device sends the SUM data to the controller. The
controller should determine whether writing to the RAM has terminated normally
depending on whether the SUM value is received after sending the end record to
the device.
11. After sending the SUM, the device goes to a state waiting for the user program
start code. If the SUM value is correct, the controller should send the user
program start command to the n’th – 1 byte. The user program start command is
C0H.
12. The n’th byte is used to echo back the user program start code to the controller.
After sending the echo back to the controller, the stack pointer is set to 105FH and
the boot program jumps to the first address that is received as data in extended
Intel Hex format.
13. If the user program start code is wrong or a receive error occurs, the device goes to
an idle state after returning three bytes of error code to the controller.
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b. Error code
The boot program sends the processing status to the controller using various code.
The error code is listed in the table below.
Table 3.13.7 Error Code
Error Code
Meaning of Error Code
62H
Baud rate modification error occurred.
64H
Operation command error occurred.
A1H
Framing error in received data occurred.
A3H
Overrun error in received data occurred.
*1: When a receive error occurs when receiving the user program, the device does not send the error code to the
controller.
*2: After sending the error code, the device goes to an idle state.
c. Notes on SUM
1.
Calculation method
SUM consists of byte + byte … + byte, the sum of which is returned in word as
the result. Namely, data is read out in byte and sum of which is calculated, with
the result returned in word.
Example:
If the data to be calculated consists of the four bytes
A1H
B2H
2.
shown to the left, SUM of the data is:
A1H + B2H + C3H + D4H = 02EAH
C3H
SUM (HIGH) = 02H
D4H
SUM (LOW) = EAH
Calculation data
The data from which SUM is calculated is the RAM data from the first address
received to the last address received.
The received RAM write data is not the only data to be calculated for SUM.
Even when the received addresses are noncontiguous and there are some
unwritten areas, data in the entire memory area is calculated. The user program
should not contain unwritten gaps.
d. Notes on extended Intel Hex format (Binary)
1.
After receiving the checksum of a record, the device waits for the start mark (3AH
for “:”) of the next record. Therefore, the device ignores all data received between
records during that time unless the data is 3AH.
2.
Make sure that once the controller program has finished sending the checksum of
the end record, it does not send anything and waits for two byes of data to be
received (Upper and lower bytes of SUM). This is because after receiving the
checksum of the end record, the boot program calculates the SUM and returns the
calculated SUM in two bytes to the controller.
3.
It becomes the cause of incorrect operation to write to areas out of device’s
internal RAM. Therefore, when an extended record is transmitted, be sure to set a
paragraph address to 0000H.
4.
Always make sure the first record type is an extended record. Because the initial
value of the address pointer is 00H.
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5.
Transmit a user program not by the ASCII code but by binary. However, start
mark “:” is 3AH (ASCII code).
Example: Transmit data in the case of writing in 16-byte data from address 1060H
Data record
3A 10 1060 00 0607F100030000F201030000B1F16010 77
Data
Checksum
Record type
Address
Number of data
“:” (Start mark)
End record
3A 00 0000 01 FF
Checksum
Record type
Address
Number of data
“:” (Start mark)
e. Error when receiving user program
If the following errors occur in extended Intel Hex format when receiving the
user program, the device goes to an idle state.
•
When the record type is not 00H, 01H, 02H
•
When a checksum error occurs
f. Error between frequency measurement and baud rate
The boot program measures the resonator frequency when receiving matching
data. If an error is under 3%, the boot program decides on that frequency. Since
there is an overlap between the margin of 3% for 32.000 MHz and 33.868 MHz,
the boundary is set at the intermediate value between the two. The baud rate is
set based on the measured frequency. Each baud rate includes a set error shown in
Table 3.13.8. For example, in the case of 20.000 MHz and 9600 bps, the baud rate
is actually set at 9615.38 bps with an error of 0.2%. To establish communication,
the sum of the baud rate set error shown in Table 3.13.8 and the frequency error
need to be under 3%.
Table 3.13.8 Set Error of Each Baud Rate (%)
9600 bps
19200 bps
38400 bps
57600 bps
115200 bps
16.000 MHz
0.2
0.2
0.2
−0.6
−0.8
20.000 MHz
0.2
0.2
0.2
−0.2
0.9
22.579 MHz
0
0.7
0
25.000 MHz
−0.2
0.5
−0.1
32.000 MHz
0.1
0.2
0.2
33.868 MHz
0.2
0.2
0.2
0
0.7
36.000 MHz
0.2
0.2
−0.7
0.2
0.2
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(7) Ports setup of the boot program
Only ports shown in Table 3.13.9 are setup in the boot program. At the time of boot
program use, be careful of the influence on a user system. Do not use CS0 space and
P60 in the system which uses the boot program.
Other ports are not setting up, and are the reset state or the state of boot program
starting.
Table 3.13.9 Ports Setting List
Function
Input/output
P60
Ports
CS0
Output
High/low
−
P61
Port
Output
−
P62
Port
Output
High
P63
Port
Output
P80
Port
Input
High
P81
RXD0
Input
High
P82
Port
Input
−
P83
Port
Input
Low
P84
Port
Input
−
P85
Port
Input
−
P86
Port
Input
−
P87
Port
Input
−
Notes
CS0 space is 20000H to 201FFH.
−
Not open-drain port.
This port becomes TXD0 after matching data reception.
This port is set as the output and becomes RTS0 after
matching data reception.
−: Un-setting up
(8) Setting method of microcontroller peripherals
Although P83 has the RTS0 function, it is initially in a high-impedance state and
not set as RTS0 . To establish serial communication, attach a pull-down resistor to P83.
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4.
Electrical Characteristics
4.1
Maximum Ratings
Parameter
Symbol
Rating
Unit
−0.5 to 5.75
Power supply voltage (5 V)
HVcc
Power supply voltage (3 V)
LVcc
−0.5 to 4.0
Input voltage
VIN
−0.5 to Vcc + 0.5
Output current (Per pin)
IOL
2
Output current (Per pin)
IOH
−2
Output current (Total)
ΣIOL
80
Output current (Total)
ΣIOH
−80
Power dissipation (Ta = 85°C)
PD
600
Soldering temperature (10 s)
TSOLDER
Storage temperature
TSTG
−65 to 150
Operating temperature
TOPR
−20 to 70
V
mA
mW
260
°C
Note: The maximum ratings are rated values which must not be exceeded during operation, even for an
instant. Any one of the ratings must not be exceeded. If any maximum rating is exceeded, a device
may break down or its performance may be degraded, causing it to catch fire or explode resulting in
injury to the user. Thus, when designing products which include this device, ensure that no
maximum rating value will ever be exceeded.
Solderability of lead free products
Test
Test condition
Note
(1)
Use of Sn-37Pb solder Bath
Pass:
Solder bath temperature =230°C, Dipping time = 5 seconds
solderability rate until forming ≥ 95%
parameter
Solderability
The number of times = one, Use of R-type flux
(2)
Use of Sn-3.0Ag-0.5Cu solder bath
Solder bath temperature =245°C, Dipping time = 5 seconds
The number of times = one, Use of R-type flux (use of lead free)
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4.2
DC Characteristics (1/2)
Parameter
Symbol
Condition
Min
HVCC
fc = 10 to 36 MHz
LVCC
fc = 10 to 36 MHz
Typ. (Note)
Max
Unit
4.75
5.25
V
3.0
3.6
V
Power supply voltage (5 V)
(AVcc = HVcc)
(AVss = DVss = 0 V)
Power supply voltage (3 V)
D0 to D7, P10 to P17
Input low voltage
Input low voltage
(D8 to D15)
Other ports
HVIL
0.8
VIL1
0.3 HVcc
RESET , NMI
P56 (INT0), P70 (INT1)
P72 (INT2), P73 (INT3)
P75 (INT4), P90 (INT5)
−0.3
VIL2
0.25 HVcc
AM0, AM1
VIL3
0.3
X1
VIL4
0.2 LVcc
D0 to D7, P10 to P17 (D8
to D15)
VIH
2.2
Other ports
VIH1
0.7 HVcc
VIH2
0.75 HVcc
AM0, AM1
VIH3
HVcc − 0.3
X1
VIH4
0.8 LVcc
RESET , NMI
P56 (INT0), P70 (INT1)
P72 (INT2), P73 (INT3)
P75 (INT4), P90 (INT5)
V
HVcc + 0.3
Output low voltage
VOL
IOL = 1.6 mA
Output high voltage
VOH
IOH = −400 μA
LVcc + 0.3
0.45
V
4.2
Input leakage current
ILI
0.02
±5
0.0 ≤ VIN ≤ HVcc
Output leakage current
ILO
0.05
±10
0.2 ≤ VIN ≤ HVcc − 0.2
μA
Power down voltage
(at STOP, RAM back up)
VSTOP
2.0
3.6
VIL2 = 0.2 HVcc,
V IH2 = 0.8 HVcc
V
RESET pull-up resistor
RRST
40
200
HVcc = 5 V ± 5%
kΩ
10
fc = 1 MHz
pF
Pin capacitance
Schmitt width
RESET , NMI , INT0 to INT5
Programmable pull-up
resistor
CIO
VTH
0.4
RKH
40
V
1.0
HVcc = 5 V ± 5%
HVcc = 5 V ± 5%
LVcc = 3.0 to 3.6 V
fc = 36 MHz
mA
40
HVcc = 5 V ± 5%
LVcc = 3.0 to 3.6 V
Ta ≤ 70°C
μA
NORMAL (Note 2)
Icc
kΩ
200
IDLE2
20
IDLE1
14
STOP
100
Note 1: Typical values are for when Ta = 25°C, HVcc = 5.0 V and LVcc = 3.3 V unless otherwise noted.
Note 2: Icc measurement conditions (NORMAL):
All functions are operational; output pins are open and input pins are fixed.
91C829-167
2006-03-15
TMP91C829
4.3
AC Characteristics
(1) HVcc = 5.0 V ± 5%, LVcc = 3.0 to 3.6 V
No.
Parameter
fFPH = 36 MHz
Variable
Symbol
Min
Max
Min
27.6
100
27.6
Unit
Max
1
fFPH period ( = x )
2
A0 to A23 valid → RD / WR fall
tAC
x − 26
1.6
ns
3
RD rise → A0 to A23 hold
tCAR
0.5x −13.8
0.0
ns
4
WR rise → A0 to A23 hold
tCAW
x − 13
14.6
ns
5
A0 to A23 valid → D0 to D15 input
tAD
3.5x − 40
56.6
ns
6
RD fall → D0 to D15 input
tRD
2.5x − 34
35.0
ns
7
RD low width
tRR
8
RD rise → D0 to D15 hold
tHR
0
0
ns
9
WR low width
tWW
2.0x − 25
30.2
ns
10
D0 to D15 valid → WR rise
tDW
1.5x − 35
6.4
ns
11
WR rise → D0 to D15 hold
tWD
x − 25
12
A0 to A23 valid → WAIT input
13
RD / WR fall → WAIT hold
14
A0 to A23 valid → Port input
tAPH
15
A0 to A23 valid → Port hold
tAPH2
16
A0 to A23 valid → Port valid
tAPO
tFPH
(1+N) waits
(1+N) waits
2.5x − 25
tCW
44.0
ns
2.6
3.5x − 60
tAW
ns
2.5x + 0
ns
36.6
69.0
3.5x − 76
3.5x
ns
20.6
96.6
3.5x + 60
ns
ns
ns
156.6
ns
AC measuring conditions
Output level: High = 2.2 V, Low = 0.8 Vcc, CL = 50 pF
Input level:
High = 2.4 V, Low = 0.45 V (D0 to D15)
High 0.8 Vcc, Low 0.2 Vcc (except D0 to D15)
Note: Symbol “x” in the above table means the period of clock “fFPH”, it’s half period of the system clock
“fSYS” for CPU core. The period of fFPH depends on the clock gear setting.
91C829-168
2006-03-15
TMP91C829
(2) Read cycle
tFPH
fFPH
A0 to A23
CSn
tAW
tCW
WAIT
tAP
tAPH2
Port input
(Note)
tAD
RD
tCAR
tRR
tAC
tRD
D0 to D15
tHR
D0 to D15
Note: Since the CPU accesses the internal area to read data from a port, the control signals of external
pins such as RD and CS are not enabled. Therefore, the above waveform diagram should be
regarded as depicting internal operation. Please also note that the timing and AC characteristics
of port input/output shown above are typical representation. For details, contact your local
Toshiba sales representative.
91C829-169
2006-03-15
TMP91C829
(3) Write cycle
fFPH
A0 to A23
CSn
WAIT
tAPO
Port output
(Note)
tCAW
WR , WAIT
tWW
tDW
tWD
D0 to D15
D0 to D15
Note: Since the CPU accesses the internal area to write data to a port, the control signals of external
pins such as WR and CS are not enabled. Therefore, the above waveform diagram should be
regarded as depicting internal operation. Please also note that the timing and AC characteristics
of port input/output shown above are typical representation. For details, contact your local
Toshiba sales representative.
91C829-170
2006-03-15
TMP91C829
4.4
AD Conversion Characteristics
AVcc = HVcc, AVss = Vss
Parameter
Symbol
Min
Typ.
Analog reference voltage (+)
VREFH
HVCC − 0.2 V
HVCC
HVCC
Analog reference voltage (−)
VREFL
DVSS
DVSS
DVss + 0.2 V
VAIN
VREFL
Analog input voltage range
Analog current for analog
Reference voltage
<VREFON> = 1
IREF
(VREFL = 0V)
<VREFON> = 0
Error
(Not including quantizing errors)
−
Max
Unit
V
VREFH
0.85
1.20
mA
0.02
5.0
μA
± 1.0
± 4.0
LSB
Note 1: 1 LSB = (VREFH − VREFL)/1024 [V]
Note 2: The value for Icc includes the current which flows through the AVcc pin.
91C829-171
2006-03-15
TMP91C829
4.5
Serial Channel Timing (I/O internal mode)
Note: Symbol “x” in the above table means the period of clock “fFPH”, it’s half period of the system clock
“fSYS” for CPU core. The period of fFPH depends on the clock gear setting.
(1) SCLK input mode
Parameter
36 MHz
(Note) Unit
Min Max
Variable
Symbol
Min
Max
SCLK period
tSCY
16X
0.44
μs
Output data → SCLK rising/falling edge*
tOSS
tSCY/2 − 4X − 85
25
ns
SCLK rising/falling edge* → Output data hold
tOHS
tSCY/2 + 2X + 0
276
ns
SCLK rising/falling edge* → Input data hold
tHSR
3X + 10
SCLK rising/falling edge* → Valid data input
tSRD
Valid data input → SCLK rising/falling edge*
tRDS
92
tSCY − 0
ns
440
0
ns
0
ns
*) SCLK rising/falling edge: The rising edge is used in SCLK rising mode.
The falling edge is used in SCLK falling mode.
Note: at tSCY = 16X
(2) SCLK output mode
Parameter
Min
Max
36 MHz
(Note) Unit
Min Max
8192X
0.44
μs
ns
Variable
Symbol
SCLK period (Programable)
tSCY
16X
Output data → SCLK rising/falling edge*
tOSS
tSCY/2 − 40
180
SCLK rising/falling edge* → Output data hold
tOHS
tSCY/2 − 40
180
ns
SCLK rising/falling edge* → Input data hold
tHSR
0
0
ns
SCLK rising/falling edge* → Valid data input
tSRD
Valid data input → SCLK rising/falling edge*
tRDS
tSCY/2 − 1X − 90
1X + 90
324
ns
117
ns
*) SCLK rising/falling edge: The rising edge is used in SCLK rising mode.
The falling edge is used in SCLK falling mode.
Note: at tSCY = 16X
tSCY
SCLK
SCLK
tOHS
tOSS
Output data
TXD
0
1
tSRD
Input data
RXD
0
Valid
91C829-172
tRDS
1
Valid
2
3
tHSR
2
3
Valid
Valid
2006-03-15
TMP91C829
4.6
Event Counter (TA0IN, TA4IN, TB0IN0, TB0IN1)
Parameter
Symbol
Variable
Min
Max
36 MHz
Min
Max
Unit
Clock perild
tVCK
8X + 100
320
ns
Clock low level width
tVCKL
4X + 40
150
ns
Clock high level width
tVCKH
4X + 40
150
ns
Note: Symbol “x” in the above table means the period of clock “fFPH”, it’s half period of the system clock
“fSYS” for CPU core. The period of fFPH depends on the clock gear setting .
4.7
Interrupts
Note: Symbol “x” in the above table means the period of clock “fFPH”, it’s half period of the system
clock “fSYS” for CPU core. The period of fFPH depends on the clock gear setting.
(1) NMI , INT0 to INT5 interrupts
Parameter
Symbol
Variable
Min
Max
36 MHz
Min
Max
Unit
NMI , INT0 to INT5 low level width
tINTAL
4X + 40
150
ns
NMI , INT0 to INT5 high level width
tINTAH
4X + 40
150
ns
91C829-173
2006-03-15
TMP91C829
4.8
Bus Request/Bus Acknowledge
BUSRQ
(Note 1)
tCBAL
BUSAK
tBAA
tABA
D0 to D15
(Note 2)
A0 to A23,
RD , WR
(Note 2)
CS0 to CS3 ,
HWR
Parameter
Variable
Symbol
fFPH = 36 MHz
Min
Max
Min
Max
Unit
Output buffer to BUSAK low
tABA
0
80
0
80
ns
BUSAK high to output buffer on
tBAA
0
80
0
80
ns
Note 1: Even if the BUSRQ signal goes low, the bus will not be released while the WAIT signal is low.
The bus will only be released when BUSRQ goes low while WAIT is high.
Note 2: This line shows only that the output buffer is in the off state.
It does not indicate that the signal level is fixed.
Just after the bus is released, the signal level set before the bus was released is maintained
dynamically by the external capacitance. Therefore, to fix the signal level using an external
resister during bus release, careful design is necessary, since fixing of the level is delayed.
The internal programmable pull-up/pull-down resistor is switched between the active and
non-active states by the internal signal.
91C829-174
2006-03-15
TMP91C829
5.
Table of SFRs
The special function registers (SFRs) include the I/O ports and peripheral control registers
allocated to the 4-Kbyte address space from 000000H to 000FFFH.
(1) I/O port
(2) I/O port control
(3) Interrupt control
(4) Chip select/wait control
(5) Clock gear
(6) 8-bit timer
(7) 16-bit timer
(8) UART/serial channel
(9) AD converter
(10) Watchdog timer
(11) Multi vector controller
Table layout
Symbol
Name
Address
7
6
1
0
Bit symbol
Read/Write
Initial value after Reset
Remarks
Note: “Prohibit RMW” in the a table means that you cannot use RMW instructions on these register.
Example: When setting bit0 only of the register PxCR, the instruction “SET 0, (PxCR)” cannot be
used. The LD (Transfer) instruction must be used to write all eight bits.
Read/Write
R/W: Both read and write are possible.
R:
Only read is possible.
W:
Only write is possible.
W*: Both read and write are possible (when this bit is read as 1).
Prohibit RMW: Read-modify-write instructions are prohibited. (The EX, ADD, ADC, BUS,
SBC, INC, DEC, AND, OR, XOR, STCF, RES, SET, CHG, TSET, RLC, RRC,
RL, RR, SLA, SRA, SLL, SRL, RLD, and RRD instruction are
read-modify-write instructions.)
R/W*:
Read-modify-write is prohibited when controlling the pull-up resistor.
91C829-175
2006-03-15
TMP91C829
Table 5.1 Address Map SFRs
[1] PORT
Address
0000H
1H
2H
3H
4H
5H
6H
7H
8H
9H
AH
BH
CH
DH
EH
FH
Name
P1
P1CR
P2
P2FC
P5
Address
0010H
1H
2H
3H
4H
5H
6H
7H
8H
9H
AH
BH
CH
DH
EH
FH
Name
P5CR
P5FC
P6
P7
P6CR
P6FC
P7CR
P7FC
P8
P9
P8CR
P8FC
P9CR
P9FC
PA
Address
Name
0020H
1H
2H
3H
4H
5H
6H
7H
8H
9H
AH
BH
CH
DH
EH
FH ODE
Address
Name
0070H
1H
2H
3H
4H
5H
6H
7H
8H
9H
AH
BH
CH
DH PZ
EH PZCR
FH PZFC
[2] INTC
Address
0080H
1H
2H
3H
4H
5H
6H
7H
8H
9H
AH
BH
CH
DH
EH
FH
Name
DMA0V
DMA1V
DMA2V
DMA3V
INTCLR
DMAR
DMAB
IIMC0
IIMC1
Address
0090H
1H
2H
3H
4H
5H
6H
7H
8H
9H
AH
BH
CH
DH
EH
FH
Name
INTE0AD
INTE12
INTE34
INTE5
INTETA01
INTETA23
INTETA45
INTETB0
INTETB0V
INTES0
INTES1
Address
00A0H
1H
2H
3H
4H
5H
6H
7H
8H
9H
AH
BH
CH
DH
EH
FH
Name
INTETC01
INTETC23
MVEC0
MVEC1
Note: Do not access to the unnamed addresses (e.g., addresses to which no register has been allocated).
91C829-176
2006-03-15
TMP91C829
[3] CS/WAIT
Address
00C0H
1H
2H
3H
4H
5H
6H
7H
8H
9H
AH
BH
CH
DH
EH
FH
[4] CGEAR, DFM
Name
B0CS
B1CS
B2CS
B3CS
BEXCS
MSAR0
MAMR0
MSAR1
MAMR1
MSAR2
MAMR2
MSAR3
MAMR3
Address
00E0H
1H
2H
3H
4H
5H
6H
7H
8H
9H
AH
BH
CH
DH
EH
FH
Name
SYSCR0
SYSCR1
SYSCR2
EMCCR0
EMCCR1
Address
0110H
1H
2H
3H
4H
5H
6H
7H
8H
9H
AH
BH
CH
DH
EH
FH
Name
TA45RUN
[5] TMRA
Address
0100H
1H
2H
3H
4H
5H
6H
7H
8H
9H
AH
BH
CH
DH
EH
FH
Name
TA01RUN
TA0REG
TA1REG
TA01MOD
TA1FFCR
TA23RUN
TA2REG
TA3REG
TA23MOD
TA3FFCR
TA4REG
TA5REG
TA45MOD
TA5FFCR
Note: Do not access to the unnamed addresses (e.g., addresses to which no register has been allocated).
91C829-177
2006-03-15
TMP91C829
[6] TMRB
Address
0180H
1H
2H
3H
4H
5H
6H
7H
8H
9H
AH
BH
CH
DH
EH
FH
[7] UART/SIO
Name
TB0RUN
TB0MOD
TB0FFCR
TB0RG0L
TB0RG0H
TB0RG1L
TB0RG1H
TB0CP0L
TB0CP0H
TB0CP1L
TB0CP1H
Address
0200H
1H
2H
3H
4H
5H
6H
7H
8H
9H
AH
BH
CH
DH
EH
FH
Name
SC0BUF
SC0CR
SC0MOD0
BR0CR
BR0ADD
SC0MOD1
SC1BUF
SC1CR
SC1MOD0
BR1CR
BR1ADD
SC1MOD1
[8] 10-Bit ADC
Address
02A0H
1H
2H
3H
4H
5H
6H
7H
8H
9H
AH
BH
CH
DH
EH
FH
Name
ADREG04L
ADREG04H
ADREG15L
ADREG15H
ADREG26L
ADREG26H
ADREG37L
ADREG37H
Address
02B0H
1H
2H
3H
4H
5H
6H
7H
8H
9H
AH
BH
CH
DH
EH
FH
Name
ADMOD0
ADMOD1
Note: Do not access to the unnamed addresses (e.g., addresses to which no register has been allocated).
[9] WDT
Address
0300H
1H
2H
3H
4H
5H
6H
7H
8H
9H
AH
BH
CH
DH
EH
FH
Name
WDMOD
WDCR
Note: Do not access to the unnamed addresses (e.g., addresses to which no register has been allocated).
91C829-178
2006-03-15
TMP91C829
(1) I/O port
Symbol
Name
Address
P1
Port 1
01H
7
6
5
4
P17
P16
P15
P14
3
2
1
0
P13
P12
P11
P10
R/W
Data from external port (Output latch register is cleared to 0.)
P2
Port 2
P27
P26
P25
P24
P23
P22
P21
P20
1
1
1
1
P56
P55
1
1
1
1
P54
P53
P61
P60
06H
R/W
R/W*
P5
Port 5
0DH
Data from external port (Output latch register is set to 1.)
0(Output latch register): Pull-up resistor OFF
1(Output latch register): Pull-up resistor ON
P63
P6
Port 6
R/W
P75
P7
Port 7
P62
12H
P74
1
0
1
1
P73
P72
P71
P70
13H
R/W
Data from external port (Output latch register is set to 1.)
P87
P86
P85
P84
P83
P82
P81
P80
R/W
P8
Port 8
18H
Data from external port (Output latch register is set to 1.)
0(Output latch register): Pull-up resistor OFF
1(Output latch register): Pull-up resistor ON
P96
P95
P94
P93
P90
R/W
R/W
Data from
P9
Port 9
19H
external port
Data from external port
(Output latch
(Output latch register is set to 1.)
register is set
to 1.)
PA7
PA
Port A
PA6
PA5
PA4
1EH
PA3
PA2
PA1
PA0
R
Data from external port
PZ3
PZ2
R/W
PZ
Port Z
7DH
Data from external port
(Output latch register is
set to 1.)
91C829-179
2006-03-15
TMP91C829
(2) I/O port control (1/2)
Symbol
P1CR
Name
Port 1
control
Address
7
6
5
4
P17C
P16C
P15C
P14C
04H
0/1
0/1
0/1
P27F
P26F
P25F
0/1
0: Input
P2FC
Port 2
function
09H
(Prohibit
RMW)
2
1
0
P13C
P12C
P11C
P10C
0/1
0/1
0/1
0/1
P23F
P22F
P21F
P20F
1
1
1
1
P61F
P60F
W
(Prohibit
RMW)
3
1: Output
P24F
W
1
1
1
1
0: Port 1: Address bus (A23 to A16)
P5CR
Port 5
control
P56C
P55C
0
0
10H
RMW)
P56F
Port 5
function
P53C
0
0
W
(Prohibit
0: Input
P5FC
P54C
11H
1: Output
P54F
W
(Prohibit
0
RMW)
P53F
W
0
0: Port
0: Port
1: BUSAK
1: INT0
0
0: Port
1: BUSRQ
P63F
P6FC
P7CR
Port 6
function
Port 7
control
P62F
15H
W
(Prohibit
RMW)
P75C
16H
0
0
0
0
0: Port
1: CS3
0: Port
1: CS2
0: Port
1: CS1
0: Port
1: CS0
P74C
P73C
(Prohibit
RMW)
0
0
0
P75F
W
0
P74F
W
0
P73F
W
0
0 : Input
P7FC
Port 7
function
P72F2
W
0
17H
(Prohibit
RMW)
0: Port
1: INT2
P87C
P8CR
Port 8
1AH
control
(Prohibit
P86C
Port 8
function
P71C
P70C
0
0
0
P71F
W
0
P70F
W
0
0: Port
1: INT4
P85C
0: Port
0: Port
1: TA5OUT 1: INT3
P84C
1 : Output
P72F1
W
0
0: Port
0: Port
0: Port
1: TA3OUT 1: TA1OUT 1: INT1
P83C
P82C
P81C
P80C
0
0
0
0
W
0
0
0
0
0: Input
RMW)
P8FC
P72C
W
1: Output
1BH
P87F
W
P86F
W
P84F
W
P83F
W
P82F
W
P80F
W
(Prohibit
0
0
0
0
0
0
RMW)
0: Port
1: STS1
0: Port
1: SCLK1
0: Port
1: TXD1
91C829-180
0: Port
1: STS0
0: Port
1: SCLK0
0: Port
1: TXD0
2006-03-15
TMP91C829
I/O port control (2/2)
Symbol
P9CR
P9FC
PZCR
Name
Port 9
control
Port 9
function
Port Z
control
Address
7
6
5
4
3
P96C
P95C
P94C
P93C
0
0
0
0
1CH
(Prohibit
(Prohibit
RMW)
0: Input
P96F
W
0
1
0
P90C
W
RMW)
1DH
2
W
0
0: Input
1: Output
1: Output
P95F
W
0
P90F
W
0
0: Port
0: Port
1: TB0OUT1 1: TB0OUT0
0: Port
1: INT5
PZ3C
7EH
PZ2C
W
(Prohibit
0
RMW)
0: Input
0
1: Output
PZ2F
PZFC
ODE
Port Z
function
Serial
open drain
7FH
W
(Prohibit
0
RMW)
2FH
(Prohibit
RMW)
0: Port
1: HWR
ODE84
ODE80
W
W
0
1: P84ODE
91C829-181
0
1: P80ODE
2006-03-15
TMP91C829
(3) Interrupt control (1/3)
Symbol
Name
Address
7
6
IADM2
90H
IADC
R
5
4
3
2
IADM1
IADM0
I0C
R
I0M2
INTAD
Interrupt
INTE0AD enable
0 & AD
0
1: INTAD
INTE12
enable
2/1
91H
I2C
R
0
1: INT2
enable
4/3
92H
I4C
R
0
1: INT4
I0M0
0
1: INT0
INT1
I2M1
I2M0
R/W
0
0
0
Interrupt request level
I4M2
I0M1
R/W
0
0
0
Interrpt request level
I1C
R
I1M2
I1M1
I1M0
R/W
0
0
0
Interrpt request level
0
1: INT1
INT4
Interrupt
INTE34
R/W
0
0
0
Interrpt request level
I2M2
0
INT0
INT2
Interrupt
1
INT3
I4M1
I4M0
R/W
0
0
0
Interrupt request level
I3C
R
I3M2
I3M1
I3M0
R/W
0
0
0
Interrpt request level
0
1: INT3
INT5
Interrupt
INTE5
enable 5
I5C
R
93H
I5M2
0
INTTA1 (TMRA1)
INTETA01
enable
timer A
95H
0
1: INTTA1
1/0
enable
timer A
96H
timer A
97H
timer B0
INTTA0 (TMRA0)
ITA1M0
R/W
0
0
0
Interrpt request level
99H
ITB01C
R
0
1: INTTB01
enable
timer B0
ITA0M2
0
1: INTTA0
ITA3M2
ITA3M1
ITA3M0
R/W
0
0
0
Interrpt request level
ITA5M2
ITA5M1
ITB01M1
ITA0M0
R/W
0
0
0
Interrpt request level
ITA2C
R
ITA2M2
0
1: INTTA2
ITA2M1
ITA2M0
R/W
0
0
0
Interrpt request level
INTTA4 (TMRA4)
ITA5M0
R/W
0
0
0
Interrpt request level
ITB01M2
ITA0M1
INTTA2 (TMRA2)
ITA4C
R
ITA4M2
0
1: INTTA4
ITA4M1
ITA4M0
R/W
0
0
0
Interrpt request level
INTTB00 (TMRB0)
ITB01M0
R/W
0
0
0
Interrpt request level
ITB00C
R
ITB00M2
0
1: INTTB00
ITB00M1
ITB00M0
R/W
0
0
0
Interrpt request level
INTTBOF0 (TMRB0 overflow)
Interrupt
INTETB0V
ITA0C
R
INTTB01 (TMRB0)
Interrupt
enable
ITA5C
R
0
1: INTTA5
5/4
INTETB0
ITA1M1
INTTA5 (TMRA5)
Interrupt
enable
ITA3C
R
0
1: INTTA3
3/2
INTETA45
ITA1M2
INTTA3 (TMRA3)
Interrupt
INTETA23
ITA1C
R
I5M0
R/W
0
0
0
Interrpt request level
1: INT5
Interrupt
I5M1
ITF0C
R
9BH
0
(overflow)
1: INTTBOF0
91C829-182
ITF0M2
ITF0M1
ITF0M0
R/W
0
0
0
Interrpt request level
2006-03-15
TMP91C829
Interrupt control (2/3)
Symbol
Name
Address
7
6
ITX0C
ITX0M2
5
4
3
2
ITX0M1
ITX0M0
IRX0C
IRX0M2
INTTX0
Interrupt
INTES0
enable
9CH
serial 0
R
0
0
INTES1
enable
ITX1C
0
0
Interrpt request level
9DH
serial 1
ITX1M2
0
0
0
1: INTRX0
1: INTTX1
A0H
TC0/1
ITC1C
0
IRX1M2
0
Interrpt request level
ITC1M2
A1H
ITC3C
0
0
1: INTRX1
ITC1M0
R/W
0
0
0
Interrpt request level
ITC0C
ITC0M2
ITC0M1
0
ITC0M0
R/W
0
0
0
ITC2M1
ITC2M0
ITC2M0
ITC3M1
ITC3M0
R/W
0
IRX1M0
0
R
0
ITC3M2
R
IRX1M1
INTTC0
ITC1M1
0
0
R/W
INTTC3
Interrupt
INTETC23 enable
TC2/3
IRX1C
R
0
R
0
Interrpt request level
INTTC1
Interrupt
INTETC01 enable
ITX1M0
R/W
0
IRX0M0
R/W
INTRX1
ITX1M1
R
IRX0M1
R
INTTX1
Interrupt
0
INTRX0
R/W
1: INTTX0
1
0
91C829-183
ITC2C
ITC2M2
R
0
0
R/W
0
0
0
2006-03-15
TMP91C829
Interrupt control (3/3)
Symbol
Name
Address
7
6
DMA 0
DMA0V
request
5
4
3
DMA0V5
DMA0V4
DMA0V3
2
1
0
DMA0V2
DMA0V1
DMA0V0
0
0
0
DMA1V2
DMA1V1
DMA1V0
0
0
0
DMA2V2
DMA2V1
DMA2V0
0
0
0
DMA3V2
DMA3V1
DMA3V0
0
0
0
CLRV2
CLRV1
CLRV0
0
0
0
R/W
80H
0
vector
0
0
DMA0 start vector
DMA1V5
DMA 1
DMA1V
request
DMA1V4
DMA1V3
R/W
81H
0
vector
0
0
DMA1 start vector
DMA2V5
DMA 2
DMA2V
request
DMA2V4
DMA2V3
R/W
82H
0
vector
0
0
DMA2 start vector
DMA3V5
DMA 3
DMA3V
request
DMA3V4
DMA3V3
R/W
83H
0
vector
0
0
DMA3 start vector
Interrupt
INTCLR clear
control
88H
CLRV5
CLRV4
CLRV3
0
0
0
W
(Prohibit
RMW)
Clear interrupt request DMA flag by writing to DMA start vector.
DMA
DMAR
software
request
89H
DMAR3
DMAR2
DMAR1
DMAR0
R/W
R/W
R/W
R/W
0
0
0
0
register
1: DMA request in software
DMA
DMAB
burst
request
8AH
DMAB3
DMAB2
DMAB1
DMAB0
R/W
R/W
R/W
R/W
0
0
0
0
register
Interrupt
IIMC0
1 : DMA request on burst mode
8CH
input
mode
control 0
(Prohibit
RMW)
−
I2EDGE
I2LE
I1EDGE
I1LE
I0EDGE
I0LE
NMIREE
W
W
W
W
W
W
W
W
0
0
0
0
0
0
0
0
1: NMI
Always
INT2 edge
INT2
INT1 edge
INT1
INT0 edge
INT0
write “0”.
0: Rising
0: Edge
0: Rising
0: Edge
0: Rising
0: Edge
operation
1: Falling
1: Level
1: Falling
1: Level
1: Falling
1: Level
even on
NMI rising
edge
Interrupt
IIMC1
8DH
I5EDGE
I5LE
I4EDGE
I4LE
I3EDGE
I3LE
W
W
W
W
W
W
0
input
mode
control 1
(Prohibit
RMW)
0
0
0
0
0
INT5
INT5
INT4
INT4
INT3
INT3
edge
0: Edge
edge
0: Edge
edge
0: Edge
0: Rising
1: Level
0: Rising
1: Level
0: Rising
1: Level
1: Falling
1: Falling
91C829-184
1: Falling
2006-03-15
TMP91C829
(4) Chip select/wait control (1/2)
Symbol
Name
Address
7
6
5
4
3
2
1
0
B0CS
Block 0
CS/WAIT
control
register
B0E
W
C0H
0
0:
Disable
(Prohibit
RMW) 1: Enable
B0OM1
B0OM0
W
W
0
0
00: ROM/SRAM
01:
10:
Reserved
11:
B0BUS
W
0
Data bus
width
0: 16 bits
1: 8 bits
B0W2
B0W1
B0W0
W
W
W
0
0
0
000: 2 waits
001: 1 wait
010: (1 + N) waits 1xx: Reserved
011: 0 waits
B1CS
Block 1
CS/WAIT
control
register
B1E
W
C1H
0
(Prohibit 0: Disable
RMW) 1: Enable
B1OM1
B1OM0
W
W
0
0
00: ROM/SRAM
01:
10:
Reserved
11:
B1BUS
W
0
Data bus
width
0: 16 bits
1: 8 bits
B1W2
B1W1
B1W0
W
W
W
0
0
0
000: 2 waits
001: 1 wait
010: (1 + N) waits 1xx: Reserved
011: 0 waits
B2CS
Block 2
CS/WAIT
control
register
B2E
W
C2H
1
0:
Disable
(Prohibit
RMW) 1: Enable
B2OM1
B2OM0
W
W
0
0
00: ROM/SRAM
01:
10:
Reserved
11:
B2BUS
W
0
Data bus
width
0: 16 bits
1: 8 bits
B2W2
B2W1
B2W0
W
W
W
0
0
0
000: 2 waits
001: 1 wait
010: (1 + N) waits 1xx: Reserved
011: 0 waits
B3CS
Block 3
CS/WAIT
control
register
B3E
W
C3H
0
0:
Disable
(Prohibit
RMW) 1: Enable
B3OM1
B3OM0
W
W
0
0
00: ROM/SRAM
01:
10:
Reserved
11:
B3BUS
W
0
Data bus
width
0: 16 bits
1: 8 bits
B3W2
B3W1
B3W0
W
W
W
0
0
0
000: 2 waits
001: 1 wait
010: (1 + N) waits 1xx: Reserved
011: 0 waits
BEXBUS
W
0
Data bus
width
0: 16 bits
1: 8 bits
BEXW2
BEXW1
BEXW0
W
W
W
0
0
0
000: 2 waits
001: 1 wait
010: (1 + N) waits 1xx: Reserved
011: 0 waits
BEXCS
External
CS/WAIT
control
register
MSAR0
Memory
start
address
register 0
Memory
address
MAMR0
mask
register 0
MSAR1
Memory
start
address
register 1
Memory
address
MAMR1
mask
register 1
B2M
W
0
0: 16 M
space
1: Area
setting
C7H
(Prohibit
RMW)
S23
C8H
C9H
CAH
CBH
S22
S21
S20
S19
S18
S17
S16
1
1
1
V15
V14~9
V8
1
1
S18
S17
S16
1
1
1
V16
V15~9
V8
R/W
1
1
1
V20
V19
V18
1
1
Start address A23 to A16
V17
V16
R/W
1
1
S23
S22
1
CS0 Area size
1
1
1
0: Enable to address comparision
S21
S20
S19
R/W
1
1
1
V21
V20
V19
1
1
Stat address A23 to A16
V18
V17
R/W
1
1
1
CS1area size
1
1
1
0: Enable to address comparsion
91C829-185
1
2006-03-15
TMP91C829
Chip select/wait control (2/2)
Symbol
Name
MSAR2
Memory
start
address
register 2
Memory
address
MAMR2
mask
register 2
MSAR3
Memory
start
address
register 3
Memory
address
MAMR3
mask
register 3
Address
CCH
CDH
CEH
CFH
7
6
5
4
3
2
1
0
S23
S22
S21
S20
S19
S18
S17
S16
1
1
1
1
1
1
V22
V21
V20
V17
V16
V15
1
1
S18
S17
S16
1
1
1
V17
V16
V15
1
1
R/W
1
1
Start address A23 to A16
V19
V18
R/W
1
1
S23
S22
1
CS2 area size
S21
1
1
1
0: Enable address comparsion
S20
S19
R/W
1
1
1
V22
V21
V20
1
1
Start address A23 to A16
V19
V18
R/W
1
1
1
CS3 area size
91C829-186
1
1
1
0: Enable to address comparsion
2006-03-15
TMP91C829
(5) Clock gear
Symbol
Name
Address
7
6
5
4
3
2
1
0
−
−
−
−
−
WUEF
PRCK1
PRCK0
1
0
1
0
0
0
Warm-up
timer
0 Write:
Don’t care
Write:
Start timer
Read: End
warm-up
Read:
Not end
warm-up
0
0
R/W
System
clock
SYSCR0
control
register 0
Always
Always
Always
Always
Always
write “1”.
write “0”.
write “1”.
write “0”.
write “0”.
E0H
−
Prscaler clock seleciton
00: fFPH
01: Reserved
10: fc/16
11: Reserved
GEAR2
GEAR1
GEAR0
R/W
0
Always
System
clock
SYSCR1
control
register 1
System
clock
SYSCR2
control
register 2
write “0”.
E1H
−
R/W
0
E2H
WUPTM1
R/W
1
WUPTM0
R/W
0
1
0
0
High-frequency gear value selection
(fc)
000: fc
001: fc/2
010: fc/4
011: fc/8
100: fc/16
101: (Reserved)
110: (Reserved)
111: (Reserved)
HALTM1
R/W
1
HALTM0
R/W
1
Always
Warming-up time
00: Reserved
write “0”.
00: Reserved
01: STOP mode
8
10: IDLE1 mode
14
11: IDLE2 mode
01: 2 /input frequency
10: 2 /input frequency
DRVE
R/W
0
1: Drive the
pin in
STOP
mode
16
11: 2 /input frequency
EMC
EMCCR0 control
register 0
PROTECT
R
0
E3H
−
R/W
0
−
R/W
1
−
R/W
0
−
R/W
0
Protection
Always
Always
Always
Always
flag
write “0”.
write “1”.
write “0”.
wirte “0”.
0: OFF
−
R/W
1
−
R/W
1
Always
Always
EXTIN
R/W
0
1: fc is
external write “1”.
write “1”.
clock.
1: ON
EMC
EMCCR1 control
register 1
E4H
Protection is turned off by writing 1FH.
Protection is turned on by writing any value other than 1FH.
Note: EMCCR1
If protection is on, write operations to the following SFRs are not possible.
1. CS/WAIT control
B0CS, B1CS, B2CS, B3CS, BEXCS,
MSAR0, MSAR1, MSAR2, MSAR3,
MAMR0, MAMR1, MAMR2, and MAMR3
2. Clock gear (Only EMCCR1 can be written to)
SYSCR0, SYSCR1, SYSCR2 and EMCCR0
91C829-187
2006-03-15
TMP91C829
(6) 8-bit timer (1/2)
(6−1) TMRA01
Symbol
Name
Address
7
100H
TA0RDE
R/W
0
Double
buffer
0: Disable
1: Enable
8-bit
TA01RUN timer
RUN
8-bit
TA0REG timer
register 0
8-bit
TA1REG timer
register 1
6
RMW)
RMW)
104H
CLK &
MODE
TA1FFCR
TA01M0
0
00: 8-bit timer
01: 16-bit timer
10: 8-bit PPG
11: 8-bit PWM
0
PWM01
PWM00
TA1CLK1 TA1CLK0
R/W
0
0
0
0
00: Reserved
00: TA0TRG
6
01: 2 PWM cycle
01: φT1
7
10: φT16
10: 2
8
11: φT256
11: 2
TA1FFC1 TA1FFC0
R/W
1
1
00: Invert TA1FF
01: Set TA1FF
10: Clear TA1FF
11: Don’t care
105H
timer
flip-flop
(Prohibit
control
RMW)
2
1
0
−
W
Undefined
103H
(Prohibit
timer
3
−
W
Undefined
102H
(Prohibit
TA01M1
8-bit
4
I2TA01 TA01PRUN TA1RUN
TA0RUN
R/W
R/W
R/W
R/W
0
0
0
0
IDLE2
8-bit timer run/stop control
0: Stop
0: Stop and clear
1: Operate
1: Run (Count up)
8-bit
TA01MOD source
5
TA0CLK1
TA0CLK0
0
00: TA0IN pin
01: φT1
10: φT4
11: φT16
0
TA1FFIE
TA1FFIS
R/W
0
0
1: TA1FF
0: TMRA0
invert
1: TMRA1
enable
inversion
(6−2) TMRA23
Symbol
Name
8-bit
TA23RUN timer
RUN
Address
7
108H
TA2RDE
R/W
0
Double
buffer
0: Disable
1: Enable
6
5
4
3
10AH
(Prohibit
RMW)
−
W
Undefined
8-bit
TA3REG timer
register 1
10BH
(Prohibit
RMW)
−
W
Undefined
TA23M1
8-bit
timer
TA3FFCR
flip-flop
control
10CH
1
0
I2TA23
TA23PRUN TA3RUN
TA2RUN
R/W
R/W
R/W
R/W
0
0
0
0
IDLE2
8-bit timer run/stop control
0: Stop
0: Stop and clear
1: Operate
1: Run (Count up)
8-bit
TA2REG timer
register 0
8-bit
timer
TA23MOD source
CLK &
MODE
2
TA23M0
0
00: 8-bit timer
01: 16-bit timer
10: 8-bit PPG
11: 8-bit PWM
0
PWM21
PWM20
0
0
00: Reserved
6
01: 2 PWM cycle
7
10: 2
8
11: 2
TA3CLK1 TA3CLK0
R/W
0
0
00: TA2TRG
01: φT1
10: φT16
11: φT256
TA3FFC1 TA3FFC0
R/W
1
1
00: Invert TA3FF
01: Set TA3FF
10: Clear TA3FF
11: Don’t care
10DH
(Prohibit
RMW)
91C829-188
TA2CLK1
TA2CLK0
0
00: Reserved
01: φT1
10: φT4
11: φT16
0
TA3FFIE
TA3FFIS
R/W
0
0
1: TA3FF
0: TMRA2
invert
1: TMRA3
enable
inversion
2006-03-15
TMP91C829
8-bit timer (2/2)
(6-3) TMRA45
Symbol
Name
Address
8-bit
TA45RUN timer
RUN
110H
3
2
1
TA4RDE
7
6
5
4
I2TA45
TA45PRUN
TA5RUN
0
TA4RUN
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
Double
IDLE2
8-bit timer run/stop control
buffer
0: Stop
0: Stop and clear
0: Disable
1: Operate 1: Run (Count up)
1: Enable
8-bit
TA4REG timer
register 0
8-bit
TA5REG timer
register 1
112H
−
(Prohibit
W
RMW)
Undefined
113H
−
(Prohibit
W
RMW)
Undefined
TA45M1
TA45M0
PWM41
PWM40
0
0
0
0
8-bit
114H
TA4CLK0
0
0
0
0
00: TA4IN pin
6
01: φT1
01: φT1
7
10: φT16
10: φT4
8
11: φT256
00: Reserved
CLK &
01: 16-bit timer
01: 2 PWM cycle
MODE
10: 8-bit PPG
10: 2
11: 8-bit PWM
11: 2
TA5FFC1
TA5FFCR
TA4CLK1
00: TA4TRG
00: 8-bit timer
8-bit
TA5CLK0
R/W
timer
TA45MOD source
TA5CLK1
1
timer
(Prohibit
control
RMW)
TA5FFIE
R/W
115H
flip-flop
11: φT16
TA5FFC0
TA5FFIS
R/W
1
0
0
00: Invert TA5FF
1: TA5FF
0: Timer4
01: SET TA5FF
invert
1: Timer5
10: Clear TA5FF
enable
inversion
11: Don’t care
91C829-189
2006-03-15
TMP91C829
(7) 16-bit timer (1/2)
(7-1) TMRB0
Symbol
Name
8-bit
TB0RUN timer
Address
180H
control
16-Bit
timer
TB0MOD source
CLK
182H
(Prohibit
RMW) Invert when
TB0FFCR
timer
flip-flop
control
5
4
TB0CP0I
W*
1
TB0CPM1
TB0CPM0
3
2
1
0
I2TB0
TB0PRUN
TB0RUN
R/W
R/W
R/W
0
0
0
16-bit timer run/stop control
IDLE2
0: Stop and clear
0: Stop
1: Run (Count up)
1: Operate
0
0
0: Soft
Capture timing
capture
(TB0IN0, TB0IN1)
1: Undefined 00: Disable
TB0FF1C1 TB0FF1C0 TB0C1T1
W*
1
1
0
00: Invert TB0FF1
183H 01: Set
10: Clear
(Prohibit 11: Don’t care
Invert when
RMW) Always read as “11”.
TB0C0T1 TB0E1T1
R/W
0
0
TB0FF0 invert trigger
0: Trigger disable
1: Trigger enable
TB0E0T1
Invert when
Invert when
Invert when
is loaded
matches the
into TB0CP1. into TB0CP0. value in
TB0RG1.
TB0RG1H
TB0CP0L
189H
(Prohibit
register 0H RMW)
16-bit timer
18AH
(Prohibit
register 1L RMW)
16-bit timer
18BH
(Prohibit
register 1H RMW)
16-bit timer
Capture
18CH
register 0L
TB0CP0H
Capture
18DH
register 0H
TB0CP1L
Capture
18EH
register 1L
TB0CP1H
Capture
TB0CLK0
0
Source clock
0
00: TB0IN0 pin
01: φT1
10: φT4
11: φT16
TB0FF0C1 TB0FF0C0
W*
0
0
00: Invert TB0FF0
01: Set
10: Clear
11: Don’t care
Always read as “11”.
matches the
value in
TB0RG0.
−
W
Undefined
−
W
Undefined
−
W
Undefined
−
W
Undefined
−
R
Undefined
−
R
Undefined
−
R
Undefined
−
R
Undefined
188H
16-bit timer
TB0RG0L
(Prohibit
register 0L RMW)
TB0RG1L
0
TB0CLK1
the UC value the UC value the UC value the UC value
is loaded
TB0RG0H
TB0CLE
R/W
0
1: UC0
clear
enable
01: ↑, ↑
10: ↑, ↓
11: ↑, ↓ (TA1OUT)
Invert when
the UC value the UC value
is captured to matches the
value in
TB0CP1.
TB0RG1.
& MODE
16-bit
7
6
TB0RDE
−
R/W
R/W
0
0
Always
Double
write “0”.
buffer
0: Disable
1: Enable
TB0CT1
TB0ET1
R/W
0
0
TB0FF1 INV TRG
0: TRG disable
1: TRG enable
18FH
register 1H
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(8) UART/serial channel
(8-1) UART/SIO Channel 0
Symbol
Name
Serial
SC0BUF
channel 0
buffer
Address
7
6
5
4
3
2
1
0
200H
RB7/TB7
RB6/TB6
RB5/TB5
RB4/TB4
RB3/TB3
RB2/TB2
RB1/TB1
RB0/TB0
SCLKS
IOC
(Prohibit
R (Receiving)/W (Transmission)
RMW)
Undefined
RB8
R
Serial
SC0CR
channel 0
EVEN
201H
control
PE
R/W
Undefined
0
Receiving Parity
0: Odd
data bit8 1: Even
TB8
OERR
PERR
0
0
0
R/W
0
0
1: Error
1: Parity
CTSE
FERR
R (Cleared to 0 by reading.)
enable
Overrun
RXE
WU
0
0:SCLK0↑ 1: Input
1:SCLK0↓ SCLK0 pin
Parity
Framing
SM1
SM0
SC1
SC0
0
0
0
0
R/W
Serial
SC0MOD0 channel 0
0
202H
mode 0
0
0
Transmission 1: CTS
data bit8
−
0
1: Receive 1: Wakeup
enable
enable
BR0ADD
enable
BR0CK1
00: I/O interface
00: TA0TRG
01: UART 7 bits
01: Baud rate generator
10: UART 8 bits
10: Internal clock fSYS
11: UART 9 bits
11: External clock SCLK0
BR0CK0
BR0S3
BR0S2
BR0S1
BR0S0
0
0
0
R/W
BR0CR
Baud rate
control
0
203H
Always
write “0”.
0
0
0
1: (16 − K)/16 00: φT0
divided
01: φT2
enable
10: φT8
Set the frequency divisor N.
0 to F
11: φT32
BR0K3
Serial
BR0ADD
channel 0
K setting
BR0K2
BR0K1
BR0K0
0
0
R/W
204H
0
0
Baud rate 0 K.
register
1 to F
Serial
SC0MOD1 channel 0
mode 1
205H
I2S0
FDPX0
STSEN0
R/W
R/W
W
0
0
1
IDLE2
I/O interface
STS0
0: Stop
0: Half
1: Output
1: Operate
duplex
0: Stop
1: Full
duplex
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(8-2) UART/SIO channel 1
Symbol
Name
Serial
SC1BUF
channel 1
buffer
Address
7
6
5
208H
RB7/TB7
RB6/TB6
RB5/TB5
(Prohibit
2
1
0
RB4/TB4
RB3/TB3
RB2/TB2
RB1/TB1
RB0/TB0
SCLKS
IOC
RMW)
Undefined
EVEN
R
Serial
channel 1
3
R (Receiving)/W (Transmission)
RB8
SC1CR
4
209H
control
PE
R/W
Undefined
0
Receiving Parity
0: Odd
data bit8 1: Even
TB8
OERR
PERR
R (cleared to 0 by reading.)
0
0
0
R/W
0
0
1: Error
1: Parity
CTSE
FERR
enable
Overrun
RXE
WU
0
0:SCLK1↑ 1: Input
Parity
Framing
SM1
SM0
0
0
1:SCLK1↓ SCLK1 pin
SC1
SC0
0
0
R/W
Serial
SC1MOD0 channel 1
0
20AH
mode 0
0
0
Transmission 1: CTS
data bit8
enable
−
BR1ADD
0
0
0
1: Receive 1: Wakeup 00: I/O interface
enable
enable
BR1CK1
00: TA0TRG
01: UART 7 bits
01: Baud rate generator
10: UART 8 bits
10: Internal clock fSYS
11: UART 9 bits
11: External clock SCLK1
BR1CK0
BR1S3
BR1S2
BR1S1
BR1S0
0
0
0
R/W
BR1CR
Baud rate
control
20BH
Always
write “0”.
0
0
1: (16 − K)/16 00: φT0
divided
01: φT2
enable
10: φT8
Set the frequency divisor N.
0 to F
11: φT32
Serial
BR1ADD
channel 1
K setting
BR1K3
BR1K2
0
0
BR1K1
BR1K0
0
0
R/W
20CH
Baud rate 0 K.
register
1 to F
mode 1
FDPX1
STSEN1
R/W
R/W
W
0
Serial
SC1MOD1 channel 1
I2S1
20DH
0
1
IDLE2
I/O interface
STS1
0: Stop
1: Full
1: Output
1: Operate
duplex
0: Stop
0: Half
duplex
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(9) AD converter
Symbol
Name
Address
7
6
EOCF
AD
ADMOD0 MODE
ADBF
R
2B0H
0
0
1: End
register 0
1: Busy
5
4
3
2
1
0
−
−
ITM0
REPEAT
SCAN
ADS
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
Always
Always
Interrupt in 1: Repeat
write “0”.
write “0”.
repeat
0
1: Scan
1: Start
mode.
VREFON
I2AD
ADTRGE
R/W
R/W
R/W
0
0
0
1: VREF on IDLE2
AD
ADMOD1 MODE
register 1
2B1H
ADCH2
ADCH1
ADCH0
R/W
0
1: Enable
0
0
Input channel
0: Abort
for
000: AN0 AN0
1: Operate
external
001: AN1 AN0 → AN1
start
010: AN2 AN0 → AN1 → AN2
011: AN3 AN0 → AN1 → AN2 → AN3
100: AN4 AN4
101: AN5 AN4 → AN5
110: AN6 AN4 → AN5 → AN6
111: AN7 AN4 → AN5 → AN6 → AN7
ADM27
AD
ADMOD2 MODE
2B2H
register 2
ADM26
ADM25
ADM24
ADM23
ADM22
ADM21
ADM20
0
0
0
1
ADM33
ADM32
ADM31
ADM30
1
1
1
1
R/W
0
0
0
1
Please write “1E”.
ADM37
AD
ADMOD3 MODE
2B3H
register 3
ADM36
ADM35
ADM34
R/W
1
1
0
0
Please write “CF”.
AD result
ADREG04L register
ADR01
2A0H
0/4 low
ADR0RF
R
R
Undefined
AD result
ADREG04H register
ADR00
ADR09
ADR08
0
ADR07
ADR06
2A1H
ADR11
2A2H
1/5 low
AD result
ADREG15H register
ADR10
ADR1RF
R
Undefined
0
ADR19
ADR18
ADR17
ADR16
2A4H
ADR13
ADR20
ADR12
ADR2RF
R
R
Undefined
AD result
ADR29
ADR28
0
ADR27
ADR26
2A5H
ADR25
ADR24
ADR23
ADR22
R
2/6 high
Undefined
AD result
ADR31
2A6H
3/7 low
AD result
ADREG37H register
ADR14
Undefined
ADR21
2/6 low
ADREG37L register
ADR15
R
1/5 high
ADREG26H register
ADR02
R
2A3H
AD result
ADREG26L register
ADR03
Undefined
AD result
register
ADR04
R
0/4 high
ADREG15L
ADR05
ADR30
ADR3RF
R
R
Undefined
0
ADR39
ADR38
ADR37
ADR36
2A7H
ADR35
ADR34
ADR33
ADR32
R
3/7 high
Undefined
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(10) Watchdog timer
Symbol
Name
Address
6
5
WDTE
WDTP1
R/W
R/W
0
0
1
WDT
WDMOD MODE
7
300H
1: WDT
enable
register
4
3
2
1
WDTP0
I2WDT
RESCR
−
R/W
R/W
R/W
R/W
0
0
0
0
15
IDLE2
RESET
Always
17
0: Abort
connect
write “0”.
19
1: Operate internally
00: 2 /fSYS
01: 2 /fSYS
10: 2 /fSYS
WDT out to
21
11: 2 /fSYS
reset pin
WDCR
WDT
control
−
301H
W
(Prohibit
−
RMW)
B1H: WDT disable
4EH: WDT clear
(11) Multi vector controllor
Symbol
Name
Address
Multi
MVEC0
vector
00AEH
control
7
6
5
4
3
2
1
0
VEC7
VEC6
VEC5
VEC4
VEC3
VEC2
VEC1
VEC0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
1
1
1
1
1
1
1
1
Vector address A15 to A8
Symbol
Name
Address
Multi
MVEC1
vector
control
00AFH
7
6
5
4
3
2
1
0
VEC15
VEC14
VEC13
VEC12
VEC11
VEC10
VEC9
VEC8
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
1
1
1
1
1
1
1
1
Vector address A23 to A16
Note: Write MVEC1, MVEC0 after making an interruption prohibition state.
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6.
Port Section Equivalent Circuit Diagrams
•
Reading the circuit diagrams
The gate symbols used are essentially the same as those used for the standard CMOS logic
IC [74HCXX] series.
The dedicated signal is described below.
STOP: This signal becomes active (1) when the HALT mode setting register is set to STOP
mode (e.g., when SYSCR2<HALTM1:0> = 0, 1) and the CPU executes the HALT
instruction. When the drive enable bit SYSCR2<DRVE> is set to 1, however, STOP
will remains at 0.
•
„
The input protection resistances ranges from several tens of ohms to several hundreds of ohms.
D0 to D7, P10 to P17, P20 to P27, A0 to A15, P71, P74, P90, P93 to P96
VCC
Output data
P-ch
Output enable
STOP
N-ch
I/O
Input data
Input enable
„
RD , WR
, P60 to P63
Vcc
Output data
Output
STOP
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„
P53 to P55, P80 to P87, PZ2, PZ3
Vcc
Output data
Vcc Programmable
pull-up resistor
Output enable
STOP
I/O
Input data
Input enable
„
PA (AN0 to AN7)
Analog input
channel select
Analog input
Input
Input data
Input enable
„
P56 (INT0), P70 (INT1), P72 (INT2), P73 (INT3), P75 (INT4), P90 (INT5)
Vcc
Output data
Output enable
STOP
I/O
Input data
Schmitt trigger
„
P80 (TXD0)
Vcc
Output data
Open-drain
output enable
STOP
I/O
Input data
Input enable
„
NMI
NMI
Input
Schmitt trigger
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„
AM0 to AM1
Input data
„
Input
RESET
Vcc
P-ch
Input
Reset
Schmitt trigger
WDTOUT
Reset enable
„
X1 and X2
Oscillator
x2
High-frequency
Oscillation enable
P-ch
N-ch
x1
Clock
„
VREFH and VREFL
VREFON
P-ch
VREFH
String
resistor
VREFL
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7.
Points to Note and Restrictions
(1) Notation
a.
The notation for built-in/I/O registers is as follows register symbol <Bit symbol>
(e.g., TA01RUN<TA0RUN> denotes bit TA0RUN of register TA01RUN).
b.
Read-modify-write instructions
An instruction in which the CPU reads data from memory and writes the data to the same
memory location in one instruction.
•
Example 1: SET
3, (TA01RUN) … Set bit 3 of TA01RUN.
Example 2: INC
1, (100H) … Increment the data at 100H.
Examples of read-modify-write instructions on the TLCS-900
Exchange instruction
EX
(mem), R
Arithmetic operations
ADD (mem), R/#
SUB (mem), R/#
INC #3, (mem)
Logic operations
AND (mem), R/#
XOR (mem), R/#
ADC (mem), R/#
SBC (mem), R/#
DEC #3, (mem)
OR
(mem), R/#
Bit manipulation operations
STCF #3/A, (mem)
SET #3, (mem)
TSET #3, (mem)
RES #3, (mem)
CHG #3, (mem)
Rotate and shift operations
RLC (mem)
RRC
RL
(mem)
RR
SLA (mem)
SRA
SLL (mem)
SRL
RLD (mem)
RRD
c.
(mem)
(mem)
(mem)
(mem)
(mem)
fc, fFPH, fSYS and one state
The clock frequency input on pins X1 and 2 is called fOSCH. The clock selected by
DFMCR0<ACT1:0> is called fc.
The clock selected by SYSCR1<SYSCK> is called fFPH. The clock frequency give by fFPH
divided by 2 is called fSYS.
One cycle of fSYS is referred to as one state.
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(2) Points to note
a.
AM0 and AM1 pins
Fix these pins to VCC unless changing voltage.
b.
EMU0 and EMU1
Open pins.
c.
Reserved address areas
The TMP91C829 does not have any reserved areas.
d.
HALT mode (IDLE1)
When IDLE1 mode is used (in which oscillator operation only occurs), set
RTCCR<RTCRUN> to 0 stop the timer for the real time clock before the HALT instructions
is executed.
e.
Warm-up counter
The warm-up counter operates when STOP mode is released, even if the system is using
an external oscillator. As a result a time equivalent to the warm-up time elapses between
input of the release request and output of the system clock.
f.
Programmable pull-up resistance
The programmable pull-up resistor can be turned on/off by a program when the ports are
set for use as input ports. When the ports are set for use as output ports, they cannot be
turned ON/OFF by a program.
The data registers (e.g., P3) are used to turn the pull-up/pull-down resistors on/off.
Consequently read-modify-write instructions are prohibited.
g.
Bus releasing function
Please refer to the note about bus release in Section 3.6 “Port Functions”. The pin state is
written when the bus is released.
h.
Watchdog timer
The watchdog timer starts operation immediately after a reset is released. When the
watchdog timer is not to be used, disable it.
i.
Watchdog timer
When the bus is released, neither internal memory nor internal I/O can be accessed.
However, the internal I/O continues to operate. Hence the watchdog timer continues to run.
Therefore be careful about the bus releasing time and set the detection timer of watchdog
timer.
j.
AD converter
The string resistor between the VREFH and VREFL pins can be cut by a program so as to
reduce power consumption. When STOP mode is used, disable the resistor using the
program before the HALT instruction is executed.
k.
CPU (Micro DMA)
Only the “LDC cr, r” and “LDC r, cr” instructions can be used to access the control
registers in the CPU. (e.g., the transfer source address register (DMASn).)
l.
Undefined SFR
The value of an undefined bit in an SFR is undefined when read.
m. POP SR instruction
Please execute the POP SR instruction during DI condition.
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n.
Releasing the HALT mode by requesting an interruption
Usually, interrupts can release all halts status. However, the interrupts ( NMI , INT0 to
INT4) which can release the HALT mode may not be able to do so if they are input during
the period CPU is shifting to the HALT mode (for about 5 clocks of fFPH) with IDLE1 or
STOP mode (IDLE2 is not applicable to this case). (In this case, an interrupt request is kept
on hold internally.)
If another interrupt is generated after it has shifted to HALT mode completely, halt
status can be released without difficulty. The priority of this interrupt is compared with
that of the interrupt kept on hold internally, and the interrupt with higher priority is
handled first followed by the other interrupt.
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8. Package Dimensions
P-LQFP100-1414-0.50F
Unit: mm
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91C829-202
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