TOSHIBA Original CMOS 16-Bit Microcontroller TLCS-900/L Series TMP93PW44A Semiconductor Company Preface Thank you very much for making use of Toshiba microcomputer LSIs. Before use this LSI, refer the section, “Points of Note and Restrictions”. Especially, take care below cautions. **CAUTION** How to release the HALT mode Usually, interrupts can release all halts status. However, the interrupts = ( NMI , INT0), which can release the HALT mode may not be able to do so if they are input during the period CPU is shifting to the HALT mode (for about 3 clocks of fFPH) with IDLE1 or STOP mode (IDLE2/RUN are not applicable to this case). (In this case, an interrupt request is kept on hold internally.) If another interrupt is generated after it has shifted to HALT mode completely, halt status can be released without difficultly. The priority of this interrupt is compare with that of the interrupt kept on hold internally, and the interrupt with higher priority is handled first followed by the other interrupt. TMP93PW44A Low-power CMOS 16-Bit Microcontroller TMP93PW44ADF 1. Outline and Device Characteristics The TMP93PW44A is OTP type MCU which includes 128-Kbyte one-time PROM. Using the adapter socket, you can write and verify the data for the TMP93PW44A. The TMP93PW44ADF has the same pin assignment as TMP93CW44 (Mask ROM type). Writing the program to built-in PROM, the TMP93PW44A operates as the same way as the TMP93CW44. Note: The operation voltage of TMP93PW44A is VCC = 4.5 to 5.5 V though the operation voltage of TMP93CS44/45, TMP93PS44, TMP93CU44 and TMP93CW44 is VCC = 2.7 to 5.5 V. Especially, be careful when TMP93CU44, TMP93CW44 and TMP93PW44A are used. Please refer to the fourth chapter electric characteristic of each product for details. MCU ROM RAM Package Adapter Socket TMP93PW44ADF OTP 128 Kbytes 4 Kbytes P-QFP80-1420-0.80B BM11152 030619EBP1 • The information contained herein is subject to change without notice. • The information contained herein is presented only as a guide for the applications of our products. No responsibility is assumed by TOSHIBA for any infringements of patents or other rights of the third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of TOSHIBA or others. • TOSHIBA is continually working to improve the quality and reliability of its products. Nevertheless, semiconductor devices in general can malfunction or fail due to their inherent electrical sensitivity and vulnerability to physical stress. It is the responsibility of the buyer, when utilizing TOSHIBA products, to comply with the standards of safety in making a safe design for the entire system, and to avoid situations in which a malfunction or failure of such TOSHIBA products could cause loss of human life, bodily injury or damage to property. In developing your designs, please ensure that TOSHIBA products are used within specified operating ranges as set forth in the most recent TOSHIBA products specifications. Also, please keep in mind the precautions and conditions set forth in the “Handling Guide for Semiconductor Devices,” or “TOSHIBA Semiconductor Reliability Handbook” etc.. • The TOSHIBA products listed in this document are intended for usage in general electronics applications (computer, personal equipment, office equipment, measuring equipment, industrial robotics, domestic appliances, etc.). These TOSHIBA products are neither intended nor warranted for usage in equipment that requires extraordinarily high quality and/or reliability or a malfunction or failure of which may cause loss of human life or bodily injury (“Unintended Usage”). Unintended Usage include atomic energy control instruments, airplane or spaceship instruments, transportation instruments, traffic signal instruments, combustion control instruments, medical instruments, all types of safety devices, etc.. Unintended Usage of TOSHIBA products listed in this document shall be made at the customer’s own risk. • The products described in this document are subject to the foreign exchange and foreign trade laws. • TOSHIBA products should not be embedded to the downstream products which are prohibited to be produced and sold, under any law and regulations. • For a discussion of how the reliability of microcontrollers can be predicted, please refer to Section 1.3 of the chapter entitled Quality and Reliability Assurance/Handling Precautions. Purchase of TOSHIBA I2C components conveys a license under the Philips I2C Patent Rights to use these components in an I2C system, provided that the system conforms to the I2C Standard Specification as defined by Philips. 93PW44A-1 2004-02-10 TMP93PW44A AN0 to AN2 (P50 to P52) AN3/ ADTRG (P53) AN4 to AN7 (P54 to P57) AVCC AVSS VREFH VREFL VCC [2] VSS [2] 900/L CPU 10-bit 8-ch AD converter TXD0 (P60) RXD0 (P61) SCLK0/ CTS0 (P62) Serial I/O (Channel 0) TXD1 (P63) RXD1 (P64) SCLK1/ CTS1 (P65) Serial I/O (Channel 1) XWA XBC XDE XHL XIX XIY XIZ XSP W A B C D E H L IX IY IZ SP 32 bits SR Highfrequency OSC X1 X2 CLK Lowfrequency OSC XT1 (P66) XT2 (P67) AM8/ AM16 EA RESET F PC Interrupt controller ALE TEST1/TEST2 INT0 (P35) NMI WAIT (P70) P71 P72 P73 P74 P75 P76 P77 TI0/INT1 (P40) Watchdog timer Port 7 4-Kbyte RAM 8-bit timer (TIMER 0) Port 0 AD0 to AD7 (P00 to P07) Port 1 AD8 to AD15/A8 to A15 (P10 to P17) Port 2 A0 to A7/A16 to A23 (P20 to P27) 8-bit timer (TIMER 1) 8-bit timer (TIMER 2) TO3 (P41) 8-bit timer (TIMER 3) Port 3 128-Kbyte PROM INT4/TI4 (P42) INT5/TI5 (P43) TO4 (P44) INT6/TI6 (P45) INT7/TI7 (P46) TO6 (P47) 16-bit timer (TIMER 4) Wait controller (3 blocks) Serial bus interface controller 16-bit timer (TIMER 5) RD (P30) WR (P31) HWR /SCK (P32) SO/SDA (P33) SI/SCL (P34) Note: The items in parentheses ( ) are the initial setting after reset. Figure 1.1 TMP93PW44A Block Diagram 93PW44A-2 2004-02-10 TMP93PW44A 2. Pin Assignment and Functions The assignment of input/output pins for the TMP93PW44A, their names and outline functions are described below. 2.1 Pin Assignment 41 45 50 55 65 40 70 35 TMP93PW44ADF QFP80 Top view 75 30 80 P07 (AD7) P06 (AD6) P05 (AD5) P04 (AD4) P03 (AD3) P02 (AD2) P01 (AD1) P00 (AD0) ALE VSS VCC TEST2 TEST1 P67 (XT2) P66 (XT1) 24 RESET EA 20 15 5 (TXD0) P60 (RXD0) P61 (SCLK0/CTS0) P62 (TXD1) P63 (RXD1) P64 (SCLK1/CTS1) P65 (WAIT) P70 P71 VSS P72 P73 P74 P75 P76 P77 CLK AM8/AM16 X1 X2 NMI 1 10 25 (AN5) P55 (AN6) P56 (AN7) P57 (TO3) P41 (TI4/INT4) P42 (TI5/INT5) P43 (TO4) P44 (TI6/INT6) P45 (TI7/INT7) P46 (TO6) P47 VREFH VREFL AVSS AVCC (AN0) P50 (AN1) P51 (AN2) P52 (AN3/ ADTRG ) P53 (AN4) P54 60 64 P40 (TI0/INT1) P35 (INT0) P34 (SI/SCL) P33 (SO/SDA) P32 (HWR/SCK) P31(WR) P30 (RD) VCC P27 (A23/A7) P26 (A22/A6) P25 (A21/A5) P24 (A20/A4) P23 (A19/A3) P22 (A18/A2) P21 (A17/A1) P20 (A16/A0) P17 (AD15/A15) P16 (AD14/A14) P15 (AD13/A13) P14 (AD12/A12) P13 (AD11/A11) P12 (AD10/A10) P11 (AD9/A9) P10 (AD8/A8) Figure 2.1.1 shows pin assignment of the TMP93PW44ADF. Figure 2.1.1 Pin Assignment (P-QFP80-1420-0.80B) 93PW44A-3 2004-02-10 TMP93PW44A 2.2 Pin Names and Functions The TMP93PW44A has MCU mode and PROM mode. (1) Table 2.2.1 shows pin function of TMP93PW44A in MCU mode. Table 2.2.1 Pin Names and Functions (1/3) Pin Name Number of Pins P00 to P07 AD0 to AD7 8 P10 to P17 AD8 to AD15 A8 to A15 8 P20 to P27 8 I/O Port 1: I/O port that allows selection of I/O on a bit basis Output Address: Bits 8 to 15 for address bus I/O Port 2: I/O port that allows selection of I/O on a bit basis (with pull-up resistor) Output Address: Bits 0 to 7 for address bus Output Address: Bits 16 to 23 for address bus 1 Output Port 30: Output port Output Read: Strobe signal for reading external memory 1 Output Port 31: Output port Output Write: Strobe signal for writing data on pins AD0 to AD7 WR P32 I/O Port 0: I/O port that allows selection of I/O on a bit basis 3-state Address/data (Upper): Bits 8 to 15 for address/data bus RD P31 Functions 3-state Address/data (Lower): Bits 0 to 7 for address/data bus A0 to A7 A16 to A23 P30 I/O 1 I/O Port 32: I/O port (with pull-up resistor) Output High write: Strobe signal for writing data on pins AD8 to AD15 HWR SCK I/O Mode clock SBI SIO mode clock P33 SO SDA 1 P34 SI SCL 1 P35 INT0 1 P40 TI0 INT1 1 P41 TO3 1 P42 TI4 INT4 1 I/O Port 33: I/O port Output Serial send data I/O SBI I2C bus mode channel data I/O Port 34: I/O port Input Serial receive data I/O SBI I2C bus mode clock I/O Port 35: I/O port Input Interrupt request pin 0: Interrupt request pin with programmable level/rising edge I/O Port 40: I/O port Input Timer input 0: Timer 0 input Input Interrupt request pin 1: Interrupt request pin with rising edge I/O Port 41: I/O port Output PWM output 3: 8-bit PWM timer 3 output I/O Port 42: I/O port Input Timer input 4: Timer 4 count/capture trigger signal input Input Interrupt request pin 4: Interrupt request pin with programmable rising/falling edge 93PW44A-4 2004-02-10 TMP93PW44A Table 2.2.2 Pin Names and Functions (2/3) Pin Name Number of Pins P43 TI5 INT5 1 P44 TO4 1 P45 TI6 INT6 1 P46 TI7 INT7 1 P47 TO6 1 P50 to P52, P54 to P57 AN0 to AN2, AN4 to AN7 7 P53 AN3 1 I/O Functions I/O Port 43: I/O port Input Timer input 5: Timer 4 count/capture trigger signal input Input Interrupt request pin 5: Interrupt request pin with rising edge I/O Port 44: I/O port Output Timer output 4: Timer 4 output pin I/O Port 45: I/O port Input Timer input 6: Timer 5 count/capture trigger signal input Input Interrupt request pin 6: Interrupt request pin with programmable rising/falling edge I/O Port 46: I/O port Input Timer input 7: Timer 5 count/capture trigger signal input Input Interrupt request pin 7: Interrupt request pin with rising edge I/O Port 47: I/O port Output Timer output 6: Timer 5 output pin Input Port 50 to 52, port 54 to 57: Input port Input Analog input: Analog signal input for AD converter Input Port 53: Input port Input Analog input: Analog signal input for AD converter ADTRG Input AD converter external start trigger input P60 TXD0 1 P61 RXD0 1 P62 1 I/O Port 60: I/O port (with pull-up resistor) Output Serial send data 0 I/O Port 61: I/O port (with pull-up resistor) Input Serial receive data 0 CTS0 I/O Port 62: I/O port (with pull-up resistor) Input Serial data send enable 0 (Clear to send) SCLK0 I/O Serial clock I/O 0 P63 TXD1 1 P64 RXD1 1 P65 SCLK1 1 I/O Port 63: I/O port (with pull-up resistor) Output Serial send data 1 I/O Port 64: I/O port (with pull-up resistor) Input Serial receive data 1 I/O Port 65: I/O port (with pull-up resistor) I/O Serial clock I/O 1 CTS1 Input Serial data send enable 1 (Clear to send) P66 XT1 1 P67 XT2 1 I/O Port 66: I/O port (Open-drain output) Input Low-frequency oscillator connecting pin I/O Port 67: I/O port (Open-drain output) Output Low-frequency oscillator connecting pin 93PW44A-5 2004-02-10 TMP93PW44A Table 2.2.3 Pin Names and Functions (3/3) Pin Name P70 Number of Pins 1 I/O Functions I/O Port 70: I/O port (High current output available) Input WAIT: Pin used to request CPU bus wait. (It is active in (1 + N) WAIT mode. Set by the bus-width/wait control register.) WAIT P71 to P77 7 AVCC 1 I/O Port 71 to 77: I/O port (High current output available) Input Power supply pin for AD converter AVSS 1 Input GND pin for AD converter (0 V) VREFH 1 Input Pin for high level reference voltage input to AD converter VREFL 1 Input Pin for low level reference voltage input to AD converter NMI 1 Input Non-maskable interrupt request pin: Interrupt request pin with falling edge. Can also be operated at falling and rising edges by program. X1 1 Input High-frequency oscillator connecting pin X2 1 Output High-frequency oscillator connecting pin RESET 1 ALE 1 Output Address latch enable Can be disabled for reducing noise. Input Reset: Initializes TMP93PW44A (with pull-up resistor). CLK 1 Output Clock output: Outputs “fSYS ÷ 2” clock. Pulled-up during reset. Can be disabled for reducing noise. EA 1 Input External access: “1” should be inputted AM8/ AM16 1 Input Address mode: Selects external data bus width. “1” should be inputted. The data bus width for external access is set by chip select/WAIT control register, port 1 control register. VCC 2 Input Power supply pin VSS 2 TEST1/TEST2 2 Input GND pin (All VSS pins are connected to the GND (0 V)). Output/Input TEST1 should be connected with TEST2 pin. Do not connect to any other pins. Note: Built-in pull-up resistors can be released from the pins other than the RESET pin by software. 93PW44A-6 2004-02-10 TMP93PW44A (2) PROM mode Table 2.2.4 shows pin functions of the TMP93PW44A in PROM mode. Table 2.2.4 Pin Names and Functions of PROM Mode Pin Function Number of Input/Output Pins Function Pin Name (MCU Mode) A7 to A0 8 Input A15 to A8 8 Input P27 to P20 A16 1 Input D7 to D0 8 I/O Memory data of pfogram P07 to P00 CE 1 Input Chip enable P32 OE 1 Input Output control P30 PGM 1 Input Program control P31 Memory address of program P17 to P10 P33 VPP 1 Power supply 12.75 V/5 V (Power supply of program) EA VCC 3 Power supply 6.25 V/5 V VCC, AVCC VSS 3 Power supply 0 V VSS, AVSS Pin Function Number of Input/Output Pins P60 1 Input RESET 1 Input CLK 1 Input ALE 1 Output X1 1 Input X2 1 Output P66 to P61 AM8/ AM16 7 Input TEST1/TEST2 2 Input/Output 30 I/O P35, P34 P47 to P40 P57 to P50 P67 P77 to P70 VREFH VREFL Disposal of Pin Fix to low level (Security pin) Fix to low level (PROM mode) Open Self oscillation with resonator Fix to high level TEST1 should be connected with TEST2 pin. Do not connect to any other pins. Open NMI 93PW44A-7 2004-02-10 TMP93PW44A 3. Operation This section describes the functions and basic operational blocks of the TMP93PW44A. The TMP93PW44A has PROM in place of the mask ROM which is included in the TMP93CW44. The other configuration and functions are the same as the TMP93CW44. Regarding the function of the TMP93PW44A (Not described), see the part of TMP93CW44. The TMP93PW44A has two operational modes: MCU mode and PROM mode. 3.1 MCU mode (1) Mode setting and function The MCU mode is set by opening the CLK pin (Pin open). In the MCU mode, the operation is same as TMP93CW44. (2) Memory map The memory map of TMP93PW44A is same as that of TMP93CW44. Figure 3.1.1 shows the memory map in MCU mode. Figure 3.1.2 show that in PROM mode. 000000H 00000H Internal I/O (128 bytes) 000080H Internal RAM (4 Kbytes) 001080H Internal PROM (128 Kbytes) External memory FE0000H 1FFFFH Internal PROM (128 Kbytes) FFFF00H FFFFFFH ( = Internal area) Interrupt vector table area (256 bytes) Figure 3.1.1 Memory Map in MCU Mode 93PW44A-8 Figure 3.1.2 Memory Map in PROM Mode 2004-02-10 TMP93PW44A 3.2 PROM Mode (1) Mode setting and function PROM mode is set by setting the RESET and CLK pins to the “L” level. The programming and verification for the internal PROM is achieved by using a general EPROM programmer with the adaptor socket. 1. Preparation of OTP adaptor BM11152: for TMP93PW44ADF 2. Setting of OTP adaptor The switch (SW1) is set to N side. 3. Setting of PROM writer i) Set PROM type to TC 571000D. Size: 1 Mbits (128 K × 8 bits) VPP: 12.75 V tPW: 100 µs Electric signature mode: None ii) Data transmittion In TMP93PW44A, PROM is placed on addresses 00000H to 1FFFFH in PROM mode, and addresses FE0000H to FFFFFFH in MCU mode. Therefore data should be transferred to addresses 00000H to 1FFFFH in PROM mode using the object converter (tuconv) or the block transfer mode (See instruction manual of PROM programmer.) iii) Setting of the program address Start address: 00000H End address: 1FFFFH 4. Programming Program and verify according to operating process of PROM programmer. 93PW44A-9 2004-02-10 TMP93PW44A Figure 3.2.1 shows the setting of the pins in PROM mode. VPP (12.75 V/5 V) VCC EA A16 to A0 AVCC, VCC TEST1 TEST2 P30 P32 P31 P33 P17 to P10 P27 to P20 P07 to P00 OE CE PGM D7 to D0 section on pin functions (Table 2.2.2). RESET * Use the 10 MHz resonator in case of programming and CLK VCC X1 * For other pins, refer to the verification by a general PROM programmer. P65 to P61 AM8/ AM16 X2 VSS AVSS P60 SECURITY Figure 3.2.1 PROM Mode Pin Setting (2) Caution for electric signature The TMP93PW44A dose not support the electric signature mode (Hereinafter referred to as “signature”). If PROM programmer used the signature, the device would be damaged because of applying voltage of 12 ± 0.5 V to pin 9 (A9) of the address. Please use without setting the signature. (3) Program mode All bits of the TMP93PW44A are “1” when delivered (The erase state). Data “0” is written in the necessary bit location during program operating. Writing function can be operated at VPP = 12.5 V, OE = VIH, CE = VIL. Built-in one time PROM can be written in any sequence. It is possible to write only special address. (4) Adopter socket (BM11152: for TMP93PW44ADF) BM11152 is the adapter sockets to write data into the TMP93PW44A. The TMP93PW44A has built-in one time PROM using a general EPROM programmer. 93PW44A-10 2004-02-10 TMP93PW44A (5) Program storing area of PROM mode The TMP93PW44A has the program space (FE0000H to FFFFFFH) of 128 Kbytes. The address 0000H to 1FFFFH of PROM mode equals to the address FE0000H to FFFFFFH of MCU mode. (6) Program write setting method using a general PROM programmer PROM to be prepared should equal to TC571000D functions. 1. Set the switch (SW1) of BM11152 (Hereinafter referred to as “adapter”) to the program side (NOR) (Note 1). 2. Connect MCU to the adapter (Note 2). 3. Connect the adapter to PROM programmer (Note 2). 4. Set the PROM type of PROM programmer to TC571000D. 5. Set the start address for writing PROM to 0000H, and the end address to 1FFFFH (Note 3). 6. Writing to built-in one time PROM and verifying should be operated according to the operation procedures of PROM programmer. Note 1: If data is written to built-in one time PROM without setting the switch (SW1) to the program side, the device would be damaged. Note 2: Please set with the first pin of the adapter and that of PROM programmer socket matched. If the first pin is conversely set, MCU or programmer would be damaged. Note 3: If data “0” is written to the address which is over 1FFFFH, the contents of the original program would be damaged because of writing “0” to the addresses 0000H to 1FFFFH. 93PW44A-11 2004-02-10 TMP93PW44A (7) Programming flow chart The programming mode is set by applying 12.75 V (Programming voltage) to the VPP pin when the following pins are set as follows, (VCC: 6.25 V, RESET : “L” level, CLK: “L” level). While address and data are fixed and CE pin is set to “L” level, 0.1 ms of “L” level pulse is applied to PGM pin to program the data. Then the data in the address is verified. If the programmed data is incorrect, another 0.1 ms pulse is applied to PGM pin. This programming procedure is repeated until correct data is read from the address (25 times maximum). Subsequently, all data are programmed in all addresses. The verification for all data is done under the condition of VPP = VCC = 5 V after all data were written. Figure 3.2.2 shows the programming flowchart. Start VCC = 6.25 V ± 0.25 V VPP = 12.75 V ± 0.25 V Address = Start address X=0 Program 0.1 ms pulse X=X+1 X > 25? Yes No Error Address = Address + 1 Verify OK No Last address? Yes VCC = 5 V VPP = 5 V Read all data Error OK Pass Failure Figure 3.2.2 Flowchart (High-speed program writing) 93PW44A-12 2004-02-10 TMP93PW44A (8) Security bit The TMP93PW44A has a security bit in PROM cell. If the security bit is programmed to “0”, the content of the PROM is disable to be read (FFH data) in PROM mode. (How to program the security bit) The difference from the programming procedures described in section 3.2 (1) are as follows. 1. Setting OTP adaptor Set the switch (SW1) to S side. 2. Setting PROM programmer i) Transferring the data ii) Setting of programming address The security bit is in bit0 of address 00000H. Set the start address 00000H and the end address 00000H. Set the data FEH at the address 00000H. 93PW44A-13 2004-02-10 TMP93PW44A 4. Electrical Characteristics 4.1 Maximum Ratings (TMP93PW44AD) Parameter Symbol Power supply voltage Rating Unit −0.5 to 6.5 VCC except EA pin −0.5 to VCC + 0.5 Input voltage VIN Output current (Per 1 pin) P7 IOL1 Output current (Per 1 pin) except P7 IOL2 2 Output current (P7 total) ΣIOL1 80 Output current (Total) ΣIOL 120 Output current (Total) ΣIOH −80 Power dissipation (Ta = 85°C) PD 350 Soldering temperature (10 s) TSOLDER 260 Storage temperature TSTG −65 to 150 Operating temperature TOPR −40 to 85 Note: 4.2 “X” used in an expression shows a cycle of clock fFPH selected by SYSCR1<SYSCK>. If a clock gear or a low speed oscillator is selected, a value of “X” is different. The value as an example is calculated at fc, gear=1/fc (SYSCR1<SYSCK, GEAR2:0> = “0000”). V −0.5 to 14.0 EA pin 20 mA mW °C The maximum ratings are rated values which must not be exceeded during operation, even for an instant. Any one of the ratings must not be exceeded. If any maximum rating is exceeded, a device may break down or its performance may be degraded, causing it to catch fire or explode resulting in injury to the user. Thus, when designing products which include this device, ensure that no maximum rating value will ever be exceeded. DC Characteristics (1/2) VCC = 5 V ± 10%, Ta = −40 to 85°C Parameter Power supply voltage AVCC = VCC AVSS = VSS = 0 V AD0 to AD15 Input low voltage Symbol VCC Condition fc = 4 to 20 MHz fs = 30 to 34 kHz Min Typ. (Note 1) 4.5 (Note 2) VIL Port 2 to 7 (except P35) VIL1 VIL2 RESET , NMI , INT0 Max Unit 5.5 V 0.8 0.3 VCC VCC = 5 V ± 10% −0.3 0.25 VCC EA , AM8/ AM16 VIL3 0.3 X1 VIL4 0.2 VCC AD0 to AD15 VIH Port 2 to 7 (except P35) VIH1 Input high VIH2 RESET , NMI , INT0 voltage EA , AM8/ AM16 VIH3 X1 2.2 V 0.7VCC VCC = 5 V ± 10% 0.75VCC VCC + 0.3 VCC − 0.3 VIH4 0.8 VCC Output low voltage VOL IOL = 1.6 mA Output low current (P7) IOL7 VOL = 1.0 V 16 mA Output high voltage VOH IOH = −400 µA 4.2 V 0.45 V Note 1: Typical values are for Ta = 25°C and VCC = 5 V unless otherwise noted. Note 2:The minimum operation voltage of TMP93CU44/TMP93CW44 is VCC = 2.7 V (at fc = 4 to 12.5 MHz, fs = 30 to 34 kHz). 93PW44A-14 2004-02-10 TMP93PW44A DC Characteristics (2/2) Parameter Symbol Condition Min Typ. (Note 1) Max Unit −3.5 mA Darlington drive current (8 output pins max) IDAR (Note 2) VEXT = 1.5 V REXT = 1.1 kΩ Input leakage current ILI 0.0 ≤ VIN ≤ VCC 0.02 ±5 Output leakage current ILO 0.2 ≤ VIN ≤ VCC − 0.2 0.05 ±10 Power down voltage (at STOP, RAM backup) VSTOP VIL2 = 0.2VCC, VIH2 = 0.8VCC 2.0 6.0 RESET pull-up resistance RRST VCC = 5.5 V 45 130 VCC = 4.5 V 50 160 Pin capacitance CIO Schmitt width RESET , NMI , INT0 VTH Programmable pull-up resistance RKH −1.0 fc = 1 MHz 10 0.4 1.0 VCC = 5.5 V 45 130 VCC = 4.5 V 50 160 27 33 RUN 22 27 16 19 fc = 20 MHz IDLE1 4.2 7 SLOW (Note 3) 85 140 50 100 35 75 20 65 RUN IDLE2 ICC fs = 32.768 kHz IDLE1 Ta ≤ 50°C STOP V kΩ pF V NORMAL (Note 3) IDLE2 µA kΩ mA µA 10 Ta ≤ 70°C 0.2 Ta ≤ 85°C 20 µA 50 Note 1: Typical values are for Ta = 25°C and VCC = 5 V unless otherwise noted. Note 2: IDAR is guranteed for total of up to 8 ports. Note 3: ICC measurement conditions (NORMAL, SLOW): Only CPU is operational; output pins are open and input pins are fixed. (Reference) Definition of IDAR REXT IDAR VEXT 93PW44A-15 2004-02-10 TMP93PW44A 4.3 AC Electrical Characteristics (1) VCC = 5 V ± 10% No. Parameter Symbol Variable Min Max 31250 16 MHz Min Max 20 MHz Unit Min Max 1 Osc. period (= X) tOSC 50 62.5 50 2 CLK pulse width tCLK 2X − 40 85 60 ns ns 3 A0 to A23 valid → CLK hold tAK 0.5X − 20 11 5 ns 4 CLK valid → A0 to A23 hold tKA 1.5X − 70 24 5 ns 5 A0 to A15 valid → ALE fall tAL 0.5X − 15 16 10 ns 6 ALE fall → A0 to A15 hold tLA 0.5X − 20 11 5 ns 7 ALE high pulse width tLL X − 40 23 10 ns 8 ALE fall → RD / WR fall tLC 0.5X − 25 6 0 ns 9 RD / WR rise → ALE rise tCL 0.5X − 20 11 5 ns 10 A0 to A15 valid → RD / WR fall tACL X − 25 38 25 ns 11 A0 to A23 valid → RD / WR fall tACH 1.5X − 50 44 25 ns 12 RD / WR rise → A0 to A23 hold tCA 0.5X − 25 13 A0 to A15 valid → D0 to D15 input tADL 3.0X − 55 133 95 ns 14 A0 to A23 valid → D0 to D15 input tADH 3.5X − 65 154 110 ns 15 RD fall → D0 to D15 input tRD 2.0X − 60 65 40 ns 16 RD low pulse width tRR 2.0X − 40 85 60 17 RD rise → D0 to D15 hold tHR 0 0 0 ns 18 RD rise → A0 to A15 output tRAE X − 15 48 35 ns 19 tWW 2.0X − 40 85 60 ns tDW 2.0X − 55 70 45 ns tWD 0.5X − 15 WR low pulse width 20 D0 to D15 valid → WR rise 21 WR rise → D0 to D15 hold 6 0 16 ns ns 10 ns 22 A0 to A23 valid → WAIT input (1 + N) WAIT mode tAWH 3.5X − 90 129 85 ns 23 A0 to A15 valid → WAIT input (1 + N) WAIT mode tAWL 3.0X − 80 108 70 ns 24 RD / WR fall → WAIT hold (1 + N) WAIT mode tCW 5 ns 25 A0 to A23 valid → PORT input 26 A0 to A23 valid → PORT hold 27 2.0X + 0 tAPH2 WR rise → PORT valid 125 2.5X − 120 tAPH 2.5X + 50 tCP 100 36 206 200 ns 175 200 ns 200 ns AC Measuring Conditions • Output level: High 2.2 V/Low 0.8 V, CL = 50 pF (However CL = 100 pF for AD0 to AD15, A0 to A23, ALE, RD , WR , HWR , CLK) • Input level: High 2.4 V/Low 0.45 V (AD0 to AD15) High 0.8 × VCC/Low 0.2 × VCC (except for AD0 to AD15) 93PW44A-16 2004-02-10 TMP93PW44A (2) Read cycle tOSC X1/XT1 tCLK CLK tAK tKA A0 to A23 tAWH tAWL tCW WAIT tAPH tAPH2 Port input (Note) tADH tCA tRR RD tACH tACL AD0 to AD15 tRD tLC A0 to A15 tAL tADL tHR tRAE D0 to D15 tLA tCL ALE tLL Note: Since the CPU accesses the internal area to read data from a port, the control signals of external pins such as RD and CS are not enabled. Therefore, the above waveform diagram should be regarded as depicting internal operation. Please also note that the timing and AC characteristics of port input/output shown above are typical representation. For details, contact your local Toshiba sales representative. 93PW44A-17 2004-02-10 TMP93PW44A (3) Write cycle X1/XT1 CLK A0 to A23 WAIT Port output (Note) tWW WR , HWR tDW AD0 to AD15 A0 to A15 tCP tWD D0 to D15 ALE Note: Since the CPU accesses the internal area to write data to a port, the control signals of external pins such as WR and CS are not enabled. Therefore, the above waveform diagram should be regarded as depicting internal operation. Please also note that the timing and AC characteristics of port input/output shown above are typical representation. For details, contact your local Toshiba sales representative. 93PW44A-18 2004-02-10 TMP93PW44A 4.4 Serial Channel Timing (1) I/O interface mode 1. SCLK input mode Parameter Variable Symbol 32.768 MHz Min Max Min (Note) 20 MHz Max Min Max Unit tSCY 16X 488 µs 0.8 µs ns tOSS tSCY/2 − 5X − 50 91.5 µs 100 ns SCLK rising/falling edge → Output data hold tOHS 5X − 100 152 µs 150 ns SCLK rising/falling edge → Input data hold tHSR 0 0 0 ns SCLK rising/falling edge → Effective data input tSRD SCLK cycle Output data → Falling edge of SCLK tSCY − 5X − 100 336 µs 450 ns Note 1: When fs is used as system clock or fs divided by 4 is used as input clock to prescaler. Note 2: SCLK rising/falling timing; SCLK rising in the rising mode of SCLK, SCLK falling in the falling mode of SCLK. 2. SCLK output mode Parameter SCLK cycle (Programmable) Output data → SCLK rising edge tSCY 32.768 MHz Min Max Min 16X 8192X 488 µs tOSS tSCY − 2X − 150 2X − 80 SCLK rising edge → Output data hold tOHS SCLK rising edge → Input data hold tHSR SCLK rising edge → Effective data input tSRD Note: Variable Symbol 0 (Note) 20 MHz Max Min Max 250 ms 0.8 µs Unit 409.6 ns µs 427 µs 550 ns 60 µs 20 ns 0 0 ns tSCY − 2X − 150 428 µs 550 ns When fs is used as system clock or fs divided by 4 is used as input clock to prescaler. tSCY SCLK Output mode/ Input rising edge mode SCLK (Input falling edge mode) tOHS tOSS Output data TXD 0 1 2 tSRD Input data RXD 0 Valid 3 tHSR 1 Valid 2 Valid 3 Valid (2) UART mode (SCLK0 and SCLK 1 are external input) Parameter Symbol Variable Min 32.768 MHz Max Min (Note) Max 20 MHz Min Max Unit SCLK cycle tSCY 4X + 20 122 µs 220 ns SCLK low level pulse width tSCYL 2X + 5 6 µs 105 ns SCLK high level pulse width tSCYH 2X + 5 6 µs 105 ns Note: When fs is used as system clock or fs divided by 4 is used as input clock to prescaler. 93PW44A-19 2004-02-10 TMP93PW44A 4.5 AD Conversion Characteristics AVCC = VCC, AVSS = VSS Parameter Symbol Power Supply Min Typ. Max Analog reference voltage ( + ) VREFH VCC − 0.2 V VCC VCC Analog reference voltage ( − ) VREFL VSS VSS VSS + 0.2 V Analog input voltage range VAIN Analog current for analog reference voltage <VREFON> = 1 IREF (VREFL = 0 V) VREFL VCC = 5 V ± 10% <VREFON> = 0 Error (except quantization errors) − Unit V VREFH 0.5 1.5 mA 0.02 5.0 µA ±1.0 ±3.0 LSB Note 1: 1LSB = (VREFH − VREFL)/2 [V] 10 Note 2: The operation above is guaranteed for fFPH ≥ 4 MHz. Note 3: The value ICC includes the current which flows through the AVCC pin. 4.6 Event Counter Input Clock (External Input Clock: TI0, TI4, TI5, TI6, TI7) Parameter Symbol Variable Min Max 20 MHz Min Max Unit Clock cycle tVCK 8X + 100 500 ns Low level clock pulse width tVCKL 4X + 40 240 ns High level clock pulse width tVCKH 4X + 40 240 ns 4.7 Interrupt and Capture Operation (1) NMI , INT0 interrupts Parameter Symbol Variable Min Max 20 MHz Min Max Unit NMI , INT0 low level pulse width tINTAL 4X 200 ns NMI , INT0 high level pulse width tINTAH 4X 200 ns (2) INT1, INT4 to INT7 interrupts and capture Parameter Symbol Variable Min Max 20 MHz Min Max Unit INT1, INT4 to INT7 low level pulse width tINTBL 4X + 100 300 ns INT1, INT4 to INT7 high level pulse width tINTBH 4X + 100 300 ns 93PW44A-20 2004-02-10 TMP93PW44A 4.8 Serial Bus Interface Timing (1) I2C bus mode Parameter Symbol START command → SDA fall Variable Typ. Min Max Unit tGSTA 3X ns tHD:STA 2nX ns SCL low level pulse width tLOW 2nX ns SCL high level pulse width tHIGH 2nX + 12X ns Hold time START condition Data hold time (input) tHD:IDAT 0 ns Data setup time (input) tSU:IDAT 250 ns Data hold time (output) tHD:ODAT 7X 11X tODAT STOP command → SDA fall tFSDA 3X SDA falling edge → SCL rising edge tFDRC 2nX ns tSU:STO 2nX + 16X ns Setup time STOP condition Note: 2nX − tHD:ODAT ns Data output → SCL rising edge ns ns “n” value is set by SBICR1<SCK2:0> STOP Command START command SDA tHD:ODAT tGSTA tODAT tLOW tFSDA tFDRC SCL tHD:STA tHD:IDAT tHIGH tSU:IDAT 93PW44A-21 tSU:STO 2004-02-10 TMP93PW44A (2) Clocked-synchronous 8-bit SIO mode 1. SCK input mode Parameter Variable Symbol Min Unit Max SCK cycle tSCY2 25X ns SCK falling edge → Output data hold tOHS2 6X ns Output data → SCK rising edge tOSS2 tSCY2 − 6X ns SCK rising edge → Input data hold tHSR2 6X ns Input data → SCK rising edge tISS2 0 ns 2. SCK output mode Parameter Variable Symbol Min Max 211X Unit SCK cycle tSCY2 25X SCK falling edge → Output data hold tOHS2 2X Output data → SCK rising edge tOSS2 tSCY2 − 2X ns SCK rising edge → Input data hold tHSR2 2X ns Input data → SCK rising edge tISS2 0 ns ns tOSS2 tSCY2 SCK (Input/output mode) ns tISS2 tOHS2 SO (Output data) SI (Input data) tHSR2 93PW44A-22 2004-02-10 TMP93PW44A 4.9 Read Operation in PROM Mode DC/AC characteristics Ta = 25 ± 5°C Vcc = 5 V ± 10% Parameter Symbol Condition Min Max VPP read voltage VPP − 4.5 5.5 Input high voltage (A0 to A16, CE , OE , PGM ) VIH1 − 2.2 VCC + 0.3 Input low voltage (A0 to A16, CE , OE , PGM ) VIL1 − −0.3 0.8 Address to output delay tACC CL = 50 pF − 2.25TCYC + α Unit V ns TCYC = 400 ns (10 MHz clock) α = 200 ns A0 to A16 CE OE PGM tACC D0 to D7 Data output 93PW44A-23 2004-02-10 TMP93PW44A 4.10 Program Operation in PROM Mode DC/AC characteristics Ta = 25 ± 5°C VCC = 6.25 V ± 0.25 V Condition Min Typ. Max Programming supply voltage Parameter Symbol VPP − 12.50 12.75 13.00 Input high voltage (D0 to D7, A0 to A16, CE , OE , PGM ) VIH − 2.6 VCC + 0.3 Input low voltage (D0 to D7, A0 to A16, CE , OE , PGM ) VIL − −0.3 0.8 VCC supply current ICC fc = 10 MHz − 50 VPP supply current IPP VPP = 13.00 V − 50 PGM program pulse width tPW CL = 50 pF 0.095 0.1 Unit V mA 0.105 ms A0 to A16 CE OE D0 to D7 Unknown Data-in stable Data-out valid tPW PGM VPP Note 1: The power supply of VPP (12.75 V) must be set power-on at the same time or the later time for a power supply of VCC and must be clear power-on at the same time or early time for a power supply of VCC. Note 2: The pulling up/down device on condition of VPP = 12.75 V suffers a damage for the device. Note 3: The maximum spec of VPP pin is 14.0 V. Be carefull a overshoot at the programming. 93PW44A-24 2004-02-10 TMP93PW44A 5. Package Dimensions P-QFP80-1420-0.80B Unit: mm 93PW44A-25 2004-02-10 TMP93PW44A 93PW44A-26 2004-02-10