SD56120M RF POWER TRANSISTORS The LdmoST FAMILY N-CHANNEL ENHANCEMENT-MODE LATERAL MOSFETs • EXCELLENT THERMAL STABILITY • COMMON SOURCE CONFIGURATION, PUSHPULL • POUT = 120 W WITH 13 dB gain @ 860 MHz /32V • BeO FREE PACKAGE M252 epoxy sealed • INTERNAL INPUT MATCHING ORDER CODE SD56120M DESCRIPTION The SD56120M is a common source N-Channel enhancement-mode lateral Field-Effect RF power transistor designed for broadband commercial and industrial applications at frequencies up to 1.0 GHz. The SD56120M is designed for high gain and broadband performance operating in common source mode at 32 V. Its internal matching makes it ideal for TV broadcast applications requiring high linearity. BRANDING SD56120M PIN CONNECTION 1 2 3 5 4 1. Drain 2. Drain 3. Source 4. Gate 5. Gate ABSOLUTE MAXIMUM RATINGS (TCASE = 25°C) Symbol Parameter Value Unit V(BR)DSS Drain-Source Voltage 65 V VGS Gate-Source Voltage ± 20 V Drain Current 14 A Power Dissipation (@ Tc = 70°C) 236 W ID PDISS Tj TSTG Max. Operating Junction Temperature Storage Temperature 200 °C -65 to +150 °C 0.55 °C/W THERMAL DATA Rth(j-c) Junction -Case Thermal Resistance March, 11 2003 1/8 SD56120M ELECTRICAL SPECIFICATION (TCASE = 25°C) STATIC (Per Section) Symbol Test Conditions Min. Typ. Max. Unit V(BR)DSS VGS = 0 V IDS = 10 mA IDSS VGS = 0 V VDS = 28 V 1 µA IGSS VGS = 20 V VDS = 0 V 1 µA VGS(Q) VDS = 28 V ID = 100 mA 5.0 V VDS(ON) VGS = 10 V ID = 3 A 0.8 V 65 V 2.0 0.7 GFS VDS = 10 V ID = 3 A 3 mho CISS* VGS = 0 V VDS = 28 V f = 1 MHz 221 pF COSS VGS = 0 V VDS = 28 V f = 1 MHz 48.9 pF CRSS VGS = 0 V VDS = 28 V f = 1 MHz 2.25 pF * Includes Internal Input Moscap. DYNAMIC Symbol Test Conditions POUT VDD = 32 V IDQ = 400 mA GPS VDD = 32 V IDQ = 400 mA ηD VDD = 32 V Load mismatch Min. Typ. Max. 120 POUT = 120 W f = 860 MHz 13 IDQ = 400 mA POUT = 120 W f = 860 MHz 50 % VDD = 32 V IDQ = 400 mA ALL PHASE ANGLES POUT = 120 W f = 860 MHz 10:1 VSWR W 16 IMPEDANCE DATA D ZDL Typical Input Impedance Typical Drain Load Impedance G Zin S FREQ. ZIN (Ω) ZDL(Ω) 860 MHz 5.57 + j 3.488 4.21 - j 2.88 Measured drain to drain and gate to gate respectively. 2/8 Unit f = 860 MHz dB SD56120M TYPICAL PERFORMANCE Capacitance vs. Drain Voltage 1000 C, CAPACITANCE (pF) Ciss 100 Coss 10 Crss f =1 MHz 1 0 5 10 15 20 25 Vds, DRAIN-SOURCE VOLTAGE (V) 30 Vgs, GATE-SOURCE VOLTAGE (NORMALIZE Gate-Source Voltage vs. Case Temperature 1.03 1.02 ID = 5 A 1.01 ID = 4 A 1 ID = 3 A 0.99 ID = 2 A 0.98 V DS = 10 V ID = 1 A 0.97 0.96 -20 0 20 40 60 80 Tc, CASE TEMPERATURE (°C) Drain Current vs. Gate Voltage 9 Id, DRAIN CURRENT (A) 8 Vds= 10V 7 6 5 4 3 2 1 0 0 1 2 3 4 5 6 Vgs, GATE-SOURCE VOLTAGE (V) 3/8 SD56120M Power Gain vs. Output Power 100 20 160 90 19 Pout 140 80 120 70 Eff 100 60 80 50 60 40 40 Vdd = 32 V Idq= 2 x 200 mA f = 860 MHz 20 0 0 1 2 3 4 5 Gp, POWER GAIN (dB) 180 Nd , EFFICIENCY (%) Pout, OUTPUT POWER (W) TYPICAL PERFORMANCE Output Power & Efficiency vs. Input Power Idq = 2 x 600mA Idq = 2 x 400mA 18 Idq = 2 x 300mA 17 Idq = 2 x 200mA 16 15 14 30 13 20 12 Vdd = 32V f = 860 MHz 1 6 10 1000 Output Power vs. Drain Voltage -10 210 -15 Pout, OUTPUT POWER (W) IMD3, INTERMODULATION DISTORTION (dBc) Intermodulation Distortion vs. Output Power -20 -25 Idq = 2 x 625 mA -30 Idq = 2 x 200 mA -35 Idq = 2 x 400 mA -40 f1= 860 MHz f2= 859.9 MHz Vdd = 32 V -45 -50 0 30 60 90 120 Pout, OUTPUT POWER (WPEP) 4/8 100 Pout, OUTPUT POWER (W) Pin, INPUT POW ER (W ) 180 Pin = 5 W Vdd = 32 V Idq = 2 x 200 mA f = 860 MHz 150 Pin = 2.5 W 120 90 Pin = 1.25 W 60 30 0 150 12 16 20 24 28 Vds, DRAIN VOLTAGE (V) 32 36 SD56120M TEST CIRCUIT SCHEMATIC D.U.T. NOTEs: 1. C3 AND C4 ADJACENT TO EACH OTHER 2. GAP BETWEEN GROUND & TRANSMISSION LINE = 0.056 [1.42] TYP. REF. 7248365A TEST CIRCUIT COMPONENT PART LIST COMPONENT C1, C2, C10, C11 C3 C4, C8 C5, C9 C6 C7 C12, C15, C18, C22 C13, C16, C20, C24 C14, C17, C21, C25 C19, C23 R1, R2, R3, R4 R5, R6 B1, B2 L1, L2 FB1, FB2 PCB DESCRIPTION 51 pF ATC 100B SURFACE MOUNT CERAMIC CHIP CAPACITOR 9.1 pF ATC 100B SURFACE MOUNT CERAMIC CHIP CAPACITOR 0.6 - 4.5 GIGATRIM VARIABLE CAPACITOR 5.6 pF ATC 100B SURFACE MOUNT CERAMIC CHIP CAPACITOR 12 pF ATC 100A SURFACE MOUNT CERAMIC CHIP CAPACITOR 13 pF ATC 100B SURFACE MOUNT CERAMIC CHIP CAPACITOR 91 pF ATC 100B SURFACE MOUNT CERAMIC CHIP CAPACITOR 10 µF 50V ALUMINUM ELECTROLYTIC RADIAL LEAD CAPACITOR 0.1 µF 500V SURFACE MOUNT CERAMIC CHIP CAPACITOR 100 µF 63V ALUMINUM ELECTROLYTIC RADIAL LEAD CAPACITOR 200 OHM 1/4 W SURFACE MOUNT CHIP RESISTOR 1.8 OHM 1/4 W SURFACE MOUNT CHIP RESISTOR BALUN, 25 OHM SEMI-RIDGE OD=”0.141”, 2.37 LG COAXIAL CABLE OR EQUIVALENT CHIP INDICATOR 10 nH SURFACE MOUNT COIL SURFACE MOUNT EMI SHIELD BEAD WOVEN GLASS REINFORCED / CERAMIC FILLED 0.030” THK εr = 3.48, 2 Oz ED CU BOTH SIDES 5/8 SD56120M TEST FIXTURE 4 inches TEST CIRCUIT PHOTOMASTER 6.4 inches 6/8 SD56120M M252 (.400 x .860 4L BAL N/HERM W/FLG) MECHANICAL DATA mm DIM. A MIN. TYP. 8.13 B Inch MAX MIN. 8.64 .320 10.80 TYP. MAX .340 .425 C 3.00 3.30 .118 .130 D 9.65 9.91 .380 .390 E 2.16 2.92 .085 .115 F 21.97 22.23 .865 .875 G 27.94 1.100 H 33.91 34.16 1.335 1.345 I 0.10 0.15 .004 .006 J 1.52 1.78 .060 .070 K 2.36 2.74 .093 .108 L 4.57 5.33 .180 .210 M 9.96 10.34 .392 .407 N 21.64 22.05 .852 .868 Controlling dimension: Inches 1022783C 7/8 SD56120M Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. 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