M62342GP 8-Bit, 2-Channel D-A Converter (Buffered) REJ03F0074-0100Z Rev.1.0 Sep.19.2003 Description The M62342GP is a CMOS-structure semiconductor integrated circuit incorporating two 8-bit D-A converter channels with output buffer op-amps. Serial data transfer type input can easily be used through a combination of three lines: DI, CLK, and LD. Outputs incorporate buffer op-amps that have a drive capacity of 1 mA or above for both sink and source, and can operate over the entire voltage range from almost ground to VCC (0 to 5 V), making peripheral elements unnecessary and enabling configuration of a system with few component parts. This product is currently under development, and specifications and other details may be modified at a future date. Features • Data transfer format 10-bit serial data input type • Output buffer op-amps Operable over entire voltage range from almost ground to VCC (0 to 5 V) • High output current capacity ±1 mA or higher Application Signal gain setting and automatic adjustment in DSC, CTV, and display monitors, conversion from digital data to analog data in consumer and industrial products Pin Connection Diagram (Top View) AO1 AO2 N.C. VCC 1 2 3 4 M62342GP 8 7 6 5 LD CLK DI GND N.C (Not connected) Packages: Package: 8P2J Rev.1.0, Sep.19.2003, page 1 of 6 M62342GP Block Diagram VCC LD CLK DI 5 8 7 6 GND 5 10-bit shift register Power-on reset Channel decoder 8 8-bit latch 8-bit latch 8-bit uppe segment R-2R 8-bit uppe segment R-2R + + - - 1 2 3 AO1 AO2 N.C. Pin Description Pin No. Symbol Function 6 7 DI CLK Serial data input pin. Inputs serial data with a 10-bit data length. Serial clock input pin. Input signal from DI pin is input to 10-bit shift register at rise of shift clock. 8 LD 1 Ao1 2 3 Ao2 N.C. Load pin. When “H” level is input to LD pin, value in 10-bit shift register is loaded into decoder and D-A output register. 8-bit resolution D-A converter output pins (After power-on, all channels are reset and DAC data 00h is output.) 4 5 Vcc GND (Not connected) Power supply voltage pin GND pin Rev.1.0, Sep.19.2003, page 2 of 6 M62342GP Digital Data Format Last LSB D0 First MSB D1 D2 D3 D4 D5 D6 D7 D8 D9 For channel address For D-A output D-A Data D0 D1 D2 D3 D4 D5 D6 D7 D-A output 0 0 0 0 0 0 0 0 Vcc/256×1 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 Vcc/256×2 Vcc/256×3 1 ⋅⋅ ⋅ 1 ⋅⋅ ⋅ 0 ⋅⋅ ⋅ 0 ⋅⋅ ⋅ 0 ⋅⋅ ⋅ 0 ⋅⋅ ⋅ 0 ⋅⋅ ⋅ 0 ⋅⋅ ⋅ Vcc/256×4 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Vcc/256×255 Vcc/256×256 ⋅⋅ ⋅ Channel Select Data D8 D9 Channel Selection 0 0 AO1 selected 1 0 0 1 AO2 selected Don’t care 1 1 Don’t care Data Timing Chart (Model) DI D9 D8 D7 CLK LD D-A output Rev.1.0, Sep.19.2003, page 3 of 6 D6 ••• ••• D3 D2 D1 D0 M62342GP Absolute Maximum Ratings Item Symbol Rated Value Unit Power supply voltage VCC -0.3 to 7.0 V Input voltage Vin -0.3 to Vcc+0.3 ≤ 7.0 V Output voltage Internal power consumption Vo Pd -0.3 to Vcc+0.3 ≤ 7.0 200 V mW Operating ambient temperature Storage temperature Topr Tstg -20 to +85 -55 to +125 °C °C Electrical Characteristics (Unless specified otherwise, VCC = +5 V ±10%, GND = 0 V, Ta = -20ºC to 85ºC) Specification Values Item Symbol Min. Typ. Max. Unit Test Conditions Power supply voltage Power supply current Vcc Icc 2.7 0 5.0 0.7 5.5 2.5 V mA IILK 0 −10 0.5 Input leakage current 1.6 10 µA Input voltage “L” Input voltage “H” VIL VIH 0 0.5Vcc 0.2Vcc Vcc V V Buffer amp output voltage range VAO 0.1 0.1 Vcc−0.1 Vcc−0.2 V IAO = ±100 µA IAO = ±500 µA Buffer amp output drive range Differential nonlinearity error IAO −1.0 1.0 mA SDL −1.0 1.0 LSB Upper saturation voltage = 0.3 V Lower saturation voltage = 0.2 V Vcc = 5.12V (20mV/LSB) No load (IAO = 0) Nonlinearity error Zero point error SL SZERO −1.5 −2.0 1.5 2.0 LSB LSB Full-scale error Oscillation limit output capacitance SFULL Co −2.0 2.0 0.1 LSB µF Buffer amp output impedance Ro At CLK = 1 MHz operation, IAO = 0 µA D-A data: 6 Ah (at maximum current) DI = CLK = LD = GND, IAO = 0µA VIN = 0 to Vcc 5.0 AC Characteristics (Unless specified otherwise, VCC = +5 V ±10%, GND = 0 V, Ta = -20ºC to 85ºC) Specification Values Item Symbol Min. Clock “L” pulse width tCKL 200 ns Clock “H” pulse width Clock rise time tCKH tCR 200 ns ns Clock fall time Data setup time tCF tDCH 30 ns ns Data hold time Load setup time tCHD tCHL 60 200 ns ns Load hold time Load “H” pulse width tLDC tLDH 100 100 ns ns D-A output settling time tLDD Rev.1.0, Sep.19.2003, page 4 of 6 Typ. Max. 200 200 300 Unit µs Test Conditions Until output reaches last 1/2 LSB M62342GP Timing Chart t CR t CKH t CF CLK t CKL t LDC DI t LDH t DCH t CHD t CHL LD t LDD D-A output Usage Notes 1. With this IC, D-A converter upper reference voltage setting is performed by means of the power supply voltage. If ripples or spikes are imposed on this pin, conversion accuracy may fall. When using this IC, a capacitor must be inserted between the power supply pin and GND in order to ensure stable D-A conversion. 2. The output buffer amps of this IC are highly tolerant of capacitive loads. Therefore, connecting capacitors (0.1 µF max.) between the output pins and ground in order to eliminate jitter or noise due to output line wiring presents no problems whatever in terms of operation. Sample Standard Application Circuit 1 AO1 Analog voltage output pins LD 8 CLK 7 DI 6 2 AO2 M62342GP 3 N.C. 4 VCC 5V Rev.1.0, Sep.19.2003, page 5 of 6 + 10µF GND 5 MCU G HE EIAJ Package Code SSOP8-P-175-0.65 Z1 E Rev.1.0, Sep.19.2003, page 6 of 6 e 1 8 z D b y Detail G 4 5 JEDEC Code – x M Weight(g) Detail F A2 A A1 F Lead Material Cu Alloy c L Symbol e1 b2 e1 I2 A A1 A2 b c D E e HE L L1 z Z1 x y b2 Dimension in Millimeters Min Nom Max – – 1.2 0 0.2 0.1 – 1.0 – 0.2 0.25 0.32 0.14 0.15 0.2 2.9 3.0 3.1 4.3 4.4 4.5 – 0.65 – 6.2 6.4 6.6 0.3 0.5 0.7 – 1.0 – – 0.525 – – – 0.675 – – 0.13 – – 0.1 0° – 8° – 0.35 – – 5.8 – 1.0 – – Recommended Mount Pad e Plastic 8pin 175mil SSOP I2 8P2J-A M62342GP Package Dimensions L1 Sales Strategic Planning Div. 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