NOV. 1996 Rev. 2.1 8-BIT SINGLE CHIP MICROCOMPUTER GMS84512 / 84524 USER’S MANUAL HYUNDAI MicroElectronics GMS84512/84524 USER’S MANUAL Table of Contents 1. Overview 2. CPU 3. Peripheral Function 4. Control Function 5. Support Tool 6. Appendix 1. Overview 1. Features 2. Block Diagram 3. Summary Of Peripheral Function Register 4. Pin Assignment 5. Pin Description 6. Terminal Types 2. CPU 1. Registers 2. Memory Space 3. Peripheral Function 1. PORT 2. Clock Generation Circuit 3. Timer 4. A/D Comparator 5. Serial I/O 6. PWM 7. Interrupt Interval Measurement Circuit 8. On Screen Display 4. Control Function 1. Interrupts 2. Standby Function 3. Reset Function 5. Support Tool 1. Emulator 2. Debugger 3. Assembler 4. Linker 5. Font Editor 6. OTP Chip 6. Appendix l Electrical Data l Package Outline GMS 84512 / 84524 An 8-bit microcomputer using the G8MC Core is a single-chip microcomputer including several peripheral functions such as Timer, I/O Comparator, Serial I/O, PWM, Watch-dog Timer and On-Screen Display. 1.1 FEATURES l l l l l l l l l l l l l l l l ROM RAM Minimum instruction execution time I/O PORT Serial I/O A/D Comparator Pulse Width Modulation Timer - Timer/Counter - Basic Interval Timer - Watch Dog Timer Interrupt Interval estimation circuit Interrupt Sources Pulse ( T2048 ) Output Function On Screen Display - Kinds of character - Construction of character - Size of character - Number of display character - Display colors - Color Edge, Smoothing Function Power Save Mode Operating Voltage Package OTP chip 12,288 Bytes ( GMS84512 ) 24,576Bytes ( GMS84524 ) 256 Bytes 1 us ( @ Xin = 4 MHz ) 42 ( INPUT: 3, OUTPUT: 10, I/O: 29 ) 8-bit X 1 ch. ( 1MHz, 500KHz, 250 KHz, Ext. clock ) 5-bit X 4 ch. ( max. 1 LSB ) 14-bit X 1 ch. 7-bit X 8 ch. 8 bit X 4 ch. ( 16-bit X 2 ch is Acceptable) 8 bit X 1 ch. for Remocon signal receiving 14 sources Period : 2,048 us, Duty: 50 % 128 kinds (include 2 test characters) 14 dots X 18 dots 4 X 4 kinds 22 Characters X 3 lines ( Max. 12 lines) 8 kinds STOP mode 4.5 ~ 5.5 V 52 SDIP GMS84512T/84524T 1-1 GMS 84512 / 84524 R50/ R R51/ G R52/ B R53/ Y R15/ Cin1 R16/ Cin2 R45/ PWM0 R44/ PWM1 R43/ PWM2 R42/ PWM3 R41/ PWM4 R40/ PWM5 R37/ PWM6 R36/ PWM7 R32/ PWM8 OSC2 A/D COMP. OSD OSC1 PWM TEST Vdd Vss G8MC CORE RAM R2 PORT R40 ~ R45 R20 ~ R27 R50 ~ R53 R17 R10 ~ R16 R00 ~ R07 R30 ~ R31 R32 ~ R37 R4 PORT R3 PORT R0 PORT ( 256 byte ) WATCH DOG TIMER ROM ( 12K / 24K) R5 PORT R1 PORT INTERRUPT CONTROLLER REMOCON / B.I.T. PRESCALER SYSTEM CON. CLOCK GEN./ Xout R30/ INT1 VD SERIAL I/O Xin R31/ INT2 HD TIMER RESET R17/ Cin0/ INT3 R35/ Sin/ Cin3 R34/ Sclk R33/ Sout R27/ EC3 R26/ EC2 1-2 BLOCK DIAGRAM 1.2 GMS 84512 / 84524 1.2 Peripheral Function Overview BLOCK Function Prescaler is consists of 10 bits binary counter, and divide oscillation clock. PRESCALER The divided output from each bit of prescaler provided to peripheral hardware. B.I.T a 8 bit binary counter has a function such as security of oscillation / B.I.T. stabilization time, generation of basic interval time interrupt as watch function, providing the clock for watch-dog timer WDT is consist of 6-bit binary counter, WDTR(Watch-Dog Timer Register), and WATCH-DOG comparator, input clock of WDT is provided by Basic Interval Timer interrupt and maximum output cycle is 4 seconds. -TIMER When WDTOM is ‘1’, the output of WDT reset the Device. Timer is an 8 bit binary counter and consisted of T0, T1, T2, T3. As an 8-bit binary counter, each T0, T1 can be used 16-bit interval Timer to connect each other. As an 8 bit binary counter/event counter each T2, T3 can TIMER / be used 16-bit/event counter to connect each other. COUNTER At 4 MHz oscillation, Maximum interval time of T0 is 8.192 ms, T1 is 2048 ms, T0-T1 is about 2 seconds, T2 is 2.048 ms, T3 is 512 uS,T2-T3 is about 0.5 seconds A/D Comparator has 5 bit resolution, and 4 input channel. It has sample and A/D COMPhold function of input. At 4 MHz it takes about 8 uS to compare. Error is less ARATOR than 1/2 LSB. It is 8 bit clock synchronous serial interface unit, the clock transmission cycle is 1uS,2uS,4uS Which can be selected external clock. When IOSW(Bit 6 Of SERIAL I/O Serial I/O Mode Register) is ‘1’, R33 pin operates Sout at transmission mode, Sin at receiving mode. PWM is consists of 14 bit PWM 1 ch and 7 bit PWM 8 ch. PWM 14 bit PWM has 0.5 uS minimum resolution width, 8192 uS cycle time, 7 bit ( Pulse Width PWM has 8uS minimum resolution 8 uS,1024uS, cycle time. The polarity of Modulation ) PWM output can be assign by Software. Interrupt interval measurement circuit consists of 8 bit binary counter, interrupt INTERRUPT interval saving circuit. It can select 32uS, 64uS as a measurement clock . Because it can select external signal edge, measurement of input signal cycle INTERVAL or pulse width is possible. So it can be used Remocon receiving. INDEX 3 - 13 3 -16 3 - 19 3 - 26 3 - 28 3 - 32 3 - 38 MEASUREMENT CIRCUIT OSD ( On-ScreenDisplay ) Maximum number of character or symbol displayed in CRT is 128 basically displayed by 22 characters X 3 lines. Maximum 12 lines is possible with OSD interrupt. OSD clock can use 4 MHz ~ 8 MHz size of display character is 16 kinds, it can be used by line unit. The color of display character is 8 kinds it can be used by character unit. In display mode, there are character mode, background mode, color mode, and Blanking mode, it can be used by line unit especially smoothing function and OSD oscillator control function exists. 3 - 41 1-3 GMS 84512 / 84524 1.4 1 52 R50/ R VD 2 51 R51/ G R45/ PWM0 3 50 R52/ B R44/ PWM1 4 49 R53/ Y R43/ PWM2 5 48 R00 R42/ PWM3 6 47 R01 R41/ PWM4 7 46 R02 R40/ PWM5 8 45 R03 R37/ PWM6 9 44 R04 R36/ PWM7 10 43 R05 R35/ Sin/ Cin3 11 42 R06 R34/ Sclk 12 41 R07 R33/ Sout 13 40 R10 R32/ PWM8 14 39 R11 R31/ INT2 15 38 R12 R30/ INT1 16 37 R13 R27/ EC3 17 36 R14 R26/ EC2 18 35 R15/ Cin1 R25/ T2048 19 34 R16/ Cin2 R24 20 33 R17/ Cin0/ INT3 R23 21 32 R20 R22 22 31 R21 TEST 23 30 RESET Xin 24 29 OSC1 Xout 25 28 OSC2 Vss 26 27 Vdd HME HD GMS84512/84524 1-4 PIN ASSIGNMENT GMS 84512 / 84524 1.5 PIN DESCRIPTION Classification No. Symbol I/O Function 27 Vdd Input Power supply (4.5~5.5V) Power System Control or Clock 26 Vss 23 TEST Type Remark Input Ground (0V) Input TEST Input pin At 'L' input: SINGLE CHIP MODE IA At 'H' input : TEST MODE 24 Xin Input CRYSTAL connection pin (with Xout) If an external clock is used, Xin pin should be connected external clock source 25 Xout Output CRYSTAL connection pin(with Xin) If an external clock used, Xout pin should be open 30 RESET Input In the state of 'L' level, system IA enter the reset state OSD PWM SCI TIMER 1 HD Input Horizontal synchronizing signal input pin 2 VD Input Vertical synchronizing signal input pin IA 28 OSC2 Ouptut Clock output for OSD 29 OSC1 49 Y Output Switching signal output pin 50 B Output BLUE signal output pin 51 G Output GREEN signal output pin R51 share 52 R Output RED signal output pin R50 share Input Clock input for OSD R53 share OA R52 share 3 PWM0 Output Pulse width modulation output pin R45 share 4 PWM1 Output (7BIT PWM) R44 share 5 PWM2 Output 6 PWM3 Output R42 share 7 PWM4 Output R41 share 8 PWM5 Output R40 share 9 PWM6 Output 10 PWM7 Output 14 PWM8 Output 14BIT PWM output pin 19 T2048 Output Pulse(2048uS) output pin 11 Sin 12 Sclk 13 Sout 17 EC3 OB IOF R37 share R36 share Input Serial Data Input pin I/O R43 share Serial Clock I/O pin IOD R25 share IOE R35 share IOG R34 share Output Serial Data output pin Input Event Counter input pin R32 share R33 share IOB R27 share 1-5 GMS 84512 / 84524 1-6 ~ INT2 INT1 INT3 Cin3 Cin0 Cin2 Cin1 R07 48 33 34 R00 R17 R16 I/O Input Input Input Input Input Input Input I/O I/O Input I/O Function External interrupt request input pin (INT1,INT2 : Remocon input capture Input possible) Analog input pin (Default selection : Cin0) TYPE Remarks IB IC IOE IC IOC R31 share R30 share R17 share R35 share R17 share R16 share R15 share R0 Port (Can assigned I/O state bit by bit by R0DD) IOA R1 Port ( R17 Input only ) ( 7 ports of R10~R16 can assigned I/O IC IOC state bit by bit by R1DD ~ I/O Port 15 16 33 11 33 34 35 41 ~ A/D Comparator NO. Symbol ~ Classification Interrupt 40 17 18 19 20 21 22 R10 R27 R26 R25 R24 R23 R22 I/O I/O I/O I/O I/O I/O I/O 31 32 9 10 11 R21 R20 R37 R36 R35 I/O I/O I/O I/O I/O 12 13 14 15 16 3 4 5 6 R34 R33 R32 R31 R30 R45 R44 R43 R42 I/O I/O I/O Input ( R30,R31 is input only) Input Output R4 Port Output ( 6 bit output only ) Output Output 7 8 49 R41 R40 R53 Output Output Output R5 Port 50 51 52 R52 R51 R50 Output ( 4 bit output only ) Output Output R2 Port ( Can assigned I/O state bit by bit by R2DD) Cin0/INT3 share Cin2 shrae Cin1 share IOA IOB IOD EC3 share EC2 share T2048 share IOA R3 PORT ( 6 Bits of R31~R32 can assigned I/O state bit by bit by R3DD IOB PWM6 share PWM7 share IOE Sin/Cin3 share IOG Sclk share Sout share PWM8 share INT2 share INT1 share PWM0 share PWM1 share PWM2 share PWM3 share IOD IB OB PWM4 share PWM5 share Y share OA B share G share R share GMS 84512 / 84524 1.6 TERMINAL TYPES PIN TERMINAL TYPE Vdd at RESET Vdd Xin Xin Xout Oscillation Vdd Vss Vss Vss Xout STOP Vss Vdd Xin OSC1 OSC2 Oscillation Stop Vdd Vdd Vss Vss Xout Vss OSDON Vss Vss IA type Vdd RESET HD VD RST I ( “L” ) H Sync V sync SCHMITT Input Hi-Z Vss TEST Test Pin is using normal gate IB type Vdd R30/ INT1 R31/ INT2 Rd I Data Bus Hi-Z Vss INT1,INT2 SCHMITT Input IC type Vdd R17/ Cin0 / INT3 Rd I Data Bus Hi-Z INT1,INT2 Vss SCHMITT Input Cin3 1-7 GMS 84512 / 84524 PIN TERMINAL TYPE at RESET OA type R50/ R R51/ G R52/ B R53/ Y Selection Vdd R, G, B, Y Data Bus Vdd MUX O Hi-Z Data REG. Vss Vss OB type R45/ PWM0 R44/ PWM1 R43/ PWM2 R42/ PWM3 R41/ PWM4 R40/ PWM5 Selection O PWM0 ¡ -PWM5 Hi-Z MUX Data REG. Data Bus Vss Vss IOA type Vdd R00 ~ R07 R10 ~ R14 R20 ~ R24 Data Bus Data Bus Vdd Data REG. IO Hi-Z IO Hi-Z Direction REG. Vss Vss MUX Data Bus Rd IOB type Vdd Data Bus R26/ EC2 R27/ EC3 Data Bus Direction REG. Vss MUX Data Bus Rd EC2, EC3 SCHMITT input 1-8 Vdd Data REG. Vss GMS 84512 / 84524 PIN TERMINAL TYPE at RESET IOC type Vdd Vdd Data REG. Data Bus IO R15/ Cin1 R16/ Cin2 Hi-Z Direction REG. Data Bus Vss Vss MUX Data Bus Rd Cin1, Cin2 IOD type Selection Vdd T2048, PWM8 R25/ T2048 R32/ PWM8 Vdd MUX Data Bus Data REG. Data Bus Direction REG. IO Vss Hi-Z Vss MUX Data Bus Rd IOE type Selection Vdd Vdd Data REG. Data Bus IO R35/ Sin / Cin4 Direction REG. Data Bus Hi-Z Vss MUX Data Bus Vss SCHMITT input Rd Sin Cin4 1-9 GMS 84512 / 84524 PIN TERMINAL TYPE at RESET IOF type Selection IO PWM6,PWM7 R36/ PWM7 R37/ PWM6 MUX Data REG. Data Bus Vss Data Bus Hi-Z Vss Direction REG. MUX Data Bus Rd IOG type Selection IO PWM6,PWM7 Data Bus R34/ Sclk R33/ Sout MUX Data REG. Vss Data Bus Data Bus Direction REG. MUX SCHMITT input Rd 1 - 10 Vss Hi-Z GMS84512/84524 USER’S MANUAL Table of Contents 1. Overview 2. CPU 3. Peripheral Function 4. Control Function 5. Support Tool 6. Appendix GMS 84512 / 84524 2.1. REGISTERS 15 87 0 PCH Program Counter PCL 7 0 A - Register A 15 8 7 0 Y ( YA 16bit Accumulator ) A 7 0 X - Register X 7 0 Y - Register Y 7 0 Stack Pointer *1 SP 7 0 Program Status PSW N V G B H I Z Word C Carry Flag Zero Flag Interrupt Enable Flag Half Carry Flag Break Flag G ( Direct Page ) Flag Overflow Flag Negative Flag *1 STACK ADDRESS ( 0100H ~ 013FH ) 15 8 7 01H 0 SP Hardware fixed 2-1 GMS 84512 / 84524 2.1.1. A - Register l 8 bit Accumulator l In the case of 16-bit operation, compose the lower 8-bit of YA (16-bit Accumulator) l In the case of multiplication instruction, execute as a multiplier register. After multiplication operation, the lower 8-bit of the result enters. (Y * A → YA) l In the case of division instruction, execute as the lower 8-bit of dividend. After division operation, quotient enters. (YA ¡À X ¡æ Q: A , 2.1.2. R: Y ) X- Register l General-purpose 8-bit register l In the case of index addressing mode within direct page(RAM area), execute as index register l In the case of G mode operation, execute as destination address register. The operation result enters into memory indirectly addressed by X register. l 2.1.3. In the case of division instruction, execute as divisor register. Y- Register l General-purpose 8-bit register l In the case of index addressing mode, execute as index register l In the case of 16-bit operation instruction, execute as the upper 8-bit of YA (16-bit accumulator). l In the case of multiplication instruction, execute as a multiplicand register. After multiplication operation, the upper 8-bit of the result enters. l In the case of division instruction, execute as the upper 8-bit of dividend. After division operation, quotient enters. l 2.1.4. l Can be used as loop counter of conditional branch command. (e.g. DBNE Y, REL) Stack Pointer In the cases of subroutine call, Interrupt and PUSH, POP, RETI, RET instruction, stack data on RAM or in the case of returning, assign the storage location having stacked data. l Stack area is constrained within 1-page (00H-FFH). Page is fixed by H/W. User can only assign the lower address. At the initial stage, stack pointer should be initialized to 2-2 GMS 84512 / 84524 point to RAM area having H/W. ¨çInterrupt M (sp) ¡ç ( PCH ) M (sp) ¡ç ( PCL ) M (sp) ¡ç ( PSW ) sp ¡ç sp - 1 sp ¡ç sp - 1 sp ¡ç sp - 1 sp ¡ç sp + 1 sp ¡ç sp + 1 sp ¡ç sp + 1 ( PSW ) ¡ç M (sp) ( PCL ) ¡ç M (sp) ( PCH) ¡ç M (sp) ¨èRETI ¨éSubroutine CALL M (sp) ¡ç ( PCH ) M (sp) ¡ç PCL ) sp ¡ç sp - 1 sp ¡ç sp - 1 sp ¡ç sp + 1 sp ¡ç sp + 1 ¨êRET ( PCL ) ¡ç M (sp) ¨ëPUSH A ( X, Y, ( PCH) ¡ç M (sp) PSW ) M (sp) ¡ç A sp ¡ç sp - 1 ¨ìPOP A ( X, Y, PSW ) sp ¡ç sp + 1 A ¡ç M (sp) 2-3 GMS 84512 / 84524 2.1.5. Program Counter ( PC ) l Program counter is a 16-bit counter consisted of 8-bit register PCH and PCL. l Addressing space is 64K bytes. l In reset state, Reset routine address in address FFFFH and FFFEH enter into PC. 2.1.6. Program Status Word( PSW ) l PSW is an 8-bit register. l Consisted of the flags to show the post state of operation and the flags determining the CPU operation, initialized as 00H in reset state. PSW 7 6 5 4 3 2 1 0 N V G B H I Z C ¨ ç Carry Flag ( C ) l After operation, set when there is a carry from bit7 of ALU or there is not a borrow. l Set by SETC and clear by CLRC. l Executable as 1-bit accumulator. l Branch condition flag of BCS, BCC. ¨ è Zero Flag ( Z ) l After operation also including 16-bit operation, set if the result is “0”. l Branch condition flag of BEQ, BNE. ¨ é Interrupt Enable Flag ( I ) l Master enable flag of interrupt except for RST(reset). l Set and cleared by EI, DI . ¨ ê Half Carry Flag ( H ) l After operation, set when there is a carry from bit3 of ALU or there is not a borrow from bit4 of ALU. 2-4 l Can not be set by any instruction. l Cleared by CLRV instruction like V flag. GMS 84512 / 84524 ¨ ë Break Flag ( B ) l Set by BRK (S/W interrupt) instruction to distinguish BRK and TCALL instruction having the same vector address. ¨ ì Direct Page Flag ( G ) l Assign direct page (0-page, 1-page). l Set and cleared by SETG, CLRG instruction. l If used with PG2R(00FCH ) it is enable to access 2-page ( OSD RAM ). G-flag PG2R Direct Page 0 - 0 - Page Access 1 0 1 - Page Access 1 2 - Page Access *NOTICE : Always after clearing, PG2R is enable to be accessed for it is the register of 0-page ¨ í Overflow Flag ( V ) l After operation, set when overflow or underflow occurs. l In the case of BIT instruction, bit6 of memory location is input to V-flag. l Cleared by CLRV instruction, but not set by any instruction. l Branch condition flag of BVS, BVC. ¨ î Negative Flag ( N ) l N-flag is set whenever the result of a data transfer or operation is negative (bit7 isset to “1”). l In the case of BIT instruction, bit7 of memory location is inputted to N-flag l No CLEAR and SET instruction. l Branch condition flag of BPL, BMI. 2-5 GMS 84512 / 84524 2.2 MEMORY SPACE The memory space of GMS84512/84524 is 64K byte, it is equipped with RAM area, OSD RAM area, FONT ROM area and PROGRAM ROM area. 2.2.1. RAM area 0-PAGE ( 0000H ~ 00FF H ) RAM 192 Bytes ( 0000H ~ 00BF H ) and peripheral function register( 00C0H ~ 00FF H ) 1-PAGE ( 0100 H ~ 013F H ) RAM 64 Bytes ( 0100H ~ 013F H ) and STACK area 2-PAGE ( 0200 H ~ 02D5 H ) OSD RAM 182 Bytes ( 0200H ~ 02D5 H ) 2.2.2. FONT ROM area ( 2000H ~ 3FFFH ) 128 character OSD FONT 2.2.3. PROGRAM ROM area Approximately ROM memory is 12 K bytes and it is domain of User Program. The highest page(FF00H ~ FFFF H ) is called U- Page and it is utilized domain as following. PCALL area ( FF00 H ~ FFBF H ) Domain of jumping at PCALL instruction TCALL Vector area ( FFC0 H ~ FFDF H ) Storage domain of vector address at TCALL instruction. Interrupt Vector area ( FFE0 H ~ FFFF H ) Storage domin of interrupt vector address,inclusive RESET 2-6 GMS 84512 / 84524 MEMORY MAP (GMS84512/84524 ) 0000H RAM 00BFH 00FFH ( 192 Bytes ) 0-PAGE PERIPHERAL REGISTERS 0100H 013FH RAM ( STACK ) ( 64 Bytes ) DIRECT-PAGE 1-PAGE No H/W 0200H OSD RAM ( 182 Bytes ) 2-PAGE 02D5H No H/W 2000H FONT ROM ( 8 K bytes ) 3FFFH No H/W A000H GMS84524 ( 24K Bytes ) PROGRAM ROM D000H GMS84512 ( 12K Bytes ) FF00H FFC0H FFE0H FFFFH PCALL AREA TCALL VECTOR AREA U-PAGE INTERRUPT VECTOR AREA 2-7 GMS 84512 / 84524 TABLE 2.1. PERIPHERALREGISTER LIST Address SYMBOL R/W RESET VALUE Register Name Page 7 6 5 4 3 2 1 0 00C0H R0 PORT DATA 00C1H R0 PORT I/O 00C2H R1 PORT DATA 00C3H R1 PORT I/O 00C4H R2 00C5H R2 PORT I/O 00C6H R3 PORT DATA 00C7H R3 PORT I/O DIRECTION 00C8H R4 PORT DATA 00C9H R5 PORT DATA 00CAH PORT FUNCTION 00CBH EXT. INTERRUPT 00CCH OPERATION 00CEH BASIC PORT CLOCK REGISTER R0 R/W Undefined 3-1 R0DD W 0 0 0 0 0 0 0 0 3-1 R1 R/W Undefined 3-2 R1DD W - 0 0 0 0 0 0 0 3-2 R2 R/W Undefined 3-4 R2DD W 0 0 0 0 0 0 0 0 3-4 R3 R/W Undefined 3-6 R3DD W REGISTER R4 R/W - - REGISTER R5 R/W - - - - Undefined 3 - 10 FUNC W - - - 0 0 0 0 0 3-3 IEDS W - - 0 0 0 0 0 0 3 - 39 TMR W - - - - - 0 0 0 ¡ ª BITR R Undefined 3 - 16 CKCTLR W - - 0 1 0 1 1 1 3 - 13 WDTR W - 0 1 1 1 1 1 1 3 - 17 DIRECTION REGISTER REGISTER DIRECTION DATA REGISTER REGISTER DIRECTION REGISTER REGISTER SELECTION EDGE MODE INTERVAL REGISTER REGISTER SELECTION REGISTER REGISTER TIMER REGISTER CONTROL REGISTER REGISTER - 3-6 Undefined 3-9 00CFH WATCH-DOG 00D0H TIMER MODE REGISTER0 TM0 R/W - 0 0 0 0 0 0 0 3 - 21 00D1H TIMER MODE REGISTER2 TM2 R/W - 0 0 0 0 0 0 0 3 - 21 00D2H TIMER0 DATA REGISTER TDR0 R/W Undefined 3 - 21 00D3H TIMER1 DATA REGISTER TDR1 R/W Undefined 3 - 21 00D4H TIMER2 DATA REGISTER TDR2 R/W Undefined 3 - 21 00D5H TIMER3 DATA REGISTER TDR3 R/W Undefined 3 - 21 00D6H A/D COMPARATOR CMR W *6 0 0 - 0 0 0 0 0 3 - 27 00D7H A/D COMP. CHANNEL CIS W - - - - - - 0 0 3 - 27 00D8H SERIAL I/O MODE R/W *0 - 0 0 0 0 0 0 1 3 - 29 00D9H SERIAL I/O DATA 00DAH PWM0 DATA 00DBH PWM1 00DCH 00DDH 2-8 TIMER 0 0 0 0 0 0 - MODE REGISTER SELECTION REGISTER REGISTER REGISTER SIOM SIOR R/W REGISTER PWMR0 W - Undefined 3 - 35 DATA REGISTER PWMR1 W - Undefined 3 - 35 PWM2 DATA REGISTER PWMR2 W - Undefined 3 - 35 PWM3 DATA REGISTER PWMR3 W - Undefined 3 - 35 Undefined 3 - 28 GMS 84512 / 84524 Address SYMBOL R/W RESET VALUE Register Name Page 7 6 5 4 3 2 1 0 00DEH PWM4 DATA REGISTER PWMR4 W - Undefined 3 - 35 00DFH PWM5 DATA REGISTER PWMR5 W - Undefined 3 - 35 00E0H PWM6 DATA REGISTER PWMR6 W - Undefined 3 - 35 00E1H PWM7 DATA REGISTER PWMR7 W - Undefined 3 - 35 00E2H PWM8 DATA REGISTER HIGH PWM8H R/W 00E3H PWM8 DATA REGISTER LOW PWM8L R/W - - Undefined 3 - 36 00E4H PWM CONTROL REGISTER1 PWMCR1 R/W 0 0 0 0 0 0 0 0 3 - 37 00E5H PWM CONTROL REGISTER2 PWMCR2 R/W - - - 0 0 0 0 0 3 - 37 00E6H INTERRUPT MODE IMOD R/W - - 0 0 0 0 0 0 4-4 00E8H INTERRUPT ENABLE IENL R/W 0 0 0 0 0 - - - 4-3 00E9H INTERRUPT REQUEST IRQL R/W 0 0 0 0 0 - - - 4-4 00EAH INTERRUPT ENABLE IENH R/W 0 0 0 0 0 0 0 0 4-3 00EBH INTERRUPT REQUEST IRQH R/W 0 0 0 0 0 0 0 0 4-4 00ECH INTERRUPT INTERVAL CONTROL REGISTER DETERMINATION IDCR R/W - - - - - 0 0 0 3 - 40 00EDH INTERRUPT DETERMINATION REGISTER IDR R 0 0 0 0 0 0 0 0 3 - 38 00F0H OSD 1st LINE HDP1 W - - 0 0 0 0 0 0 3 - 47 00F1H OSD 2nd LINE HORIZONTAL POSITION REGISTER HDP2 W - - 0 0 0 0 0 0 3 - 47 00F2H OSD 3rd LINE HORIZONTAL POSITION REGISTER HDP3 W - - 0 0 0 0 0 0 3 - 47 00F3H OSD 1st LINE VERTICAL VDP1 W - 0 0 0 0 0 0 0 3 - 47 00F4H OSD 2nd LINE VERTICAL POSITION REGISTER VDP2 W - 0 0 0 0 0 0 0 3 - 47 00F5H OSD 3rd LINE VERTICAL POSITION REGISTER VDP3 W - 0 0 0 0 0 0 0 3 - 47 00F6H OSD 1st LINE DISPLAY MODE, CHARACTER SIZE, SMOOTHING FUNCTION SELECTION REGISTER DMSS1 W - 0 0 0 0 0 0 0 3 - 44 00F7H OSD 2nd LINE DISPLAY MODE, CHARACTER SIZE, SMOOTHING FUNCTION SELECTION REGISTER DMSS2 W - 0 0 0 0 0 0 0 3 - 44 00F8H OSD 3rd LINE DISPLAY MODE, CHARACTER SIZE, SMOOTHING FUNCTION SELECTION REGISTER DMSS3 W - 0 0 0 0 0 0 0 3 - 44 00F9H OSD OUTPUT REGISTER CONTROL OSDCON1 W 0 0 0 0 0 0 0 0 3 - 48 00FAH I/O POLARITY CONTROL and CONTROL REGISTER OSCILLATION OSDCON2 W 0 0 0 0 0 0 0 0 3 - 48 00FCH OSD PG2R** R/W - - - - - - - 0 3 - 43 REGISTER REGISTER FLAG INTERVAL HORIZONTAL and RAM ( 2 page ) REGISTER REGISTER FLAG LOW HIGH REGISTER POSITION POSITION BACKGROUND OSD ACCESSABLE LOW HIGH REGISTER REGISTER REGISTER 3 - 36 Undefined ¡ Ø -: Not used *0: READ only for bit 0 *6: READ only for bit 6 ¡Ø Write Only Register can not be accessed by bit manipulation instruction. ** : OSD RAM area (2-page) can be accessed by LDM,SET1 2-9 GMS 84512 / 84524 VECTOR AREA FFC0H TCALL 15 FFC1H FFC2H TCALL 14 FFC3H FFC4H TCALL 13 FFC5H FFC6H TCALL 12 FFC7H FFC8H TCALL 11 FFC9H FFCAH TCALL 10 FFCBH FFCCH TCALL 9 FFCDH FFCEH TCALL 8 FFCFH FFD0H TCALL 7 FFD1H FFD2H TCALL 6 FFD3H FFD4H TCALL 5 FFD5H FFD6H TCALL 4 FFD7H FFD8H TCALL 3 FFD9H FFDAH TCALL 2 FFDBH FFDCH TCALL 1 FFDDH FFDEH FFDFH TCALL 0 * (L) FFE0H (H) FFE1H (L) FFE2H (H) FFE3H (L) FFE4H (H) FFE5H (L) FFE6H (H) FFE7H (L) FFE8H (H) FFE9H (L) FFEAH (H) FFEBH (L) FFECH (H) FFEDH (L) FFEEH (H) FFEFH (L) FFF0H (H) FFF1H (L) FFF2H (H) FFF3H (L) FFF4H (H) FFF5H (L) FFF6H (H) FFF7H (L) FFF8H (H) FFF9H (L) FFFAH (H) FFFBH (L) FFFCH (H) FFFDH (L) FFFEH (H) FFFFH * This vector area is used in both BRK and TCALL 0 instruction 2 - 10 not used (L) (H) SERIAL I/O (L) (H) Basic Interval Timer (L) (H) Watch Dog Timer (L) (H) EXT. INT 3 (L) (H) Timer 3 (L) (H) Timer1 (L) (H) V-Sync Interrupt (L) (H) 1mS Interrupt (L) (H) Timer 2 (L) (H) Timer 0 (L) (H) EXT. INT 2 (L) (H) EXT. INT1 (L) (H) On Screen Display (L) (H) not used (L) (H) RESET (L) (H) GMS84512/84524 USER’S MANUAL Table of Contents 1. Overview 2. CPU 3. Peripheral Function 4. Control Function 5. Support Tool 6. Appendix GMS 84512 / 84524 3.1 PORT There are 6-ports in this device. You can use these ports an digital I/O or 2nd function I/O 3.1.1 R0 PORT 8-bit I/O port including direction register and port data register (IOA Type) l Register Structure and Description Register Name Symbol R/W Address Initial Value R0 I/O Direction Register R0DD W 00C1H 0000 0000 R0 PORT Data Register R0 R/W 00C0H Not initialized R0 PORT I/O DIRECTION REGISTER W W W W W W W W 7 6 5 4 3 2 1 0 R0DD <00C1H> Initial Value when RESET R0DD7 R0DD6 R0DD5 R0DD4 R0DD3 R0DD2 R0DD1 R0DD0 [ 0000 0000 ] Assign the direction of R0 port (R0DD0) is assigned to R00 port) 0 : Input 1 : Output R0 PORT DATA REGISTER R/W R/W R/W R/W R/W R/W R/W R/W 7 6 5 4 3 2 1 0 R07 R06 R05 R04 R03 R02 R01 R00 R0 <00C0H> Initial Value when RESET [Not initialized ] Port R0 output data If output mode port is read, the read data is R0 register data. And if input mode port is read, the read data is R0 pin data. 3- 1 GMS 84512 / 84524 3.1.2 R1 PORT You can use the R17 port as input mode only, but others as input or output mode. Selection Mode Pin Name R1 PORT l Port Selection 2nd Function Type 0 R10 R10 ( I/O ) R10 ( I/O ) IOA 1 R11 R11 ( I/O ) R11 ( I/O ) IOA 2 R12 R12 ( I/O ) R12 ( I/O ) IOA 3 R13 R13 ( I/O ) R13 ( I/O ) IOA 4 R14 R14 ( I/O ) R14 ( I/O ) IOA 5 R15/ Cin1 R15 ( I/O ) Cin1 ( I ) IOC 6 R16/ Cin2 R16 ( I/O ) Cin2 ( I ) IOC 7 R17/ Cin0/ INT3 R17 ( I ) Cin0/ INT3 ( I ) IC Register Structure and Description Register Name Symbol R/W Address Initial Value R1DD W 00C3H 0000 0000 R1 Port Data Register R1 R/W 00C2H Not initialized A/D COMP. Input CH. Selection Register CIS w 00D7H ---- --00 FUNC W 00CAH ---0 0000 R1 I/O Directin Register Port Function Selection Register R1 PORT I/O DIRECTION REGISTER - W W W W W W W 7 6 5 4 3 2 1 0 R1DD <00C3H> - Initial Value when Reset R1DD6 R1DD5 R1DD4 R1DD3 R1DD2 R1DD1 R1DD0 [ -000 0000 ] Assign the direction of R1 port Not used (R1DD0) is assigned to R10 port) 0 : Input 1 : Output 3-2 GMS 84512 / 84524 R1 PORT DATA REGISTER R R/W R/W R/W R/W R/W R/W R/W 7 6 5 4 3 2 1 0 R16 R15 R14 R13 R12 R11 R10 Initial Value when Reset R1 - <00C2H> Input data when read A/D COMP. Port R1 output data INPUT CHANNEL SELECTION - - - - - - W W 7 6 5 4 3 2 1 0 - - - - - - CIS1 CIS0 Initial Value when Reset CIS <00D7H> [ Not initialized ] [ ---- --00 ] Analog input channel selection 00 : CIN0 01 : CIN1 10 : CIN2 11 : CIN3 PORT Selection CIS1 CIS0 Channel 0 0 1 1 0 1 0 1 Channel 0 (Cin0) Channel 1 (Cin1) Channel 2 (Cin2) Channel 3 (Cin3) R15/ Cin1 R15 Cin1 R15 R15 R16/ Cin2 R16 R16 Cin2 R16 R17/ Cin0/ INT3 R35/ Sin/ Cin3 Cin0/ INT3 R17/ Cin0 R17/ Cin0 R17/ Cin0 R35/ Sin R35/ Sin R35/ Sin Cin3 PORT FUNCTION SELECTION REGISTER - - - W W W W W 7 6 5 4 3 2 1 0 - - - Initial value when MCU Reset FUNC <00CAH> EC3S EC2S INT3S INT2S INT1S [ ---0 0000 ] R30 / INT1 Selection R27 / EC3 Selection 0 : R27 ( I/O ) 1 : EC3 ( Input ) R26 / EC2 Selection 0 : R26 ( I/O ) 1 : EC2 ( Input ) 0 : R30 ( Input ) 1 : INT1 ( Input ) R31/ INT2 Selection 0 : R31 ( Input ) 1 : INT2 ( Input ) R17 / INT3 Selection 0 : R17 ( Input ) 1 : INT3 ( Input ) 3- 3 GMS 84512 / 84524 3.1.3 R2 PORT 8- BIT I/O Port Selection Mode Pin Name R2 PORT l Port Selection 2nd Functin Type 0 R20 R20 ( I/O ) R20 ( I/O ) IOA 1 R21 R21 ( I/O ) R21 ( I/O ) IOA 2 R22 R22 ( I/O ) R22 ( I/O ) IOA 3 R23 R23 ( I/O ) R23 ( I/O ) IOA 4 R24 R24 ( I/O ) R24 ( I/O ) IOA 5 R25/ T2048 R25 ( I/O ) T2048 ( O ) IOD 6 R26/ EC2 R26 ( I/O ) EC2 ( I ) IOB 7 R27/ EC3 R27 ( I/O ) EC3 ( I ) IOB Register Structure and Description Register Name R2 I/O Direction Register R2 Port Data Register Port Function Selection Register PWM Control Register 2 Symbol R/W Address Initial Value R2DD W 00C5H 0000 0000 R2 R/W 00C4H Not initialized FUNC W 00CAH ---0 0000 00E5H ---0 0000 PWMCR2 R/W R2 PORT I/O DIRECTION REGISTER W W W W W W W W 7 6 5 4 3 2 1 0 R2DD <00C5H> Initial value when MCU Reset R2DD7 R2DD6 R2DD5 R2DD4 R2DD3 R2DD2 R2DD1 R2DD0 [ 0000 0000 ] Assign the direction of R2 port R2DD is assigned to R20 port 0 : Input 1 : Output 3-4 GMS 84512 / 84524 R2 PORT DATA REGISTER R/W R/W R/W R/W R/W R/W R/W R/W 7 6 5 4 3 2 1 0 R27 R26 R25 R24 R23 R02 R21 R20 Initial value when MCU Reset R2 <00C4H> [ Not initialized ] Port R2 output data PORT FUNCTION SELECTION REGISTER - - - W W W W W 7 6 5 4 3 2 1 0 - - - Initial value when MCU Reset ) FUNC <00CAH> EC3S EC2S INT3S INT2S INT1S [ ---0 0000 ] R30 / INT1 Selection 0 : R30 ( Input ) 1 : INT1 ( Input ) R27 / EC3 Selection 0 : R27 ( I/O ) 1 : EC3 ( Input ) R31/ INT2 Selection 0 : R31 ( Input ) 1 : INT2 ( Input ) R26 / EC2 Selection 0 : R26 ( I/O ) 1 : EC2 ( Input ) R17 / INT3 Selection 0 : R17 ( Input ) 1 : INT3 ( Input ) PWM OUTPUT CONTROL REGISTER 2 - - - R/W R/W R/W R/W R/W 7 6 5 4 3 2 1 0 - - - EN7 EN6 Initial value when MCU Reset PWMCR2 <00E5H> T2048 POL2 POL1 R25/ T2048 Selection 0 : R25 1 :T2048 (Output rectangular wave(T=2048uS) 7-bit PWM OUTPUT Polarity 0 : Positive Polarity 1 : Negative Polarity [ ---0 0000 ] R37/ PWM6 Selection 0 : R37 1 : PWM6 R36/ PWM7 Selection 0 : R36 1 : PWM7 14-bit PWM Output Polarity 0 : Positive poarity 1 : Negative Polarity 3- 5 GMS 84512 / 84524 3.1.4 R3 PORT You can use lower 2-bits(R31, R30) of R3 port as input mode only. But others as input or output mode Selection Mode Pin Name R3 PORT l Port Selection 2nd Function Type 0 R30/ INT1 R30 ( I ) INT1 ( I ) IB 1 R31/ INT2 R31 ( I ) INT2 ( I ) IB 2 R32/ PWM8 R32 ( I/O ) PWM8 ( O ) IOD 3 R33/ Sout R33 ( I/O ) Sout ( I/O ) IOG 4 R34/ Sclk R34 ( I/O ) Sclk ( I/O ) IOG 5 R35/ Sin/ Cin3 R35 ( I/O ) Sin/ Cin3 ( I ) IOE 6 R36/ PWM7 R36 ( I/O ) PWM7 ( O ) IOF 7 R37/ PWM6 R37 ( I/O ) PWM6 ( O ) IOF Register Structure and Description Register Name Symbol R/W Address Initial Value R3DD W 00C7H 0000 0000 R3 R/W 00C6H Not Initialized Port Function Selection Register FUNC W 00CAH ---0 0000 Serial I/O Mode Register SIOM R/W 00D8H -000 0001 PWM Control Register 1 PWMCR1 R/W 00E4H 0000 0000 PWM Control Regsiter 2 PWMCR2 R/W 00E5H ---0 0000 R3 I/O Direction Register R3 Port Data Register PORT R3 I/O DIRECTION REGISTER W W W W W W - - 7 6 5 4 3 2 1 0 - - R3DD <00C7H> R3DD7 R3DD6 R3DD5 R3DD4 R3DD3 R3DD2 Not used Port R3 I/O Direction Register ( R3DD2 is assigned to R32 port ) 0 : Input 1 : Output 3-6 Initial value when MCU Reset [ 0000 00-- ] GMS 84512 / 84524 R3 PORT DATA REGISTER R/W R/W R/W R/W R/W R/W R R 7 6 5 4 3 2 1 0 R37 R36 R35 R34 R33 R32 - - Initial value when MCU Reset R3 <00C6H> [ Not initialized ] Input data when read Port R3 Output Data PORT FUNCTION SELECTION - - - W W W W W 7 6 5 4 3 2 1 0 - - - Initial vlaue when MCU Reset FUNC <00CAH> EC3S EC2S INT3S INT2S INT1S [ ---0 0000 ] R30 / INT1 Selection 0 : R30 ( Input ) 1 : INT1 ( Input ) R27 / EC3 Selection 0 : R27 ( I/O ) 1 : EC3 ( Input ) R31/ INT2 Selection 0 : R31 ( Input ) 1 : INT2 ( Input ) R26 / EC2 Selection 0 : R26 ( I/O ) 1 : EC2 ( Input ) R17 / INT3 Selection 0 : R17 ( Input ) 1 : INT3 ( Input ) PWM CONTROL REGISTER 1 R/W R/W R/W R/W R/W R/W R/W R/W 7 6 5 4 3 2 1 0 EN5 EN4 EN3 EN2 EN1 EN0 EN8 CNT Initial value when MCU Reset PWMCR1 <00E4H> 14-bit / 7-bit PWM Count Start/Stop 0 : Count Start 1 : Count Stop R40/ PWM5 Selection 0 : R40 1 : PWM5 R41/ PWM4 Selection 0 : R41 1 : PWM4 R42/ PWM3 Selection 0 : R42 R43/ PWM2 Selection 1 : PWM3 0 : R43 1 : PWM2 [ 0000 0000 ] R32/ PWM8 Selection 0 : R32 1 : PWM8 R44/ PWM1 Selection 0 : R44 1 : PWM1 R45/ PWM0 Selection 0 : R45 1 : PWM0 3- 7 GMS 84512 / 84524 PWM CONTROL REGISTER 2 - - - R/W R/W R/W R/W R/W 7 6 5 4 3 2 1 0 - - - EN7 EN6 Initial value when MCU Reset PWMCR2 <00E5H> T2048 POL2 POL1 [ ---0 0000 ] R37/ PWM6 Selection 0 : R37 1 : PWM6 R25/ T2048 Selection 0 : R25 1 :T2048 (Output rectangular(T=2048ys)) R36/ PWM7 Selection 0 : R36 1 : PWM7 7-bit PWM Output Polarity 0 : Positive Polarity 1 : Negative Polarity 14-bit PWM Output Polarity 0 : Positive Polarity 1 : Negative Polarity SERIAL I/O MODE REGISTER - R/W R/W R/W R/W R/W R/W R 7 6 5 4 3 2 1 0 - IOSW SM1 SM0 Initial value when MCU Reset SIOM <00D8H> SCK1 SCK0 SIOST SIOSF [ -000 0001 ] erial transmission status FLAG 0 : In transmitting 1 : End of transmission Serial Input Selection 0 : Input via Sin 1 : Input via Sout Serial Operation Mode 01 : Receive Mode (Sclk, Sout) 10 : Send Mode (Sclk, Sin) etc. : R33,R34,R35 Selection Serial Transmission Start 0 : Invalid 1 : Transmission Start(Reset after cycle ) Serial Transmission ClockSelection 00 : PS3 ( 1 uS ) 01 : PS4 ( 2 uS ) 10 : PS5 ( 4 uS ) 11 : External Clock Port Selection SM1 SM0 Function Selection R33/ Sout R34/ Sclk R35/ Sin/ Cin3 * 0 0 1 0 1 0 Send Mode Receive Mode R33 Sout R33 R34 Sclk Sclk R35 R35 Sin 1 1 - R33 R34 R35 R35 port will not operate, when Cin3 is operating as A/D input port. 3-8 GMS 84512 / 84524 3.1.5 R4 PORT 6-Bit output port. Selection Mode Pin Name R4 PORT l Port Selection Function Selection Type 0 R40/ PWM5 R40 ( O ) PWM5 ( O ) OB 1 R41/ PWM4 R41 ( O ) PWM4 ( O ) OB 2 R42/ PWM3 R42 ( O ) PWM3 ( O ) OB 3 R43/ PWM2 R43 ( O ) PWM2 ( O ) OB 4 R44/ PWM1 R44 ( O ) PWM1 ( O ) OB 5 R45/ PWM0 R45 ( O ) PWM0 ( O ) OB Register Structure and Description Register Name R4 Port Data Register PWM Control Register Symbol R/W Address Initial Value R4 R/W 00C8H Not initialized PWMCR1 R/W 00E4H 0000 0000 R4 PORT DATA REGISTER - - R/W R/W R/W R/W R/W R/W 7 6 5 4 3 2 1 0 - - R45 R44 R43 R42 R41 R40 Initial value when MCU Reset R4 <00C8H> [ Not initialized ] Port R4 output data Not used PWM CONTROL REGISTER 1 R/W R/W R/W R/W R/W R/W R/W R/W 7 6 5 4 3 2 1 0 EN5 EN4 EN3 EN2 EN1 EN0 EN8 CNT Initial value when MCU Reset PWMCR1 <00E4H> R40/ PWM5 Selection 0 : R40 1 : PWM5 14-bit / 8-bit PWM Count Start/Stop 0 : Count Start 1 : Count Stop R41/ PWM4 Selection 0 : R41 1 : PWM4 R42/ PWM3 Selection 0 : R42 R43/ PWM2 Selection 1 : PWM3 0 : R43 1 : PWM2 [ 0000 0000 ] R32/ PWM8 Selection 0 : R32 1 : PWM8 R44/ PWM1 Selection 0 : R44 1 : PWM1 R45/ PWM0 Selection 0 : R45 1 : PWM0 3- 9 GMS 84512 / 84524 3.1.6 R5 PORT 4-Bit output only port. Selection Mode Pin Name R5 PORT l Port Selection 2nd Function Type 0 R50/ R R50 ( O ) R(O) OA 1 R51/ G R51 ( O ) G(O) OA 2 R52/ B R52 ( O ) B(O) OA 3 R53/ Y R53 ( O ) Y(O) OA Register Structure and Description Register Name Sumbol R/W Address Initial Value R5 R/W 00C9H Not initialized OSDCON1 W 00F9H 0000 0000 R5 Port Data Register OSD Output/ BACKGROUND Control Register R5 PORT DATA REGISTER - - - - R/W R/W R/W R/W 7 6 5 4 3 2 1 0 - - - - R53 R52 R51 R50 Initial value when MCU Reset R5 <00C9H> Not used [ Not initialized ] Port R5 Output Data OSD OUTPUT & BACKGROUND CONTROL W W W W W W W W 7 6 5 4 3 2 1 0 OY OB OG OR OSDON BB BG BR Initial value when MCR Reset OSDCON1 <00F9H> R53/ Y Selection 0 : R53 1:Y R52/ B Selection 0 : R52 1:B R51/ G Selection 0 : R51 1:G 3 - 10 [ 0000 0000 ] Background and Edge Color Selecton OSD Output Control 0 : Disable 1 : Enable R50/ R Selection 0 : R50 1:R GMS 84512 / 84524 3.2 CLOCK GENERATION CIRCUIT The clock generation circuit of GMS84512/84524 is consist of oscillation circuit for CPU clock, prescaler for peripheral clock and Basic Interval Timer Clock. Basic Interval Timer for reference time, and water Dog Timer for detecting S/W overrun. OSC Clock Pulse Generator Internal System Clock Circuit PRESCALER (11) ENPCK 11 PERIPHERAL CIRCUIT IFBIT 8 0 MUX 7 Basic Interval Timer(8) 0 5 Watch Dog Timer(6) WDTCL 6 BTCL COMPARATOR WDTON 6 0 CKCTLR 0 1 2 3 4 5 WDTR 5 6 IFWDT 6 to RESET CIRCUIT WDT CL 7 8 Internal DATA BUS FIG.3.2.1 Clock Generation Circuit Block Diagram 3 - 11 GMS 84512 / 84524 3.2.1 Oscillation Circuit The clock signal incoming from crystal oscillator or ceramic resonator via Xin and Xout, or from external clock via Xin is supplied to Clock Pulse Generator and Prescaler Internal System Clock for CPU is made by Clock Pulse Generator, and several peripheral clock devided by prescaler Clock Generation circuit of Crystal Oscillator or Ceramic Resonator is shown in Fig.3.2.2 ¨ çClock Generation Circuit by Crystal Oscillator or Ceramic Resonator Cout Xout Xin GND Cin ¨ èClock generator circuit by external clock Xout Open Xin External Clock FIG. 3.2.2. Clock Generation Circuit ¡ W Ú hen STOP Mode, Oscillation Stops, Xin pin is High-Impedance, and Xout pin is going to High level state. 3 - 12 is GMS 84512 / 84524 3.2.2 PRESCALER Prescaler is consisted of 11-bit binary counter, and input clock is supplied by oscillation circuit. Frequency divided output from each bit of prescaler is used as peripheral clock. PS2 fex PS3 PS4 PS5 PS6 PS7 PS8 PS9 PS10 PS11 ENPCK B.I.T. 8 PS21 PS2 PS3 PS4 PS5 PS6 PS7 PS8 PS9 PS10 PS11 Peripheral 11 FIG. 3.2.3 Configuration of Prescaler TABLE 3.2.1 Frequency-Divided Outputs of Prescaler fEX ( §Ö) 4 6 PS1 PS2 PS3 Interval 4 §Ö 2 §Ö Period 250nS 500 n S Interval 6§Ö Period 3§Ö PS4 PS5 PS6 PS7 1§Ö 500 § Õ 250 § Õ 125 § Õ 62.5 § Õ 31.25 § Õ 15.63 § Õ 1uS 2uS 1.5§Ö 750 §Õ 166.7 n S 333.3 n S 666.7 n S 1.3 u S 4uS 375 § Õ 2.7 u S 8uS 16 u S PS8 32 u S PS9 64 u S PS10 PS11 7.18 § Õ 3.91 § Õ 128 u S 256 u S 187.5 § Õ 93.75 § Õ 46.88 § Õ 23.44 § Õ 11.72 § Õ 5.86 § 5.3 u S 10.7 u S 21.3 u S 42.7 u S 85.3 u S 170.7 u S CLOCK CONTROL REGISTER l CKCTLR W W W W W W W W 7 6 5 4 3 2 1 0 - - WDTON ENPCK BTS1 BTS0 BTCL BTS2 Initial value when MCU Reset CKCTLR : [ --01 0111 ] <00CEH> B.I.T. count value (When read) WDT function control (When writing) 0 : 6bit TIMER 1 : WATCH-DOG TIMER Peripheral Clock Enable ( When writing ) 0 : Peripheral Clock Stop 1 : Peripheral Clock Supply B.I.T input clock selection (When writing) 000 : PS4 ( 001 : PS5 ( 010 : PS6 ( 011 : PS7 ( 2 u S ) 100 : PS8 ( 32u S ) 4 u S ) 101 : PS9 ( 64u S ) 8 u S ) 110 : PS10 ( 128uS ) 16 u S ) 111 : PS11 ( 256u S ) B.I.T. CLEAR ( When writing ) 0 : B.I.T. FREE-RUN 1 : B.I.T. CLEAR ( Auto reset after 1-cycle ) 3 - 13 GMS 84512 / 84524 Peripheral Hardware Clock control Function Peripheral Clock supplied from prescaler can be stopped by ENPCK. Peripheral hardware clock control bit of CKCTLR Register.(However, PS11 cannot be stopped by ENPCK). 3.2.3 Basic Interval Timer There is 8-bit binary counter is Basic Interval Timer. It operates as following function. - Reference Time interval interrupt request as timer. - B.I.T. can be read ( Note; The writing at same address overwrites the CKCTLR.) - Clock supply of Watch Dog Timer. Data BUS 6 CKCTLR - - WDTON ENPCK BTCL BTS2 BTS1 BTS0 Same address when read, it can be read as counter value. When write, it can be write as control register. PS4 PS5 PS6 PS7 PS8 PS9 PS10 PS11 B.I.T. MUX bit7 bit6 bit5 bit3 bit4 bit2 bit1 bit0 IFBIT 8 Data BUS FIG. 3.2.4 3 - 14 Configuration of Basic Interval Timer GMS 84512 / 84524 Control of Basic Interval Timer Basic Interval Timer is Free Running Timer, but it can be cleared by setting BTCL ( Bit 3 of clock control register). Initial state (after Reset) of BTCL is “0”, and if it is set to “1” it is auto-cleared after 1 machine cycle. CLOCK CONTROL REGISTER CKCTLR W W W W W W W W 7 6 5 4 3 2 1 0 - - WDTON ENPCK BTS1 BTS0 BTCL BTS2 Initial value when MCU Reset CKCTLR : [ --01 0111 ] <00CEH> B.I.T. input clock selection see Table 3.3.2 B.I.T. CLEAR ( When writing ) 0 : B.I.T. Free-run 1 : B.I.T. Clear ( auto cleared after 1 machine cycle ) l Input clock selection of Basic Interval Timer and Reference Time interrupt interval Input clock of Basic Interval Timer is selected by BTS2~BTS0(Bit2~0 of clock control register)among the prescaler outputs. Reference time interval interrupt is generated by BIT overflow. CLOCK CONTROL REGISTER CKCTLR W W W W W W W W 7 6 5 4 3 2 1 0 - - WDTON ENPCK BTS1 BTS0 BTCL BTS2 Initial value when MCU Reset CKCTLR : [ --01 0111 ] <00CEH> B.I.T Input Clock Selection ( When writing ) B.I.T. count value (When read) TABLE 3.2.2 Input clock selection of Basic Interval Timer and reference time interrupt interval (@4MHz) BTS2 BTS1 BTS0 B.I.T. Input Clock Period Reference Time Interrupt Period 0 0 0 PS4 (2uS) 512uS 0 0 1 PS5 (4uS) 1,024uS 0 1 0 PS6 (8uS) 2,048uS 0 1 1 PS7 ( 16 u S ) 4,096uS 1 0 0 PS8 ( 32 u S ) 8,192uS 1 0 1 PS9 ( 64 u S ) 16,384uS 1 1 0 PS10 ( 128 u S ) 32,768uS 1 1 1 PS11 ( 256 u S ) 65,536uS 3 - 15 GMS 84512 / 84524 l Reading of Basic Interval Timer Basic Interval Timer Register can be read and interval up to 65ms can be measured (Note : The writing at same address overwrites the CKCTLR.) BASIC INTERVAL TIMER REGISTER BITR R R R R R R R R 7 6 5 4 3 2 1 0 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 Initial value when MCU Reset Not initialized <00CEH> B.I.T.count value ( When read) 3.2.4 Watch Dog Timer Watch Dog Timer is consist of 6-bit Binary Counter, 6-Bit Comparator and Watch Dog Timer Register(WDTR) IFWDT is generated when counter value equals to WDTR, it can be used as S/W interrupt or MCU reset (Watch Dog Function) signal. 6-bit Counter 0 IFBIT 5 WDT0 WDT1 WDT2 WDT3 WDT4 WDT5 WDTON CLR to Reset Circuit 6-bit COMPARATOR IFWDT 0 WDTR 6 WDTR WDTR WDTR WDTR WDTR WDTR 0 1 2 3 4 5 WDT CL 7 Data BUS FIG. 3.2.4 Configuration Watch Dog Timer 3 - 16 GMS 84512 / 84524 l Control of WDT WDTcan be used as 6-bit Timer or Watch Dog Timer according to WDTON ( Bit 5 of CKCTLR). WDT is cleared by setting WDTCL (Bit 6 WDTR) to “1”. < Notice > 1: After WDTON=1, maximum error of Timer is are one of period of IFBIT. 2: Because 6-bit counter begin to count after MCU Reset the Watch Dog Timer should be enabled after clearing it. CLOCK CONTROL REGISTER CKCTLR W W W W W W W W 7 6 5 4 3 2 1 0 - - WDTON ENPCK BTS1 BTS0 BTCL BTS2 Initial value when MCU Reset CKCTLR : [ --01 0111 ] <00CEH> WDT control (When writing) 0 : 6-bit Timer 1 : Watch-Dog Timer WATCH-DOG TIMER REGISTER - W W W W W W W 7 6 5 4 3 2 1 0 WDTR <00CFH> - WDTCL WDTR 5 WDTR WDTR WDTR WDTR WDTR 4 3 2 1 0 WDT CLEAR 0 : WDT Free-Run 1 : WDT CLEAR (Auto reset after 1 cycle ) l Initial value when MCU Reset [ -011 1111 ] Interval of WDT IFWDT period= ( WDTR value )X( IFBIT interval ) Interval of WDT Interrupt Interval of WDT Interrupt is decided by Basic Interval Timer Interrupt an WDTR That is, Interval of = ( WDTR value ) X ( IFBIT interval ). 3 - 17 GMS 84512 / 84524 l Selection of WDT clock and maximum interval of WDT interrupt Input clock of WDT is IFBIT, so WDT interval is decided by BTS2~BTS1. Interval of WDT interrupt become maximum value. < Notice > Do not use WDTR=0 for MCU not to be Reset state always. TABLE 3.2.2 3 - 18 Selection of WDT clock and maximum interval of WDT interrupt (@ 4MHz) BTS2 BTS1 BTS0 B.I.T. Input Clock WDT Input Clock IFWDT max. interval 0 0 0 PS4 ( 2 u S ) 512 uS 32,256 uS 0 0 1 PS5 ( 4 u S ) 1,024 uS 64,512 uS 0 1 0 PS6 ( 8 u S ) 2,048 uS 129,024 uS 0 1 1 PS7 ( 16 u S ) 4,096 uS 258,048 uS 1 0 0 PS8 ( 32 u S ) 8,192 uS 516,096 uS 1 0 1 PS9 ( 64 u S ) 16,384 uS 1,032,192 uS 1 1 0 PS10 ( 128 u S ) 32,768 uS 2,064,384 uS 1 1 1 PS11 ( 256 u S ) 65,536 uS 4,128,768 uS GMS 84512 / 84524 3.3 TIMER Timer of GMS84512/84524 is 8-bit binary counter is consisted of Timer0(T0). Timer1(T1), Timer2(T2), Timer(T3), Timer Data Register(TDR0~TDR3). Timer Mode Register(TM0, TM2) and control circuit. T0, T1 is each 8-bit interval Timer and can be used as a 16-bit intrval Timer. T2, T3 is each 8-bit interval timer/event counter and can be used as a 16-bit interval timer/event counter 3.3.1 OPERATION MODE OF TIMER l Operating mode of T0, T1 T0 T1 8-bit Interval Timer l l l l 8-bit Interval Timer 16-bit Interval Timer Operating mode ofT2, T3 T2 T3 -. 8-bit Interval Timer -. 8-bit Interval Timer -. 8-bit Event Counter -. 8-bit Event Counter -. 16-bit Interval Timer -. 16-bit Event Counter When T2, T3 are used as event counter the relevant Port Mode Register Value should be assigned to select EC2 or EC3. When T2, T3 are used as event counter, TDR value should be initialized to “FFH” because Timer count value is cleared if it equals to TDR value Note) At the Reset Routine, TDR0 ~ TDR3 are should be initialized by software. (Except 00H) PORT FUNCTION SELECTION REGISTER - - - W W W W W 7 6 5 4 3 2 1 0 - - - FUNC <00CAH> Initial value (When MCU Reset EC3S EC2S INT3S INT2S INT1S R27 / EC3 Selection R26 / EC2 Selection 0 : R27 ( I/O ) 1 : EC3 ( Input ) 0 : R26 ( I/O ) 1 : EC2 ( Input ) [ ---0 0000 ] 3 - 19 GMS 84512 / 84524 Data BUS 7 8 TDR0 TM0 - 8 8 8 TDR1 Data Reg. 0 Data Reg. 1 8 8 Comparator 0 Comparator 1 8 8 6 5 4 3 2 1 0 T0CN 2 ck PS2 PS4 PS6 PS8 ck T0 T1 MUX Clear Clear T0ST 2 16bit Mode 16bit Mode PS2 PS4 PS6 IFT1 MUX 1 MUX 0 T1ST FIG. 3.3.1 1 MUX 0 IFT0 Configuration TIMER0,TIMER1 Data BUS 7 8 TDR2 TM2 - 8 8 8 TDR3 Data Reg. 2 Data Reg. 3 8 8 Comparator 2 Comparator 3 8 8 6 5 4 3 2 1 0 T2CN 2 EC2 PS4 PS6 PS8 ck ck T2 T3 MUX Clear Clear T2ST 2 EC3 PS4 PS6 16bit Mode 16bit Mode T3ST FIG. 3.3.2 3 - 20 IFT3 MUX 1 MUX 0 Configuration of TIMER2,TIMER3 1 MUX 0 IFT2 GMS 84512 / 84524 TIMER MODE REGISTER 0 - R/W R/W R/W R/W R/W R/W R/W 7 6 5 4 3 2 1 0 Initial Value when MCU Reset TM0 - <00D0H> T1ST T1SL1 T1SL0 T0ST T0CN T0SL1 T0SL0 T1 Start/Stop control 0 : Cout Stop 1 : Counting start after clearing T1 * Don't care in 16bit Mode [ -000 0000 ] T0 Input Clock Selection 00 : PS2 ( 500 u S ) 01 : PS4 ( 2uS) 10 : PS6 ( 8uS) 11 : PS8 ( 32 u S ) T1 Input Clock Selection 00 : Connection to T0 (16bit Mode ) 01 : PS2 ( 500 u S ) 10 : PS4 ( 2uS) 11 : PS6 ( 8uS) T0 Start/Stop control 0 : COUNT Stop 1 : COUNT Start T0 Start/Stop control 0 : Count Stop 1 : Counting start after clearing T0 TIMER MODE REGISTER 2 - R/W R/W R/W R/W R/W R/W R/W 7 6 5 4 3 2 1 0 Initial value when MCU Reset TM2 - <00D1H> T3ST T3SL1 T3SL0 T2ST T2CN T2SL1 T2SL0 T2 Input Clock Selection 00 : Input external clock source(EC2) 01 : PS2 ( 500 u S ) T3 Start/Stop control 0 : Count Stop 1 : Counting start after clearing T3 * Don't care in 16bit Mode 10 : PS4 ( 11 : PS6 ( T3 Input Clock Selection 00 : Connection to T2 ( 16bit Mode ) 01 : Input external clock source(EC3) 10 : PS2 ( 500 u S ) 11 : PS4 ( [ -000 0000 ] 2uS) 8uS ) T2 Start/Stop Control 0 : Count Stop 1 : Count Start 2uS) T2 Start/Stop Control 0 : Count Stop 1 : Counting start after clearing T2 TIMER0 ~ TIMER3 DATA REGISTER TDR0 R/W R/W R/W R/W R/W R/W R/W R/W <00D2H> 7 6 5 4 3 2 1 0 TDR1 <00D3H> TDR0 TDR0 TDR0 TDR0 TDR0 TDR0 TDR0 TDR0 7 6 5 4 3 2 1 0 Initial value when MCU Reset [ Not Initialized ] TDR2 <00D4H> TDR3 <00D5H> ( READ ) T0 Count Value Read T1 Count Value Read T2 Count Value Read T3 Count Value Read ( WRITE) Modulo Data Write of T0 Modulo Data Write of T1 Modulo Data Write of T2 Modulo Data write T3 3 - 21 GMS 84512 / 84524 TABLE 3.3.1 Timer resolutin and maximum count at fIN=4MHz Timer 8-bit TIMER Mode Resolution( ck ) T0 T2 T1 T3 3.3.2 16-bit TIMER Mode max.count Resolution( ck ) max. count PS2 ( 0.5 § Á ) 128 § Á PS2 ( 0.5 § Á ) PS4 ( 2 § Á ) 512 § Á PS4 ( 2 § Á ) 131,072 §Á PS6 ( 8 § Á ) 2,048 § Á PS6 ( 8 § Á ) 524,288 §Á PS8 ( 32 § Á ) 8,192 § Á PS8 ( 32 § Á ) 2,097,152 §Á PS2 ( 0.5 § Á ) 128 § Á PS2 ( 0.5 § Á ) 32,768 §Á PS4 ( 2 § Á ) 512 § Á PS4 ( 2 § Á ) 131,072 §Á PS6 ( 8 § Á ) 2,048 § Á PS6 ( 8 § Á ) 524,288 §Á PS2 ( 0.5 § Á ) 128 § Á ( Note ) PS4 ( 2 § Á ) 512 §Á Operation As Upper 8-Bit of T0 PS6 ( 8 § Á ) 2,048 §Á PS2 ( 0.5 § Á ) 128 §Á ( Note ) PS4 ( 2 § Á ) 512 §Á Operation As Upper 8-Bit of T2 32,768 §Á Operation of TIMER0, TIMER1 T0 ( T1 ) is consisted of 8-bit Binary Up-Counter. If T0 or T1 counter value become equal to Tdr0(or TDR1) value, it is cleared to 00H, and Interrupt request (IFT0 or IFT1) is generated. TDR0 VALUE MATCH MATCH MATCH Clear Clear Clear T0 VALUE 00H Interrupt IFT0 Interval Period FIG 3.3.3 Operation of TIMER0 ,TIMER1 3 - 22 Interrupt Interrupt GMS 84512 / 84524 l Any of the PS2, PS4, PS6 or PS8 can be selected as the clock source of T0 by bit1(T0SLI) and bit0(T0SL0) of TM0. Andy of the PS2, PS4, PS6 or overflow of T0 can be selected as the clock source of T1 by bit5(T1SL1) and bit4(T1SL0) of TM0. l The operation of T0, T1 is controlled by bit3(T0ST), bit2(T0CN) and bit6(T1ST) of TM0. T0CN controls count stop/start without clearing counter. T0ST and T1ST control count stop/start. In order to enable timer to count-up, T0CN, T0ST and T1St should become “1”. After clearing T0, T1 in order to count-up. T0st or T1ST should become “0” for a moment and return to “1”. TDR0 VALUE MATCH MATCH T0 VALUE 00H Clear Clear Clear Interrupt Interrupt IFT0 “0” “1” Clear & Start T0ST “0” “1” Start T0CN COUNTER Count Stop Count Stop Count FIG 3.3.4 START/ STOP Control of Timer0 l The 16-bit interval timer is selected by assigning bit5(T1SL1) and bit4(T1SL0) to “0”.) At 16-bit timer mode, IFT0 interrupt only is valid. It is prefered to write to the TDR in non counting timer in order to protect undesirable interrupt. 3 - 23 GMS 84512 / 84524 3.3.2 Operation of TIMER2, TIMER3 l T2 ( T3 ) is consisted of 8-bit Binary Up-Counter. If T2(T3) counter value become equal to TDR2(TDR3) value, it is cleared to 00H and interrupt request (IFT2 or IFT3) is generated. TDR2 VALUE MATCH MATCH MATCH Clear Clear Clear T2 VALUE 00H Interrupt Interrupt Interrupt IFT2 Interval Period FIG 3.3.5 Operation of TIMER2 ( or TIMER3) l Any of the PS2, PS4, PS6 or external event input can be selected as the clock source of T2 by bit1(T2SL1) and bit0(T2SL0) of TM0. Any of the PS2, PS4 external event input or overflow of T2 can be selected as the clock source of T1 by bit5(T3SL1) and bit4(T3SL0) of TM0. If input clock is selected as external event input (EC2 or EC3), T2 and T3 operates as 8-bit event counter. l The operation of T2, T2 is controlled by bit3(T2ST), bit2(T2CN) and bit6(T3ST) of TM2. controls count stop/start without clearing counter. T2ST and T3ST control count stop/start. order to enable timer to count-up T2CN, T2ST and T3ST should become “1”, After clearing T0,T1 in order to count-up. T2ST or T3ST should become “0” for a moment and return to “1” 3 - 24 GMS 84512 / 84524 MATCH TDR2 VALUE MATCH T2 VALUE 00H Clear Clear Clear Interrupt Interrupt IFT2 “0” “1” Clear & Start T2ST “0” “1” Start T2CN COUNTER Count Stop Count Stop Count FIG 3.3.6 START/ STOP Control of Timer2 l The 16-bit interval timer is selected by assigning bit5(T3SL1) and bit4(T3SL0) to “0”. 16-bit timer mode, iIFT2 interrupt only is valid. At It is prefered to write to the TDR in non- counting timer, in order to protect undesirable interrupt. If the input clock is selected among PS2, PS4 and PS6, T2 and T3 operate as 16-bit interval timer, while if EC2 operate as 16-bit event/counter. < Notice > 1. On counting the reading value of TDR is counted value 2. 16-bit Mode, when data are read I the middle of Timer operation, the prior upper 8 bit data are read. Next the lower 8-bit data are read, and then the upper 8 bit data are read once again. If the earlier read upper 8-bit data are matched with the later read upper 8 bit data, 16-bit data are read correctly. If not, caution should be taken in the selection of upper 8-bit data. ( Example ) 1 ) Upper 8 bit Read 0A 0A 2 ) Lower 8 bit Read FF 01 3 ) Upper 8 bit Read 0B 0B ¡ é ¡ é 0AFF 0B01 3 - 25 GMS 84512 / 84524 3.4 A/D COMPARATOR A/D comparator has an 5-bit resolution, and input is possible up to 4 channel. A/D comparator is consisted of analog input multiplexer, 5-bit D/A conversion circuit, sample & holder and control circuit FIG.3.4.1 is a block diagram of A/D comparator Data BUS 2 5 CIS 6 CMR ADCM ADCM ADCM ADCM ADCM 0 1 2 3 4 1 0 - 7 COR ADEN 5 RESISTER LADDER 5-bit D/A C. ADEN 2 Vref Cin0 ANALOG Cin1 INPUT Cin2 + MULTIPLEXER OUTPUT LATCH Cin3 COMPARATOR FIG. 3.4.1 Block Diagram of A/D Comparator 3.4.1 A/D COMPARATOR Following produce is used. - Write CIS register to select analog input channel. - After writing CMR(ADCM0~4) to select reference voltage, set ADEN(bit7 of CMR) to “1” to start A/D comparision.. < Notice > CMRcan’t be used with Bit Manipulation instruction and setting the reference voltage and starting A/D comparision can be used at same time.. - A/D Comparision processing needs 16machine cycle(8us) - The result of comparision is stored in COR(bit6 of CMR). That is, if <input voltage > reference voltage>, COR=1 if <input voltage < reference voltage>, COR=0 3 - 26 GMS 84512 / 84524 A/D COMP. INPUT CHANNEL SELECTION REGISTER - - - - - - W W 7 6 5 4 3 2 1 0 - - - - - - CIS1 CIS0 Initial value when MCU Reset CIS <00D7H> [ ---- --00 ] Analog input channel selection 00 : CIN0 01 : CIN1 10 : CIN2 11 : CIN3 Port Selection CIS1 CIS0 0 0 1 1 0 1 0 1 Function Selection R15/ Cin1 Channel 0 (Cin0) R15 Channel 1 (Cin1) Cin1 Channel 2 (Cin2) R15 Channel 3 (Cin3) R15 R16/ Cin2 R16 R16 Cin2 R16 R17/ Cin0/ INT3 R35/ Sin/ Cin3 Cin0/ INT3 R17/ Cin0 R17/ Cin0 R17/ Cin0 R35/ Sin R35/ Sin R35/ Sin Cin3 A/D COMPARATOR MODE REGISTER W R - W W W W W 7 6 5 4 3 2 1 0 CMR <00D6H> A/D Comparision Control 0 : A/D Comparision Stop 1 ; A/D Comparision Start l ADEN COR - ADCM ADCM ADCM ADCM ADCM 4 3 2 1 0 A/D Comparison Result 0 : Input Voltage <Reference Voltage 1 ; Input Voltage >Reference Voltage Initial value when MCU Reset [ 00-0 0000 ] Reference Voltage Selection 00000 : Vdd/ 64 10000 : 33Vdd/ 64 00001 : 3Vdd/ 64 10001 : 35Vdd/ 64 00010 : 5Vdd/ 64 10010 : 37Vdd/ 64 | | 01111 : 31Vdd/ 64 11111 : 63Vdd/ 64 The Calculation of Reference Voltage Reference Voltage ( Vref ) = { 2 X ( Value of ADCM) + 1 } X Vdd / 64 3 - 27 GMS 84512 / 84524 3.5 Serial I/O The serial I/O is 8-bit clock sychronous type and is consisted of serial I/O register, serial I/O mode register, clock selection circuit octal counter and control circuit. The Sout pin is degined to Input and Output. So serial I/O interface can be operated with minimum two pin. Data BUS 6 7 SIOM 6 - 0 IOSW SM1 SM0 SCK1 SCK0 SIOST SOSF SM1 SM0 2 PS3 PS4 Control MUX Octal Counter Circuit PS5 IFSIO Exclk Sclk Sout SIOR 1 7 6 5 4 3 2 1 0 MUX Sin 0 8 Data BUS FIG. 3.5.1 3.5.1 Block Diagram of Serial I/O Serial I/O Data Register Serial I/O Data Register SIORis a 8-bit Shift Register. First LSB is send or is received. R/W R/W R/W R/W R/W R/W R/W R/W 7 6 5 4 3 2 1 0 D7 D6 D5 D4 D3 D2 D1 D0 SIOR <00D9H> At transmittion Sending Data at Sending Receiving Data at Receiving 3 - 28 Initial value when MCU Reset [ Not initialized ] GMS 84512 / 84524 3.5.2 Serial I/O Mode Register This register controls serial function. According to SCK1, SCK0 internal clock or external clock can be used. SERIAL I/O MODE REGISTER - R/W R/W R/W R/W R/W R/W R 7 6 5 4 3 2 1 0 - IOSW SM1 SM0 Initial value when MCU Reset SIOM <00D6H> SCK1 SCK0 SIOST SIOSF Serial Transmission status FLAG 0 : Serial during transmission 1 : Serial finished Serial Input Selection 0 : Via Sin 1 : Via Sout Serial Transmission Start 0 : Invalid 1 : Start(After one SCK, becomes”0”) Serial Operation Mode 01 : Sending Mode (Sclk, Sout) 10 : Receiving Mode (Sclk, Sin) Others : Selection of R33,R34,R35 l [ -000 0001 ] Serial Transmission Clock Selection 00 : PS3 ( 1uS ) 01 : PS4 ( 2uS ) 10 : PS5 ( 4uS ) 11 : External Clock Port Selection According to Serial I/O Mode Port Selection SM1 SM0 Function Selection R33/ Sout R34/ Sclk R35/ Sin/ Cin3 * 0 0 0 1 Sending Mode R33 Sout R34 Sclk R35 R35 1 1 0 1 Receiving Mode - R33 R33 Sclk R34 Sin R35 * If Cin3 is used as A/D comparator input channel, R35 port do not operate as output.. l Selection of Serial input pin with the IOSW When receiving mode, serial input pin is selected by IOSW. selected. That, if IOSW=0, R35/Sin is If IOSW=1, R33/Sout 3 - 29 GMS 84512 / 84524 3.5.3 Data Transmission/Receving Timing Serial transmission is started by setting SIOST(bit1 SIOM) to :”1”. SIOST is cleared automatically to “0”. After one cycle of SCK, serial output data from 8-bit shift register is output at folloing edge of Sclk. and input data is latched at rising edge of Sclek. When transmission Clock is counted 8times, serial I/O counter is cleared as “0”. Transmission clock is halted in “H” state and serial I/O interrupt (IFSIO) occursg. Input Clock Sclk SIOST Output Sout D0 D1 D2 D3 D4 D5 D6 D7 D2 D3 D4 D5 D6 D7 Latch Sin D0 D1 IFSIO FIG. 3.5.1 3.5.4 Timing Diagram of Serial I/O Data Transmission/Receiving Method - Select transmission/receiving mode <Notice> When external clock is used, the frequency should be less than 1MH and recommanded duty is 50%. - When sending Data to be send is written at SIOR. - Set SIOST to “1” to start serial transmission. <Notice > If both transmission mode selection and starting transmission is performed simultaneouslyit makes error. - IFSIO is generated at completion and SIOSF is set to “1”. In SIO interrupt service routine correct transmission should be tested. - 3 - 30 When receiving, receiving data is acquired by reading the SIOR. GMS 84512 / 84524 3.5.5 The Method to Test Correct Transmission with S/W Serial I/O Interrupt SERVICE ROUTINE SIOSF ? 0 1 Abnormal Operation SE = 0 WRITE SIOM SR ? 0 Normal Note) 1 OVERRUN ERROR Operation SE: Interrupt Enable Regist Low IENL ( Bit3 ) SR : Interrupt Request Flag Regist Low IRQL ( Bit3 ) FIG. 3.5.4 Serial Method to Teset Transmission. 3 - 31 GMS 84512 / 84524 3.6 Pulse Width Modulation ( PWM ) The GMS84512/84524 is equipped with one 14-bit PWM(PWM8) and eight 7-bit PWM(PWM0~PWM7). The 14-bit resolution gives PWM8 the minium resolution bit width of 500ns(PS2=500ns, if Xin=4MHz) and repeat period of 8,192uS. Each PWM0~PWM7 has a 7-bit resolution with min. resolution bit width of 8uS ( PS6 ) and repeat period of 1,024uS. l PWM Specification Table ( @ Xin =4MHz ) Specification 14-bit PWM Resolution 14 bits Input Clock 0.5uS 1 Frame Cycle 7-bit PWM 7 bits 8uS 8,192uS 1,024uS Data BUS 5 7 8 PWMCR2 PWMR7 ¡ -PWMR0 - - 6 5 4 3 2 1 0 - PWMCR1 - 4 3 2 1 0 7 6 5 4 3 2 1 0 CNTB PWMR7 PWM7 EN7 EN6 PWMR6 PWMR5 PWM6 EN5 PWM5 EN4 PWMR4 PWMR3 PWM4 EN3 PWM3 EN2 PWMR2 PWM2 PWM1 EN1 PWMR1 PWMR0 EN0 7 7-bit Comparator POL2 Match PWM0 7 CNTB T2048E 7-bit Counter PS6 T F/F T2048 IF 1mS FIG. 3.6.1 3 - 32 Block Diagram of 7-bit PWM & T2048 GMS 84512 / 84524 Data BUS 8 6 8 PWM8H PWM8L 7 6 5 4 3 2 1 0 - 5 8 PWMCR2 - 5 4 3 2 1 0 - - PWMCR1 - 4 3 2 1 0 7 6 5 4 3 2 1 0 Wpwm8L 14 CNTB 14-bit Data Register 14 EN8 POL1 14-bit Comparator CNTB PWM8 14 14-bit Counter PS2 FIG. 3.6.2 3.6.1 Match Block Diagram of 14-bit PWM PWM8 (14-bit PWM ) When the PWM8 is used for output, first set the higher 8-bit of the PWM8H register, then the lower 6-bit of the PWM6 register. The 14-bit data of PWM8 can be compare with the 14-bit comparator after lower 6-bit data of PWM8 is transferred. Data setting for PWM8(14-bit PWM) l The PWM output pulse period is consist with 64(=26) high level area which is consist with 256(=28)lowlevel area. First, the basic pulse is made by the data of PWM8H, then the position of pulse as long as low level width(0.5uS) among 64 short pulse is determined by contents of PWM8L. TABLE 3.6.1 BIT Sub-Frame(short pulse) position as long as low level area Pulse Bit0 = “1” S32, 1 Bit1 = “1” S16, S48 2 Bit2 = “1” S8 , S24, S40, S56 4 Bit3 = “1” S4 , S12, S20, S28, S36, S44, S52, S60 8 Bit4 = “1” S2 , S6 , S10, S14, S18, S22, S26, S30, S34, S38, S42, S46, S50, S54, S58, S62 16 Bit5 = “1” S1 , S3 , S5 , S7, S9, S11, S13, S15, S17, S19, S21, S23, S25, S27, S29, S31, S33, S35, S37, S39, S41, S43, S45, S47, S49, S51, S53, S55, S57, S59, S61, S63 32 3 - 33 GMS 84512 / 84524 Initial value (at RESET) PWM8H W <00E2H> Initial value (at RESET) PWM8L [ Undefined ] W <00E3H> 7 6 5 4 3 2 1 0 D7 D6 D5 D4 D3 D2 D1 D0 [ Undefined ] 7 6 5 4 3 2 1 0 - - D5 D4 D3 D2 D1 D0 Added pulse Basic pulse width 13 12 11 10 9 8 7 6 5 4 3 2 1 0 1 0 0 0 0 0 1 0 0 0 0 1 1 0 Basic pulse width ( PWM8H= 82H ): ( 130 ) X 0.5 = 65uS Number of Added Pulse ( PWM8L= 06H ): 6 ( S8,S16,S24,S40,S48,S56 ) Period of Basic Pulse ( 128uS ) Basic Pulse Width ( 65 uS) Added Pulse Width( 0.5uS ) : Sub-Frame with Added Pulse Pulse Width = 65.5 uS PWM Period ( 8,192 §Á) S0 S1 S2 S3 FIG.3.6.3 3 - 34 S8 S9 S16 S17 S24 S25 S40 S41 S48 S49 Example output of the 14-bit PWM ( Polarity : Positive ) S56 S57 S61 S62 S63 GMS 84512 / 84524 3.6.2 PWM0¡-PWM7 ( 7-bit PWM ¡¿ 8 CH. ) Each PWM0~PWM7 can be used for different PWM output by each 7-bit data register (PWMR0~PWM7). The PWM pulse period is 1,024§Á and the width is (PWMR+1)¡¿T/128 . (0<PWMR<127: Value of 7-bit PWM register data) PWM0~PWM7 is positive, negative for output. The start point of output is spreaded wide, so the flow of current is proper. PWM0~PWM7 is port is N-MOS open drain. ¨ç Positive Polarity ( POL2 = 0 ) ¨è Negative Polarity ( POL2 = 1 ) Pulse Period( 1,024 §Á ) Pulse Width( 1,024) ) Pulse Width Pulse Width = ( PWMR +1 )£¯128 ¡¿ 1,024 [§Á] ( PWMR +1 )£¯128 ¡¿ 100 [ % ] DUTY CYCLE = FIG. 3.6.4 3.6.3 Pulse Width Output Pulse of PWM0 ¡- PWM7 PWMR0¡-PWMR7 REGISTER PWMR0 ¡-PWMR7 are the data register to define 7-bit PWM pulse width and it has only write . They are undefined at reset state. PWMR0 ¡-PWMR7 DATA REGISTER PWMR0 PWMR1 <00DAH> <00DBH> PWMR2 PWMR3 <00DCH> <00DDH> ¦¡ W W W W W W W 7 6 5 4 3 2 1 0 ¦¡ Initial value (at RESET) PWM0 PWM0 PWM0 PWM0 PWM0 PWM0 PWM0 D6 D5 D4 D3 D2 D1 D0 [ Undefined ] PWMR4 PWMR5 <00DEH> <00DFH> PWMR6 PWMR7 <00E0H> <00E1H> Storage of each PWM data 3 - 35 GMS 84512 / 84524 3.6.4 PWM8H, PWM8L REGISTER PWM register (PWM8H, PWM8L) are the data register to define 14bit PWM pulse width and it is enable R/W. They are not fixed at reset state. PWM8H , PWM8L DATA REGISTER PWM8H <00E2H> R/W R/W R/W R/W R/W R/W R/W R/W 7 6 5 4 3 2 1 0 Initial Value (At Reset) PWM8 PWM8 PWM8 PWM8 PWM8 PWM8 PWM8 PWM8 H5 H4 H3 H2 H1 H0 H7 H6 [ Undefined ] Storage of 14-bit PWM upper 8-bit data When PWM8L is written it is loaded in upper 8-bit of 14-bit comparator, so the width of basic pulse are determined. When PWM8L is read, the contents(PWM8L) of comparator is read. PWM8L ¡ª ¡ª R/W R/W R/W R/W R/W R/W 7 6 5 4 3 2 1 0 ¡ª ¡ª <00E3H> Initial Value (At Reset) PWM8 PWM8 PWM8 PWM8 PWM8 PWM8 L5 L4 L3 L2 L1 L0 [ Undefined ] The number and position for added-pulse of 64 basic pulse are determined 3.6.5 The control of 14-bit PWM ¨ç Write upper data to PWM8H (definition of basic pulse width) ¨è Write lower 6-bit data to PWM8L ¨é When data are written PWM8L, the 14-bit data of PWM8 is written to compare register so, even if you will change the upper 8-bit of output data, you will write 6bit data to PWM8L again. But when you will change the lower 6-bit of output data, you need not write the upper 8-bit to PWM8H again.. ¨ê Output polarity is determined by POL1.( bit2 of PWM control register 2) Default is positive polarity.(POL1=0) ¨ë PWM8 port is selected by setting EN8(bit1 of PWM ontrol register1) to “1”, so the wave of PWM is to be output. ¨ì If CNTB(bit6 of PWMCR1) is "0", Counter is operating, on the contrary if it is "1" count stops. This have an effect on both of them.(14-bit PWM/7-bit PWM counter) 3 - 36 GMS 84512 / 84524 3.6.6 The Control of 7-bit PWM ¨ç Write 7-bit data to each PWM data register (PWMR0~PWMR7). ¨èDefine output polarity by POL2 (bit3 of PWMCR2(PWM control register2)) Positive polarity is determine by default. also this has effect an all 7bit PWM output ¨é If each PWM port is selected by setting EN0~EN7(bit2~bit7 of PWMCR1, bit1 and bit2 ofPWMCR2) to "1". ¨ê If CNTB(bit0 of PWMCR1) is "0", counter is operating, on the contrary if it is “1” counter stops. This has effect on all 14-bit PWM/7-bit PWM counter. PWM CONTROL REGISTER 1 R/W R/W R/W R/W R/W R/W R/W R/W 7 6 5 4 3 2 1 0 EN5 EN4 EN3 EN2 EN1 EN0 EN8 CNTB Initial Value (at RESET) PWMCR1 <00E4H> Select R40/ PWM5 0 : R40 1 : PWM5 [ 0000 0000 ] 14-bit / 8-bit PWM Count Stop/Start COUNT Start 1: COUNT Stop Select R41/ PWM4 0 : R41 1 : PWM4 Stop/StartR32/ PWM8 0 : R32 1 : PWM8 R42/ PWM3 0 : R42 Select R43/ PWM 1 : PWM3 2 0 : R43 1 : PWM2 Select R44/ PWM1 0 : R44 1 : PWM1 R45/ PWM0 0 : R45 1 : PWM0 PWM CONTROL REGISTER 2 ¦¡ ¦¡ ¦¡ R/W R/W R/W R/W R/W 7 6 5 4 3 2 1 0 ¦¡ ¦¡ ¦¡ EN7 EN6 Initial Value (at RESET) PWMCR2 <00E5H> T2048 POL2 POL1 Start R25/ T2048 0 : R25 1 :T2048 (Period 2048 §Á rectangular pulse output select) 7-bit PWM OUTPUT Polarity 0 : Positive PolarityY 1 : Negative Polarity [ ---0 0000 ] Select R37/ PWM6 0 : R37 1 : PWM6 Select R36/ PWM7 0 : R36 1 : PWM7 14-bit PWM Output Polartity 0 : Positive Polarity 1 : Negative Polarity 3 - 37 GMS 84512 / 84524 3.7. Interrupt Interval Measurement Circuit GMS84512/84524 is equipped with distinct edge of input signal for 2 channel external interrupt (INT1, INT2) and interrupt interval measurement circuit of evaluating distinct edge interval. Interrupt interval measurement circuit is equipped with interrupt input multiplexer, 8bit binary upcounter measurement clock selection circuit, interrupt interval storage circuit and interrupt interval measurement control register Data BUS 3 7 IDCR ¡ª ¡ª ¡ª PS8 PS9 ¡ª ¡ª 2 ISEL 0 IDCK IDST IDST 32§Á 1 MUX 0 64§Á ck Delay Circuit INT2 INT1 8-bit Up-Counter Clear 1 MUX 0 8 Interrupt Interval Data Register 8 IDR Data BUS FIG. 3.7.1 Configruation of interrupt interval measurement circuit 3.7.1 Operation of Interrupt Interval Measurement Circuit Interrupt interval measurement circuit stores the count value of 8-bit up counter to IDR(interrupt interval data register) by selected edge of external interrupt input. And then it may clear 8-bit up-counter, go on counting again. And the counter value of 8-bit up-counter is stored to IDR by selected edge of second external interrupt input. So, selected edge interval of external interrupt input is measured to PS8(32§Á) or PS9(64§Á). Rising/Falling edge of interrupt input signal is selected by IEDS(External Interrupt Signal Edge Selection)and width or period of input signal is measured by combination of selected edge. External interrupt input signal is selected by FUNC(port function selection register) Fig 3.7.2 and TABLE 3.7.1 show interrupt input signal edge selection and measurement interval. 3 - 38 GMS 84512 / 84524 PORT FUNCTION SELECTION REGISTER ¦¡ ¦¡ ¦¡ W W W W W 7 6 5 4 3 2 1 0 ¦¡ ¦¡ ¦¡ Initial Value (at RESET) FUNC <00CAH> EC3S EC2S INT3S INT2S INT1S [ ---0 0000 ] R30 / INT1 Selection 0 : R30 ( Input ) 1 : INT1 ( Input ) R27 / EC3 Selection 0 : R27 ( Input, Output ) 1 : EC3 ( Input ) R31/ INT2 Selection 0 : R31 ( Input ) 1 : INT2 ( Input ) R26 / EC2 Selection 0 : R26 ( Input, Output ) 1 : EC2 ( Input ) R17 / INT3 Selection 0 : R17 ( Input ) 1 : INT3 ( Input ) EXT. INTERRUPT EDGE SELECTION REGISTER ¦¡ ¦¡ W W W W W W 7 6 5 4 3 2 1 0 ¦¡ ¦¡ Initial Value(at RESET) IEDS <00CBH> IED3H IED3L IED2H IED2L IED1H IED1L [ --00 0000 ] Edge selection of external INT input signal. 00 : No Input Selection 01 : Falling Edge Selection 10 : Rising Edge Selection 11 : Both of Edge All Selection TABLE 3.7.1 Measurement Interrupt Interval and Edge Selection Period Width of Pulse Sym bol IED*H IED*L ¨Í 1 0 ¨Î 0 1 ¨Ï 1 1 ¨Ð 1 1 INT Input Signal ¨Í ¨Î ¨Ï ¨Ð FIG 3.7.2 The Kind of Interrupt Interval 3 - 39 GMS 84512 / 84524 3.7.2 Interrupt Interval Measurement Method The following is a interrupt interval measurement method. ¨ç Select interrupt input port to be used by writing data to FUNC(00CAH) ¨è To measure interrupt interval, select the edge of interrupt input signal by writing data to IEDS( 00CBH ) ¨é Control to write data to IDCR (Interrupt interval measurement control register) . When IDST(bit0 fo IDCR) is "1", counter is operating. If IDCK (bit1 of IDCR) selecting measurement clock is "0", PS9(64§Á) is selected, otherwise PS8(32§Á) is selected. If ISEL(bit of IDCR) selecting external interrupt input is "0", INT1 is selected, otherwise INT2 is selected. ¨ê If using edge of interrupt input signal is to be input automatically the value of counter is stored to IDR(00EDH), after 1 machine cycle, counter is to be clear and go on count-up. So, interrupt interval is measured continuously. INTERRUPT INTERVAL DETERMINATION CONTROL REGISTER ¦¡ ¦¡ ¦¡ ¦¡ ¦¡ R/W R/W R/W 7 6 5 4 3 2 1 0 ¦¡ ¦¡ ¦¡ ¦¡ ¦¡ ISEL IDCK IDST IDCR <00ECH> Initial Value(at RESET) [ ---- -000 ] COUNTER Start/Stop Control 0 : Count Stop 1 : After Counter Clear Start Count-Up No use External INT. input selection 0 : INT1 1 : INT2 Interval Measurement Clock Selection 0 : 64§Á 1 : 32§Á Rising Edge INT Input Signal 33H After 1 Machine Cycle 1FH 8-bit Counter 00H Start IDR Clear Clear ? Clear 1FH FIG 3.7.3 The example of Interrupt Interval Measurement 3 - 40 33H GMS 84512 / 84524 3.8 3.8.1 On Screen Display ( OSD ) OSD Overview The OSD of GMS84512/84524 can display maxium 128 kinds of character or symbol to CRT screen, basically GMS84512/84524 incorporates a 22 characters ¡¿3lines CRT display control circuit. If OSD interrupt is to be used, maxium 12 lines can be displayed. Especially, GMS84512/84524 is equipped with smoothing function and color edge function. 3.8.2 Feature of OSD l OSD CLOCK l The Nnmber of Character : 128 characters ( include 2 test characters ) l Display Ability 22 Character ¡¿ 3 lines : : 4 §Ö ¡- 8 §Ö ( use OSD Interrupt : enable 12 lines ) l Character Size : 16 kinds ( every line unit ) l Character Color : 8 kinds ( every character unit ) l Font Configulation : 14 ¡¿18 Dots l Display Position : Horizontal 61 steps, Vertical 128 step (every line unit) l Display MOde : Character Mode, Color Edge Mode, Background Mode Blanking Mode ( every line unit ) 3.8.3 l Background Size l Background and Edge Color l Smoothing Function l OSD Oscillator Control Function : Domain of total screen, domain of line unit : 8 kinds Configuration of OSD The OSD of GMS84512/84524 is equipped with OSD oscillator, timing circuit, display position register (HDP1, HDP2, HDP3, VDP1, VDP2, VDP3) display mode register (DMSS1, DMSS2, DMSS3), display control register (OSDCON1, OSDCON2), character ROM storing 128 kinds of character font, display RAM (22 character ¡¿ 3 lines) storing font address and color data of display character and output control circuit. Fig 3.8.1 is a block of OSD circuit of GMS84512/84524 3 - 41 GMS 84512 / 84524 Data BUS 6 Display Mode Register 7 Display Position Register HDP1 HDP1 VDP1 HDP1 6 7 HDP1 DMSS1 HDP1 HDP1 Vertical Position Detection Circuit 7 HDP1 Horizontal Position Detection Circuit Hsync Vsync 2 SM, MOD VS HS OSD Clock 7 VPS 2 HPS RAM Address Generation Circuit Timing Generation Circuit DISPLAY RAM ( 3¡¿22¡¿10 bit ) 7 7 VPS Row Address Generation Circuit 5 CHARACTER ROM ( 128 ¡ ¿ 14 ¡ ¿ 18 ) Character Address Character Color 3 VD Control Circuit 14-bit Shift Register Dot Clock OSC2 R OUTPUT CONTROL CIRCUIT 14 HD 3 G B Y Serial Font Data OSDON 5 3 OSC1 3 OSC, PH, PV 3 5 OSDCON2 OSDCON1 8 8 Data BUS FIG. 3.8.1 3 - 42 BCOL, PY, PB, PG, PR Configuration of OSD Block 4 to PORT GMS 84512 / 84524 3.8.4 0200H ¡-02DF H ) OSD DISPLAY RAM ( 2-page, OSD DISPLAY RAM is storing 3lines¡¿ 22 characters of character address and color, gives data to character font ROM and output control circuit in order to do OSD output. When data are input, OSD display RAM separates character address and color and accesses twice. When data are output, data(10bits) are output once. If OSD RAM (2page) accessable register PG2R(00FCH) is set "1" instruction of direct page addressing mode can be used to OSD DISPLAY RAM. TABLE 3.8.1 Direct Page Access Method G-Flag = 1 G-Flag = 0 0 PG2R = 0 PG2R = 1 1 2 Page Page TABLE 3.8.2 OSD DISPLAY RAM ADDRESS (2-page, Page 0200H ¡-02DF H ) 1ST LINE 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 CHARACTER 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 10 11 12 13 14 15 COLOR 80 81 82 83 84 85 86 87 88 89 8A 8B 8C 8D 8E 8F 90 91 92 93 94 95 2ND LINE 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 CHARACTER 20 21 22 23 24 25 26 27 28 29 2A 2B 2C 2D 2E 2F 30 31 32 33 34 35 COLOR A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 AA AB AC AD AE AF B0 B1 B2 B3 B4 B5 3RD LINE 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 CHARACTER 40 41 42 43 44 45 46 47 48 49 4A 4B 4C 4D 4E 4F 50 51 52 53 54 55 COLOR C0 C1 C2 C3 C4 C5 C6 C7 C8 C9 CA CB CC CD CE CF D0 D1 D2 D3 D4 D5 2 3RD Line 2'st Character B G 0 6 R C6 Color Data Color 0 C5 C4 C3 C2 C1 C0 Character Address ( 128 kinds) B G R Black 0 0 0 Red 0 0 1 Green 0 1 0 Yellow 0 1 1 Blue 1 0 0 Purpul 1 0 1 Cyan 1 1 0 White 1 1 1 FIG. 3.8.2 OSD DISPLAY RAM and DATA Configuration 3 - 43 GMS 84512 / 84524 3.8.5 OSD DISPLAY MODE REGISTER ( DMSS1, DMSS2, DMSS3 ) OSD Display mode register is register to control Display Character Size, Display Mode, Smoothing function. OSD display mode register is every display line, so OSD display mode is determined by line. OSD MODE REGISTER DMSS1 <00F6H> ¦¡ W W W W W W W 7 6 5 4 3 2 1 0 ¦¡ 1SM 1HS0 1VS1 1VS0 DMSS2 1MOD 1MOD 1HS1 1 0 Initial Value (At Reset) [ -000 0000 ] <00F7H> Character size definition DMSS3 VS <00F8H> Smoothing Function definition 0 : Smoothing Off 1 : Smoothing On l Display Mode Definition 00 : Blanking Mode 01 : Character Mode 10 : Color Edge Mode 11 : Background Mode 00 01 10 11 00 1×1 1×2 1×3 1×4 01 2×1 2×2 2×3 2×4 10 3×1 3×2 3×3 3×4 11 4×1 4×2 4×3 4×4 Character Size Definition (every line unit) Each character basic configuration is a 14¡¿ 18 dots. The dot size of vertical direction is determined by VS1, VS0(bit1, 0 of DMSS) and the dot size of Horizontal direction is determined by HS1, HS0(bit3, 2 of DMSS). So, the size of display character is to be changable. TABLE 3.8.3 Character Size Definition HS1, HS0 3 - 44 00 01 10 11 VS1, VS0 00 1¡¿1 2¡¿1 3¡¿1 4¡¿1 01 1¡¿2 2¡¿2 3¡¿2 4¡¿2 10 1¡¿3 2¡¿3 3¡¿3 4¡¿3 11 1¡¿4 2¡¿4 3¡¿4 4¡¿4 GMS 84512 / 84524 l Display Mode Definition (every line unit) Display Mode is defined by MOD1, MOD0(bit5, 4 of DMSS) and is blanking mode, character mode, color edge mode, background mode and so on. Background domain is determined by BCOL(bit6 of OSDCON2). If BCOL is "0" line domain is determined on the contrary, if BCOL is "1" total screen is determined. Notes : When BCOL is "1" only background mode is enable (Refer to Fig 3,8,3) Mode Blanking Mode Character Mode Color Edge Mode Background Mode MOD1,MOD0 00 01 10 11 ABCD ABCD ABCD ABCD ABCD Normal Character Color Edge Character BCOL=0 BCOL=1 ABCD Picture FIG. 3.8.3 Background Color DISPLAY MODE 3 - 45 GMS 84512 / 84524 l Smoothing Function Definition (every line unit) When the size of display character is over 2-times than normal size, smoothing function can smooth the rectangular part. Smoothing function is defined by SM (bit 6 of DMSS) (If SM is "1" function is ON, otherwise function is OFF) Fig 3.8.4 shows color edge function and smoothing function 2 2 Original Dot Smoothing Dot Color Edge Dot FIG. 3.8.4 3 - 46 Color Edge Function and Smoothing Function GMS 84512 / 84524 3.8.6 OSD Display Position Register( HDP1¡-HDP3, VDP1¡-VDP3) OSD Display Position Register defines horizontal, vertical position of screen every each display line. HDPi, VDPi define display position of i-line first character. (only I= 1,2,3) <Note> The value of HDPi is to be over four, the value of VDPi don't have to be included in domain of previous line. OSD HORIZONTAL POSITION REGISTER ¦¡ ¦¡ W W W W W W 7 6 5 4 3 2 1 0 ¦¡ ¦¡ 1HP5 1HP4 1HP3 1HP2 1HP1 1HP0 HDP1 <00F0H> HDP2 Initial Value(at Reset) [ --00 0000 ] <00F1H> HDP3 Each Line Horizontal Position Definition HSi = To ¡¿ { 4 ¡¿ ( HDPi) £« 10 } [ To = OSD Clock Period, i = 1, 2, 3 ] <00F2H> OSD VERTICAL POSITION REGISTER VDP1 <00F3H> ¦¡ W W W W W W W 7 6 5 4 3 2 1 0 ¦¡ 1VP6 1VP5 1VP4 1VP3 1VP2 1VP1 1VP0 VDP2 Initial Value (at Reset) [ -000 0000 ] <00F4H> VDP3 Each Line Vertical Position Definition VSi = 2 ¡¿ H ¡¿ ( VDPi ) [ H orizontal Synchronous Signal Period,, i = 1, 2, 3 ] <00F5H> VS1 l Horizontal Display Position ( HSi ) HSi = To ¡¿ { 4 ¡¿ ( HDPi ) £« 10 } [ To = OSD Clock Period, HS1 VS2 VS3 i = 1, 2, 3 ] HS2 l CH 23 Fuzzy ON Vertical Display Position ( VSi ) VSi = 2 ¡¿ H ¡¿ ( VDPi ) [H = Horizontal Synchronous Signal Period, HS3 ABCD EFG HIJK i = 1, 2, 3 ] FIG. 3.8.5 CRT Screen and Display Position 3 - 47 GMS 84512 / 84524 3.8.7 OSD output Control Register( OSDCON1, OSDCON2 ) l OSDCON1 ( 00F9H ) OSD output control register 1( OSDCON1 )defines background and edge color (BB, BG, BR) and is enable/disable OSD output(OSDON) and defines function of output port. (OY, OB, OG, OR) OSD OUTPUT & BACKGROUND CONTROL REGISTER W W W W W W W W 7 6 5 4 3 2 1 0 OY OB OG OR OSDON BB BG BR Initial Value (at Reset) OSDCON1 <00F9H> R53/ Y Selection 0 : R53 1:Y R52/ B Selection 0 : R52 1:B R51/ G Selecton 0 : R51 1:G l [ 0000 0000 ] Background and Edge Color Selection OSD Output Control 0 : Disable 1 : Enable R50/ R Selection 0 : R50 1:R OSDCON2 ( 00FAH ) OSD output control register 2 (OSDCON2) defines the polarity of OSD output(PY,PB,PG,PR) and selects the polarity of input HD, VD(PH,PV) and defines background domain(BCOL) and defines the type of OSD oscillation (OSC). OSD I/O POLARITY & OSCILLATION CONTROL REGISTER W W W W W W W W 7 6 5 4 3 2 1 0 OSC BCOL PH PV PY PB PG PR OSDCON2 <00FAH> Initial value (At Reset) [ 0000 0000 ] B polarity H-sync V-sync R polarity Polarity Polarity Ypolarity G polarity Background domain determination 0 : Line area 1 : Full screen area Oscillation type 0 : Always (Full screen) 1 : Not Always ( Oscillation where only displayed) 3 - 48 Polarity control 0 : Active low 1 : Active high GMS 84512 / 84524 3.8.8 MULTI LINE DISPLAY The OSD function of GMS84512/84524 is basically enable 3-line display, but if OSD interrupt is used maximum up to 12 lines can be displayed. OSD interrupt request occurs when OSDON(bit3 of OSDCON1) is "1" and each line display finishes, and OSD interrupt happens when OSD interrupt request occurs, at this time I-Flag(bit2 of PSW) and OSDE(bit7 of IENH(00EAH)) has to set "1". OSD Display allows multiple lines(more than 3 lines) to be displayed on the screen by OSD interrupt, each time one line is displayed and rewriting display RAM data, display position register (HDPi, VDPi) and display mode register in the OSD interrupt service routine for which display is terminated. l 6 Line Display Occasion ¨ç 1'st Line Dispaly ¡æ Load 4'th line data(contents, position, mode) to 1'st line RAM and register. ¨è 2'nd Line Dispaly ¡æ Load 5'th line data(contents, position, mode) to 2'nd line RAM and register ¨é 3'rd Line Display ¡æ Load 6'th line data(contents, position, mode) to 3'rd line RAM and register ¨ê 4'th Line Dispaly ¨ë 5'th LIne Dispaly ¨ì 6'th Ling Dispaly 1’st LINE 1’st Line Display RAM HDP1, VDP1, DMSS1 2’nd LINE 3’rd LINE 3’rd Line Display RAM HDP3, VDP3, DMSS3 2’nd Line Display RAM HDP2, VDP2, DMSS2 FIG. 3.8.6 OSD Display Method 3 - 49 GMS 84512 / 84524 3.8.9 Character ROM The character ROM of GMS84512/84524 stores 128 kinds of font dot pattern data. 36bytes of dot pattern data needs to display one character. Fig 3.8.7 is a example of character dot pattern, TABLE 3.8.4 is a relation about character code and character dot pattern address. OTP / MAIN MDS EPROM 1 Addr. Data Addr. Data 060H 061H 062H 063H 064H 065H 066H 067H 068H 069H 06AH 06BH 06CH 06DH 06EH 06FH 070H 071H 2830H 2831H 2832H 2833H 2834H 2835H 2836H 2837H 2838H 2839H 283AH 283BH 283CH 283DH 283EH 283FH 3830H 3831H 00H 00H 30H 18H 0CH 06H 03H 01H 01H 03H 06H 0CH 18H 30H 00H 00H 00H 00H 00H 00H 30H 18H 0CH 06H 03H 01H 01H 03H 06H 0CH 18H 30H 00H 00H 00H 00H OTP / MAIN Character Code = 03H MSB Fig. 3.8.7 LSB MDS Addr. Data EPROM 2 Addr. Data 2030H 2031H 2032H 2033H 2034H 2035H 2036H 2037H 2038H 2039H 203AH 203BH 203CH 203DH 203EH 203FH 3030H 3031H 00H 00H 06H 0CH 18H 30H 60H 40H 40H 60H 30H 18H 0CH 06H 00H 00H 00H 00H 060H 061H 062H 063H 064H 065H 066H 067H 068H 069H 06AH 06BH 06CH 06DH 06EH 06FH 070H 071H 00H 00H 06H 0CH 18H 30H 60H 40H 40H 60H 30H 18H 0CH 06H 00H 00H 00H 00H The Example of Character Dot Pattern TABLE 3.8.4 The relation of Character Code and Dot Pattern Address Character OTP / MAIN CHIP CODE Upper 7 - Bits Lower 7 - Bits Upper 7-bit,Lower 7bit 00H 2800H ¡-280F H , 3800H , 3801H 2000H ¡-200F H , 3000H , 3001H 000H ¡-011 H 01H 2810H ¡-281F H , 3810H , 3811H 2010H ¡-201F H , 3010H , 3011H 020H ¡-031 H 02H 2820H ¡-282F H , 3820H , 3821H 2020H ¡-202F H , 3020H , 3021H 040H ~ 051H 03H 2830H ¡-283F H , 3830H , 3831H 2030H ¡-203F H , 3030H , 3031H 060H ¡-071 H XXH ( 2800H + XX0H)¡-(2800H + XXFH ) ( 3800H + XX0H) , (3800H + XX1H ) ( 2000H + XX0H)¡-(2000H + XXFH ) ( 3000H + XX0H) , (3000H + XX1H ) ( 20H * XXH + 00H ) ¡-( 20H * XXH + 11H ) 7EH * 2FE0H ¡-2FEF H , 3FE0H , 3FE1H 27E0H ¡-27EF H , 37E0H , 37E1H FC0H ¡-FD1 H 7FH * 2FF0H ¡-2FFF H , 3FF0H , 3FF1H 27F0H ¡-27FF H , 37F0H , 37F1H FE0H ¡-FF1 H * these addresses are reserved for test ( user not available ) 3 - 50 MDS GMS84512/84524 USER’S MANUAL Table of Contents 1. Overview 2. CPU 3. Peripheral Function 4. Control Function 5. Support Tool 6. Appendix GMS 84512 / 84524 4.1 INTERRUPTS GMS84512/84524 has the following function to process interrupt request from the peripheral and external interrupt pin. l Interrupt Source : 14 l Interrupt Vector : 14 l Multi Interrupt Possible. l Programmable Interrupt Mode ¨ç Hardware Priority Mode ¨è Software Selection Mode l R/W of Interrupt Request Flag is possible and in Interrupt Accept, automalically resetted. 4.1.1 Interrupt Circuit Configuration and Kinds GMS84512/84524 Interrupt circuits is consist of Interrupt Enable Register (IENH,IENL), Interrupt Request Register (IRQH,IRQL), priority circuit and selecting circuit. Configuration of Interrupt circuit is shown in Fig. 4.1.1 The Interrupt sources are external interrupt source(INT1, INT2, INT3, V-sync), peripheral function source(OSD,T0,T1,T2,T3,1ms,WDT,BIT,Serial I/O) and software interrupt source(BRK). In the case of reset input(RESET), the program execution at the start address located in vector table address like general interrupt. The classification of interrupt source is shown in Table 4.1.1. 4-1 GMS 84512 / 84524 Data BUS 8 6 8 IMOD IENH 0 1 2 3 4 5 6 7 RESET 0 1 2 3 4 5 ¡ ©¡ © 4 IRQH IFOSD OSDR INT1 INT1R INT2 INT2R IFT0 T0R IFT2 T2R IF1m 1msR IFVsync IFT1 7 Standby Mode Release VSYNC PRIORITY T1R CONTROL 0 IFT3 T3R INT3 INT3R IFWDT WDTR IFBIT IFS 7 I-FLAG BRK 13 BITR SR to CPU 3 IRQL 7 6 5 4 3 ¡© ¡© ¡© IENL 5 5 INTERRUPT VECTOR ADDRESS GEN. 8 Data BUS FIG. 4.1.1 4-2 Interrupt Function Block Diagram GMS 84512 / 84524 TABLE 4.1.1 Interrupt Request Source Type Mask Priority Non Maskable Interrupt Request Source Vector Vector H L 1 RST Reset Pin FFFFH FFFEH 2 OSD On Screen Display FFFBH FFFAH 3 INT1R External Interrupt 1 FFF9H FFF8H 4 INT2R External Interrupt 2 FFF7H FFF6H 5 T0R Timer 0 FFF5H FFF4H 6 T2R Timer 2 FFF3H FFF2H 1§Â Interrupt FFF1H FFF0H Hardware Mask 7 1ms Interrupt Enable 8 VSYNC V-sync Interrupt FFEFH FFEEH 9 T1R Timer 1 FFEDH FFECH 10 T3R Timer 3 FFEBH FFEAH 11 INT3R External Interrupt 3 FFE9H FFE8H 12 WDTR Watch Dog Timer FFE7H FFE6H 13 BITR Basic Interval Timer FFE5H FFE4H 14 SR Serial I/O FFE3H FFE2H ¡ª BRK Break Instruction FFDFH FFDEH S/W Interrupt Non Maskable 4.1.2 Interrupt Control l To process interrupt, set the interrupt master enable flag I-Flag(3'rd bit of PSW). when I-Flag="0" all interrupts are disable except RESET and S/W interrupt. l Interrupt Enable Register ( IENH, IENL) includes interrupt enable bits of each interrupt ` source, and interrupt is accepted when the interrupt enable bit and the interrupt request bit are both "1". INTERRUPT ENABLE REGISTER H, L R/W R/W R/W R/W R/W R/W R/W R/W 7 6 5 4 3 2 1 0 T0E T2E IENH <00EAH> OSDE INT1E INT2E 1mE Vsync E T1E R/W R/W R/W R/W R/W ¦¡ ¦¡ ¦¡ 7 6 5 4 3 2 1 0 SE ¦¡ ¦¡ ¦¡ IENL <00E8H> T3E INT3E WDTE BITE Initial Value (At Reset) [ 0000 0000 ] Initial Value (At Reset) [ 0000 0--- ] Interrupt Masking Flag 0 : Interrupt Disable 1 : Interrupt Enable 4-3 GMS 84512 / 84524 l Interrupt Request Flag Register ( IRQH, IRQL) When interupt occurs, interrupt request flag is set. The accepted interrupt request flag is automatically cleared by interrupt process cycle. As long as the interrupt request flag which is set to "1" is not cleared by program, it maintains '1" until interrupt is accepted. Interrupt Request Flag Register ( IRQH, IRQL) is Read/ Write Register. So, it is possible to be checked and changed by program. INTERRUPT REQUEST FLAG REGISTER H, L R/W R/W R/W R/W R/W R/W R/W R/W 7 6 5 4 3 2 1 0 IRQH OSDR INT1R INT2R <00EBH> T0R T2R Vsync 1mR R Initial Value (At Reset) T1R R/W R/W R/W R/W R/W ¦¡ ¦¡ ¦¡ 7 6 5 4 3 2 1 0 SR ¦¡ ¦¡ ¦¡ Initial Value (At Reset) IRQL T3R <00E9H> INT3R WDTR BITR [ 0000 0000 ] [ 0000 0--- ] Interrupt Request Flag 0 : Disable 1 : Enable l Interrupt Mode Register ( IMOD) Interrupt Mode Register determines interrupt priority which can be selected by hardware or program. INTERRUPT MODE REGISTER ¦¡ ¦¡ R/W R/W R/W R/W R/W R/W 7 6 5 4 3 2 1 0 ¦¡ ¦¡ IM1 IM0 IP3 IP2 IP1 IP0 IMOD <00E6H> Interrupt Mode Definition 00 : Mode 0 (Priority by H/W) 01 : Mode 1(Definition by IP3¡-IP0) 1- : Inhibit Interrupt 4-4 Initial Value (At Reset) [ Undefined ] Interrupt Definition Selection 0000 : ¦¡ 1000 : TIMER 1 0001 : OSD 1001 : TIMER 3 0010 : INT1 1010 : INT3 0011 : INT2 1011 : WDT 0100 : TIMER 0 1100 : B.I.T. 0101 : TIMER 2 1101 : SERIAL 0110 : 1024§Á 1110 : ¦¡ 0111 : V-SYNC 1111 : ¦¡ GMS 84512 / 84524 l Interrupt Mode ¨Í Mode 0 ( Priority by H/ W ) OSDR£¾ INT1R£¾INT2R£¾ T0R£¾T2R£¾1mR£¾VSYNCR£¾T1R£¾T3R£¾ INT3R£¾WDTR£¾BITR£¾SR ¨Î Mode 1 (Selection by IP3 ¡- iP0) TABLE 4.1.2 Selection of Interrupt by IP3 ¡- IP0 IP3 IP2 IP1 IP0 l Selection Interrupt 0 0 0 0 ¡ª 0 0 0 1 OSDR On Screen Display 0 0 1 0 INT1R External Interrupt 1 0 0 1 1 INT2R External Interrupt 2 0 1 0 0 T0R Timer 0 0 1 0 1 T2R Timer 2 0 1 1 0 1msR 1§Â Interrupt 0 1 1 1 VSYNCR External V-sync Interrupt 1 0 0 0 T1R Timer 1 1 0 0 1 T3R Timer 3 1 0 1 0 INT3R External Interrupt 3 1 0 1 1 WDTR Watch Dog Timer 1 1 0 0 BITR Basic Interval Timer 1 1 0 1 SR Serial I/O 1 1 1 0 ¡ª 1 1 1 1 ¡ª Interrupt Accept Timing System Clock Instruction Fetch 1 Cycles 0¡-12 Cycles A command before Interrupt 8 Cycles Interrupt Process Step Interruptroutine Int.request Sampling Interrupt Cycles Overhead : 9¡-21 FIG. 4.1.2 Interrupt Accept Timing 4-5 GMS 84512 / 84524 l The vlaid timing after executing Interrupt control Flag ¨Í I-Flag is valid, after EI, DI executed ¨Î IENH, IENL register is valid after next instruction 4.1.3 INTERRUPT SEQUENCE When interrupt is accepted, the execution program is stopped, a certain of interrupt processing step is passed, and interrupt sevice routine is started. By last instruction of interrupt service routine(RETI) return to original program. l Interrupt Process Sequence PCH Stacking sp¡çsp -1 PCL Stacking sp¡çsp -1 PSW Stacking sp¡çsp -1 I-Flag = “0” (B-Flag= “1” at BRK) Interrupt Service Routine System Clock Instruction Fetch Address Bus pc Data Bus not Used sp PCH sp-1 PCL sp-2 PSW V.L V.L V.H ADL ADH new pc Opcode Internal Read Internal Write Interrupt Process Step Interrupt Service Routine V.L, V.H is Vector Address, ADL, ADH is start Address of Interrupt Service Routine as Vector Contents FIG. 4.1.3 Interrupt Process Step Timing 4-6 GMS 84512 / 84524 4.1.4 Software Interrupt Software interrupt is interrupted by BRK instruction. cleared. In interrupt processing step I-Flag is B-flag is setted. Interrupt vector of BRK instruction is shared with the vector of table call 0, when both instruction of BRK and TCALL 0 are used, each processing routine is executable through looking at the contents at B-Flag. There is no instruction to Reset B-Flag directly. N PSW V G B H I Z C ¡ª 1 ¡ª 0 ¡ª ¡ª After BRK Instruction ¡ª ¡ª B-Flag ? BRK or TCALL0 0 1 BRK Interrupt Routine TCALL 0 Routine RTNI RTN FIG. 4.1.4 Execution of BRK/ TCALL0 4.1.4 Multiple Interrupt If there is an interrupt, interrupt enable flag is automalically resetted entering the interrupt service routine. After then, no interrupt is accepted. If EI instruction is executed, mask enable bit becomes "1", and each enable bit can accept the interrupt as a reply to 1's interrupt request. If multiple of interrupt request occurs at same time, the one with a higher priority is accepted and the other with lower priority are retained. 4-7 GMS 84512 / 84524 When multiple interrupt is accepted, it is possible to change Interrupt Accept Mode. l Case of multiple interrupt at hardware priority accept mode(Mode0) Main Program ( Mode 0 ) 1’st INT. Routine ( Mode 0 ) 2’nd INT. Routine ( Mode 0 ) 3’rd INT. Routine EI Interrupt l EI Interrupt EI Interrupt Case of multiple interrupt nest H/W priority accept mode (Mode0) and S/W selection accept mode(Mode1) Main Program ( Mode 0 ) 1’st INT. Routine ( Mode 0 ) 2’nd INT. Routine ( Mode 1 ) 3’rd INT. Routine EI Interrupt EI Stacking IMOD Change Mode EI Interrupt Interrupt Reload IMOD 4-8 GMS 84512 / 84524 4.2. Standby Function To save the consuming power of device,GMS84512/84524 has Stop Mode. In this mode,the execution of program stop. Stop Mode can be entered by Stop instruction. 4-9 GMS 84512 / 84524 OSC. Clock Pulse GEN. Circuit CLR MUX halt Prescaler Basic Interval Timer CLR STOP CPU Clock IFBIT CLR S Q S Q R Q R Q Overflow Detection RESET Release Signal from Interrupt Circuit FIG. 4.2.1 STOP Mode Circuit Diagram TABLE 4.2.1 At STOP Mode Device Operation State. Peripheral Function STOP Mode Oscillator ¡¿ CPU Clock ¡¿ RAM, Register Retain I/O Port Retain Prescaler ¡¿ Basic Interval Timer ¡¿ Serial I/O Operation( External Clock Selection) WDT, Timer, A/D Comp., PWM, OSD, Interrupt Interval Mesurment Circuit 4 - 10 ¡¿ GMS 84512 / 84524 4.2.1 STOP Mode STOP Mode can be entered by STOP instruction during program execution. In STOP mode, oscillator is stopped to make all clocks stop, which leads to the mode requring much less power consumption. All register and RAM data are preserved. 4.2.2 STOP Mode Release Release of STOP mode is done by reset input or interrupt. When there is a release signal of STOP mode, the instruction execution is started after stabilization oscillation time set by program. After releasing STOP mode, instruction execution is different by I-Flag(bit 2 of PSW) If I-Flag = “1” entered Interrupt Service Routine, If I-Flag = “0” execute program from next instruction of STOP instruction. TABLE 4.2.1 STOP Mode Release Release Factor RESET INT1,INT2 INT3, Release Method STOP By RESET pin=Low level, and Device is initialzed. In the state of enable flag=1 corrosponding to each interrupt at the edge. V-sync Serial I/O ( IFSIO ) l When SE="1" and serial I/O is executing by external clock, interrupt occurs by serial I/O operation completed Release Timing of STOP Mode STOP System Clock Release Signal by interrupt Stabilization oscillation time + 8 Cycles ¡è RESET STOP Mode Stabilization Oscillation Time determined by program. 4 - 11 GMS 84512 / 84524 When release the STOP Mode, to secure oscillation stabilization time,we use a B.I.T. So before execution STOP instruction, we must select suitable BIT clock for oscillation stabillization time. Otherwise, It is possible to release by only RESET input. l Because STOP mode is released by interrupt, even if both of interrupt enable bit(IE) and interrupt request flag is "1", STOP mode can not be executed. STOP Command STOP Mode Interrupt Request IE ? 0 1 STOP Mode Release I-Flag ? 1 Next Command Execution Interrupt Service Routine FIG. 4.2.2 STOP Mode Releasing Flow 4 - 12 0 GMS 84512 / 84524 4.3. Reset Function To reset the device, maintain the RESET="L" at least 8 machine cycle after power supplying and oscillation stabilization. RESET terminal is organized as schmitt input. TABLE 4.3.1 is, at Reset, initial value of each register, if initial value is undefined it is needed initialize by a S/W. Fig 4.3.1 is Timing of Reset Operation (Simular as interrupt instruction) l CLOCK CONTROL REGISTER CLOCK CONTROL REGISTER CKCTLR W W W W W W W W 7 6 5 4 3 2 1 0 ¦¡ ¦¡ WDTON ENPCK BTCL BTS2 BTS1 BTS0 Initial Value (At Reset) BITR : [ Undefined ] CKCTLR : [ --01 0111 ] <00CEH> B.I.T. value ( Read ) B.I.T Input Clock Selection (Initial Value) 111 : PS11 ( 256§Á) WDT Function Control( Initial Value ) 0 : 6bit TIMER B.I.T. Clear ( Initial Value) 0 : B.I.T. FREE-RUN Peripheral Clock Enable(Initial Value) 1 : Peripheral Clock Supply System Clock RESET Instruction Fetch Address Bus Data Bus ? ? ? ? ? ? ? ? FFFE FE ADL FFFF ADH Start Opcode Internal Read RESET Process Step Main Program FFFEH, is vector address and ADL, ADH is start address of main program as vector contents FIG. 4.1.1 RESET Operation Timing 4 - 13 GMS 84512 / 84524 TABLE 4.3.1 Initial state of each register at reset BLOCK Symbol Address Register Name Initial Value R/W PAGE 7 6 5 4 3 2 1 0 CPU PORT A ¡ª A - Register ¡ª Undefined 2-2 X ¡ª X- Register ¡ª Undefined 2-2 Y ¡ª Y - Register PSW ¡ª Program Status PC ¡ª Program Counter SP ¡ª Stack A/D COMP. Pointer R0 00C0H R0 Port Data R0DD 00C1H R0 Port I/O R1 00C2H R1 Port Data R1DD 00C3H R1 Port I/O Register Direction Register Register Direction Register Register 2-2 ¡ª 2-3 ¡ª Undefined 2-3 ¡ª Undefined 2-2 R/W Undefined 3-1 W 0 0 0 0 0 0 0 0 3-1 R/W Undefined 3-2 W 0 0 0 0 0 0 0 0 3-2 00C4H R2 Port Data 00C5H R2 Port I/O R3 00C6H R3 Port Data R3DD 00C7H R3 Port I/O R4 00C8H R4 Port Data Register R/W - - R5 00C9H R5 Port Data Register R/W - - - - Undefined FUNC 00CAH Port IEDS 00CBH External BITR 00CEH Direction Register Register Direction Function Register Selection Interupt Edge Basic Interval Timer Clock Control Register Timer Register Selection Register Register Undefined 3-4 W 0 0 0 0 0 0 0 0 3-4 R/W Undefined 3-6 W 0 0 0 0 0 0 - Undefined 3-6 3-9 3 - 10 W - - - 0 0 0 0 0 3 - -3 W - - 0 0 0 0 0 0 3 - 39 R Undefined 3 - 16 W - - 0 1 0 1 1 1 3 - 13 W 00CFH Watch Dog - 0 1 1 1 1 1 1 3 - 17 TM0 00D0H Timer Mode Register0 R/W - 0 0 0 0 0 0 0 3 - 21 TM2 00D1H Timer Mode Register2 R/W - 0 0 0 0 0 0 0 3 - 21 TDR0 00D2H Timer0 Data Register R/W Undefined 3 -21 TDR1 00D3H Timer1 Data Register R/W Undefined 3 - 21 TDR2 00D4H Timer2 Data Register R/W Undefined 3 - 21 TDR3 00D5H Timer3 Data Register R/W Undefined CMR 00D6H A/D Comparator Mode Comparator Channel CIS 00D7H A/D SIOM 00D8H Serial I/O Mode SIOR 00D9H Serial I/O Data IMOD 00E6H Interrup Mode Register R/W WDTR Register W*6 0 0 - 0 0 0 0 0 Selection Register Register Register Register IENL 00E8H Interrupt Enable IRQL 00E9H Interrupt Request Flag IENH 00EAH Interrupt Enable Register IRQH 00EBH Interrupt Request Flag Register High IEDS 00CBH External Interupt Edge Selection Register INTERRUPT IDCR 00ECH Interrupt Interval Determination Control Register INTERVAL D. IDR 00EDH Interrupt Interval Determination Register 4 - 14 Undefined 0 0 0 0 0 0 0 0 R2 SERIAL I/O INTERRUPT ¡ª R2DD CKCTLR TIMER Word Register Low Register Low High W 3 - 21 3 - 27 - - - - - - 0 0 3 - 27 R/W - 0 0 0 0 0 0 1 *0 3 - 29 R/W 3 - 28 Undefined R/W - - 0 0 0 0 0 0 4-4 R/W 0 0 0 0 0 - - - 4-3 R/W 0 0 0 0 0 - - - 4-4 R/W 0 0 0 0 0 0 0 0 4-3 R/W 0 0 0 0 0 0 0 0 W 4-4 - - 0 0 0 0 0 0 3 - 39 R/W - - - - - 0 0 0 3 - 40 R 0 0 0 0 0 0 0 0 3 - 38 GMS 84512 / 84524 TABLE 4.3.1 Initial State of Each Register at Reset BLOCK SYMBOL Address Register Name Initial Value R/W PAGE 7 6 5 4 3 2 1 0 PWM0 PWM OSD ¡Ø -: Not use, 00DAH PWM0 Data Register W - Undefined 3 - 35 PWM1 00DBH PWM1 Data Register W - Undefined 3 - 35 PWM2 00DCH PWM2 Data Register W - Undefined 3 - 35 PWM3 00DDH PWM3 Data Register W - Undefined 3 - 35 PWM4 00DEH PWM4 Data Register W - Undefined 3 - 35 PWM5 00DFH PWM5 Data Register W - Undefined 3 - 35 PWM6 00E0H PWM6 Data Register W - Undefined 3 - 35 PWM7 00E1H PWM7 Data Register W - Undefined 3 - 35 PWM8H 00E2H PWM8 Data Register High R/W PWM8L 00E3H PWM8 Data Register Low R/W - - PWMCR1 00E4H PWM Control Register1 PWMCR2 00E5H PWM Control Register2 HDP1 00F0H OSD 1st Line Horizontal HDP2 00F1H OSD 2nd Line HDP3 00F2H OSD VDP1 00F3H OSD VDP2 00F4H OSD 2nd Line Vertical Position VDP3 00F5H OSD 3rd Line Vertical Position DMSS1 00F6H DMSS2 DMSS3 Undefined Undefined R/W 0 0 0 0 0 0 0 0 R/W - - - 0 0 0 0 0 Position Register 3 - 36 3 - 36 3 - 37 3 - 37 W - - 0 0 0 0 0 0 3 - 47 Horizontal Position Register W - - 0 0 0 0 0 0 3 - 47 3rd Line Horizontal Position Register W - - 0 0 0 0 0 0 3 - 47 1st Line Vertical W - 0 0 0 0 0 0 0 3 - 47 Register W - 0 0 0 0 0 0 0 3 - 47 Register W - 0 0 0 0 0 0 0 3 - 47 OSD 1st Line Display Mode, Character Size, Smoothing Function Selection Register W - 0 0 0 0 0 0 0 3 - 44 00F7H OSD 2nd Line Display Mode, Character Size, Smoothing Function Selection Register W - 0 0 0 0 0 0 0 3 - 44 00F8H OSD 3rd Line Display Mode, Character Size, Smoothing Function Selection Register W - 0 0 0 0 0 0 0 3 - 44 OSDCON1 00F9H OSD Output and Background W 0 0 0 0 0 0 0 0 3 - 48 OSDCON2 00FAH OSD OSD I/O Polarity Control and Oscilllation Control Register W 0 0 0 0 0 0 0 0 3 - 48 PG2R 00FCH OSD RAM ( 2 page ) R/W - - - - - - - 0 3 - 43 Position Register Control Accessable Register Register *0: bit 0 is READ only, *6: bit 6 is READ only. 4 - 15 GMS84512/84524 USER’S MANUAL Table of Contents 1. Overview 2. CPU 3. Peripheral Function 4. Control Function 5. Support Tool 6. Appendix GMS 84512 / 84524 5.1 EMULATOR { Ref. GMS800 SERIES MDS MANUAL } The CHOICE emulator is a hardware debugging tool for developing user program via the 8 bit core G8MC family from HYUNDAI MicroElectrincs Co., Ltd. [Fig 5.1.1] Environment for developing user program User System Interface Cable Debugger Program RS-232C TV Target MCU CHOICE HOST COMPUTER 5.1.1 EMULATOR USER SYSTEM Configuration of Emulator Emulator CHOICE is constructed by “ADD-ON BOARD” architecture. MAIN Board, CONTROL Board are the base boards of CHOICE and EVA. Board is GMS84512 EVA Board for TV application. l EVA. Chip ( GMS84512EVA : 156 pin PGA ) EVA Chip is special chip for the target MICOM. EVA chip supports target MICOM’s all function & includes interface logic with the emulator hardware. 5-1 GMS 84512 / 84524 5.1.2 Cautionary notes 1.When changing board at expansion slot. You must ensure that power is off. 2. Check and ensure that power for emulator & user system is supplied separately and if this is so, EVA power option jumper must be open before using. 3. Check polarity & connection location when connecting power cable, serial cable or interface cable to board. ¨ Î If Emulator & USER System use same Power Source EMULATOR USER EVA BOARD SYSTEM Vuser SHORT USER Interface Cable MAIN BOARD Vcc Vcc GND GND Power Source ¨ Î If Emulator & USER System use different Power Source USER Interface Cable EMULATOR EVA BOARD USER SYSTEM Vuser OPEN MAIN BOARD Vcc Vcc GND GND Power Power Source 1 Source 2 FIG 5.1.2 Connecting emulator & user system 5-2 GMS 84512 / 84524 5.1.3 USER INTERFACE SOCKET PIN ASSIGNMENT a. ¢Ð Sign indicates unconnected pin. 1 52 R50/ R VD 2 51 R51/ G R45/ PWM0 3 50 R52/ B R44/ PWM1 4 49 R53/ Y R43/ PWM2 5 48 R00 R42/ PWM3 6 47 R01 R41/ PWM4 7 46 R02 R40/ PWM5 8 45 R03 R37/ PWM6 9 44 R04 R36/ PWM7 10 43 R05 R35/ Sin/ Cin3 11 42 R06 R34/ Sclk 12 41 R07 R33/ Sout 13 40 R10 R32/ PWM8 14 39 R11 R31/ INT2 15 38 R12 R30/ INT1 16 37 R13 R27/ EC3 17 36 R14 R26/ EC2 18 35 R15/ Cin1 R25/ T2048 19 34 R16/ Cin2 R24 20 33 R17/ Cin0/ INT3 R23 21 32 R20 R22 22 31 R21 23 ¢Ð 30 RESET ¢Ð 25 ¢Ð ¢Ñ 29 ¢Ñ 28 ¢Ñ 27 TEST Xin Xout Vss Fig 5.1.3. 24 26 GMS84512/84524 HD OSC1 OSC2 Vdd Pin assign of GMS84512 / 84524 interface socket 5-3 GMS 84512 / 84524 5.2 DEBUGGER { Ref. GMS800 SERIES MDS MANUAL } The G8MC Debugger is a S/W tool for developing user programs for the HYUNDAI 8 bit core (G8MC family). We prepared two types of debugger S/W. One is for the MS-DOS and the other is for the MS-Windows ( include MS-Win95 ). 5-4 GMS 84512 / 84524 5.3 ASSEMBLER { Ref. GMS800 SERIES MDS MANUAL } ASSEMBLER is a S/W which translates source code to object code. Especially GMS800 Series is like with high level language. Oject Program ( *.OBJ, *.OB2 ) Source Program ASSEMBLER List File ( *.LST ) 5.3.1 Structure of Source Program List Structure of source program list is shown below. Label Field Opcode Field : space Operand Field space Comment Field ; Character String Numeric constant, Character constant,Operator Label: Symbol 5.3.2 G8MC Instruction, Pseudo-instruction PSEUDO-INSTRUCTION FUNCTION Constant definition ROM data definition Defining RAM symbol Address alteration Program End Inserting external files Refer to external symbols Outputting List files Macro definition PSEUDO-INSTRUCTION EQU (EQUAL) DB (DEFINE BYTE ) DW (DEFINE WORD ) DS (DEFINE STORAGE ) ORG (ORIGIN ) END INCLUDE PUBLIC EXTRN (EXTERNAL ) LIST NOLIST (NO LIST ) TITLE PAGE MACRO ENDM (END OF MACRO ) 5-5 GMS 84512 / 84524 5.3.3 STRUCTURED COMMANDS l Assignment Statement ( = ) l IF Statement IF <rel_expr> <statement> ENDIF l IF <rel_expr> <statement 1> ELSE <statement 2> ENDIF FOR Statement FOR <rel_expr> <statement> NEXT l <rel_expr> relational operator £¼ ( less ) WHILE Statement DO £¾ <statement> WHILE l <rel_expr> SWITCH Statement SWITCH <data> CASE <value 1> <statement 1> BREAK CASE <value 2> <statement 2> BREAK : : DEFAULT <statement 1> BREAK ENDS l 5.3.4 5-6 BREAK Statement Usage of Assembler ( greater ) £¼£½( less or equal ) £¾£½( greater or equal ) £½£½( equal ) £¡£½( not equal ) GMS 84512 / 84524 . [syntex] XASM8 < filename > [/option] Command Extension name (default : .ASM) Extension name (default : .ASM) /? Displays help messages /L- List file is not displayed /C- Error messages are not dipalyed [example] XASM8 TEST.ASM [Output files] TEST.OB2 : Object file for OTP file TEST.OBJ : Object file for HEX file TEST.LST : List file 5-7 GMS 84512 / 84524 5.4 LINKER { Ref. GMS800 SERIES MDS MANUAL } LINKER is a S/W that creates executable machine code from one or more object programs. G8MC Linker generates Motorola S-Format. Object Program 1 .HEX file Object Program 2 .MAP file LINKER .. 5.4.1 Object Program n .SYM file Font file ( *.HL ) .OTP file Usage of Linker [syntex] XLINK8 < filename 1> ... <filename n> Command Extension name (default : . OBJ) Extension name (default : . OBJ) [/option] /? Displays help messages /M- .MAP file is not created /S- .SYM file is not created /CPU=<CPU_TYPE>Declaration targetMCU ROM size /F Specify font file name [example] XLINK8 5-8 filename1 filename2 /F font.HL /CPU=84512 GMS 84512 / 84524 5.5 FONT EDITOR { Ref. GMS800 SERIES MDS MANUAL } G8MC Font editor is OSD font editor for GMS84512. MS-Windows version is supported. Executable file name : FED8.EXE l OUTPUT FILES ¨ç £ª.DAT : Data file for Font Editor ¨è £ª.HL : Hexa file for OTP ( It is converted to otp file by link ) ¨é £ª.HI : Font hexa file for emulator upper bits ¨ê £ª.LO : Font hexa file for emulator lower bits ¡ØNotice : OTP file must be converted from *.HL file by XLINK8 using by /F option. 0 1 2 3 4 5 6 7 X:03 Y: 03 (DECIMAL) LEFT 00 Index 08 13 10 RIGHT UP °¡ 18 20 28 DOWN REVERSE 30 38 40 CLEAR 48 50 COPY FROM UNDO 58 60 68 70 78 One Character Map ( 14¡¿ 18 ) Edit Menu Character Set ( 128 Characters ) 5-9 GMS 84512 / 84524 5.6 OTP Socket Adapter ( GMS84512/24 OTP-AD ) GMS84512T/84524T is equivalent with GMS84512/84524, and it include programmable ROM. PROM writer socket adapter FONT Switch 52 SDIP SOCKET PROM TTL GMS84512/24 OTP-AD FIG.5.6.1 5 - 10 Top view of socker adapter GMS 84512 / 84524 5.6.1 OTP CHIP WRITING METHOD 1. Programming Voltage (Vpp ) is 12.5 V 2. If you write FONT ROM, then set the switch to FONT. 3. And if you write program ROM, then set the switch to PROM. 4. You must use OTP file not HEX file. 5. You must set EPROM type to 27C256 in PROM writer. 6. You must program OTP chip two times. Because FONT ROM and Program ROM are internally separated. PROM WRITER BUFFER ( RAM ) FONT 0000H ( 8 K bytes ) 1FEFH 0000H ( 8 K bytes ) GMS84512T/84524T 2000H ( 8 K bytes ) 1FEFH 3FEFH 2000H 2000H A000H ( GMS84524 ) ( GMS84524 ) ( GMS84524 ) 5000H 5000H D000H ( GMS84512 ) ( GMS84512 ) ( GMS84512 ) 7FFFH 7FFFH FFFFH Set switch to FONT User Program OTP File l Set switch to PROM ¡ØBuffer data will be write into GMS84512T at different address area by socket adapter. Cautionary notes. For chip reliability, after write & aging, reading test is recommended. 5 - 11 GMS84512/84524 USER’S MANUAL Table of Contents 1. Overview 2. CPU 3. Peripheral Function 4. Control Function 5. Support Tool 6. Appendix GMS 84512 / 84524 1.ABSOULTE MAXIMUM RATINGS ( Ta = 25¡É ) NO. Parameter Symbol Unit Ratings etc. Vdd £Ö -0.3¡-6.0 £Ö -0.3¡-9.0 1 Supply Voltage 2 Input NMOS OPEN DRAIN Vin1 Voltage etc. Vin2 Output 1 PORT PEAK Ipeak §Ì MAX. ¦¢10¦¢ Current TOTAL ¥ÒI avg §Ì MAX. ¦¢50¦¢ 3 -0.3¡-Vdd+0.3 4 Operating temeperature Topr ¡É -10¡-70 5 Starage Temperature Tstg ¡É -40¡-125 2. DC CHARACTERISTICS ( ¥° ) ( Vss = 0£Ö, Ta = -10¡-70¡É, f (Xin) = 4 MHz ) SPECIFICATION NO. 1 2 Parameter Supply Voltage Supply Voltage Symbol Unit Vdd £Ö Idd mA Test Conditions f(XIN) =4 MHz, etc. MIN. TYP. MAX. 4.5 5 5.5 10 20 10 300 RESET state 3 Supply Current in Stop Mode Istop §Ë Input = Vss *1 *1 : When port output current do not sink or source. A-1 GMS 84512 / 84524 3. DC CHARACTERISTICS ( ¥± ) ( Vdd = 5 V¡¾10%,Vss = 0£Ö, Ta = -10¡-70¡É,f (Xin) = 4 §Ö ) NO. 1 2 3 Parameter Pin Symbol Unit 'H’ Input RESET, TEST, Xin, Schmitt *1 Input Voltage Other Port *2 ‘L’ Input RESET, TEST, Xin, Schmitt *1 Input Voltage Other Port *2 'H’ Input All input pins Iih §Ë All input pins Iil §Ë Schmitt *1 Input Vt+ £Ö RESET Vt- 'H’ Output R0, R10¡-R16, R2, Voh Voltage R33¡-R35, R5 ‘L’ Output R0, R10¡-R16, R2, Voltage R32¡-R37, R4, R5 RAM DATA Vdd Vih Test Condition £Ö Specification Min. Typ. Etc. Max. 0.8 Vdd Vdd 0.7 Vdd 0 Vdd 0.12 Vdd £Ö 0 0.3 Vdd Vi = Vdd -5.0 5.0 Vi = Vss -5.0 5.0 0.3 1.0 0.2 0.7 Current 4 ‘L’ Input Current 5 6 7 8 Hysteresis Vol £Ö Ioh = -5 §Ì Ref. Fig. A.1 £Ö Iol = 5 §Ì Vram £Ö At Clock RETENSION *1 . Schmitt Input : Fig. A.1 Vdd -1 Ref. 1.0 2.0 Stop EC3, EC2, Sin, Sclk, INT1¡-INT3, HD, VD *2. Other Ports : R0, R1, R2, R3 ROOM HOT ( 75¡É) 1.0V 1.0V SPEC. SPEC. 0.8 0.8 Vdd - Voh 0.6 Vol 0.4 0.6 0.4 0.2 0.2 0 0 0 2 4 6 8 10§Ì 0 -2 Iol Fig. A.1 A-2 COLD ( -10¡É) PORT Output Characteristics ( @ Vdd = 5 V ) -4 -6 Ioh -8 - 10§Ì GMS 84512 / 84524 4. A/D COMPARATOR CHARACTERISTICS ( Vdd = 5 V¡¾10%,Vss = 0£Ö, Ta = -10¡-70¡É,f (Xin) = 4 §Ö ) NO. Parameter Pin Symbol SPECIFICATION Unit MIN. 1 Analog input voltage rage Cin0¡-Cin3 2 Accuracy VAIN V TYP. Vss etc. MAX. Vdd ¡¾ 1 LSB 5. AC CHARACTERISTICS 5.1 Input Conditions ( MAIN CLOCK, RESET, INT, EC, OSD CLOCK, VD, HD ) ( Vdd = 5 V¡¾10%,Vss = 0£Ö, Ta = -10¡-70¡É,f (Xin) = 4 §Ö ) NO. Parameter Pin Symbol Unit SPECIFICATION MIN. TYP. MAX. fcp MHz 3 4 5 tsys ns 400 500 667 Xin, Xout tST ms External Clock Pulse Width Xin tcpw ns 80 5 External Clock Transition Timer Xin trcp, tfcp ns 20 6 Interrupt Pulse Width INT1~INT3 tIW tsys 2 8 ‘L’ Reset Input Pulse RESET Width tRST tsys 8 9 Event Counter Pulse Width EC2, EC3 tECW tsys 2 10 Event Counter Transition Timer EC2, EC3 trEC, tfEC ns 20 11 Osd Clock Frequency OSC1, OSC2 f OSD MHz 4 12 V-sync Pulse Width VD tVDW §Á 2 13 H-sync Pulse Width HD tHDW § 2 1 Main Clock Frequency 2 System Clock Cycle 3 Oscillation Stable Time 4 Xin etc. 20 6 8 L-C Oscillator ¡ØFig. A-2 Ref. A-3 GMS 84512 / 84524 5.2 SERIAL TRANSFER ( Vdd = 5 V¡¾10%,Vss = 0£Ö, Ta = -10¡-70¡É,f (Xin) = 4 §Ö ) NO. Parameter Pin Symbol Unit Test Condition SPECIFICATION MIN. 1 tscyc §À 2tsys+ 200 Sclk tsck §À tsys +70 Sclk trsck, tfsck §À 30 Sin trsin, tfsin §À 30 Serial Input Data Set-Up Time Sin tsus §À Serial Input Data Sin ths Sclk Serial Input Clock Pulse Width 3 Serial Input Clock Transition Time 4 Serial Input Data Transition Time 5 6 External Sclk 100 Internal Sclk 200 §À External Sclk tsys +100 tscyc §À LOAD = 50 §Ü 4tsys Sclk tsck §À Sclk trsck, tfsck §À 30 Sout tds §À 100 Hold Time 7 Serial Output Clock Cycle 8 Serial Output Clock Pulse Width 9 Serial Output Transition Time 10 Serial Output Data Delay Time ¡ØFig. A-3 Ref. A-4 MAX. Sclk Serial Input Clock Cycle 2 TYP. 16 tsys 2tsys 30 etc. GMS 84512 / 84524 1/fcp tcpw tcpw Vdd-0.5V 0.5 V Xin tcpw INT1 INT2 INT3 tcpw tIW tIW 0.8 Vdd 0.2 Vdd tRST RESET 0.2 Vdd tECW tECW EC2 0.8 Vdd 0.8 Vdd 0.2 Vdd EC3 trEC tfEC tVDW, tHDW VD 0.2 Vdd HD Fig. A.2 CLOCK, INT, RESET, EC, VD, HD Input Timing tscyc tfsck Sclk trsck tsckW tsckW 0.8 Vdd 0.2 Vdd tsus ths 0.2 Vdd 0.8 Vdd Sin tfsin trsin tds Sout Fig. A.3 0.2 Vdd 0.8 Vdd SERIAL I/O Timing A-5 GMS 84512 / 84524 GMS84512 PACKAGE OUTLINE ( 52-PIN SDIP ) 52LD S-SIP 600MIL [ UNIT : millimeters ] 52 27 0¡-15° 15.24 ± 0.25 13.97 ± 0.25 HME GMS84512 / 84524 1 26 0.25 ± 0.05 45.97 ± 0.13 52-PIN S-DIP PACKAGE DIMENSION 3.24 ± 0.20 A-6 A.4 1.778 ± 0.25 4.83 Max. Fig. 1.02 ± 0.25 0.50 Min. 0.47 ± 0.13 3.81 ± 0.13 0.76 ± 0.13 GMS84512T/24T PROGRAMMING MANUAL GMS84512T/GMS84524T EPROM PROGRAMMING 1. D E V I C E O V E R V I E W The GMS84512T/GMS84524T are high-performance CMOS 8-bit microcontroller with 12K/24K bytes of EPROM. The device is one of GMS800 family. The HYUNDAI GMS84512T/GMS8424T are powerful microcontroller which provides a highly flexible and cost effective solution to many embedded control applications. The GMS84512T/GMS84524T provides the following standard features: 12K/24K bytes of EPROM, 256 bytes of RAM, 42 I/O lines, 16-bit or 8-bit timer/counter, On Screen Display, 5-bit A/D comparotor, PWM, on-chip oscillator and clock circuitry. DEVICE NAME ROM SIZE GMS84512T 12K PROM GMS84524T 24K PROM 2. P I N C O N F I G U R A T I O N GMS84512T GMS84524T 2 GMS84512T/GMS84524T EPROM PROGRAMMING 52SDIP Package for GMS84512T/GMS84524T Pin No. 1 MCU Mode HD OTP Mode I (1) Pin No. MCU Mode OTP Mode I 27 VDD I VDD O 2 VD I (1) I 28 OSC2 O (3) 3 R45/PWM0 O (1) O 29 OSC1 I (1) I 4 R44/PWM1 O (1) O 30 RESET I (1) I 5 R43/PWM2 O (1) O 31 R21 I/O A9 I 6 R42/PWM3 O (1) O 32 R20 I/O A8 I 7 R41/PWM4 O (1) O 33 R17/Cin0/INT3 I A7 I 8 R40/PWM5 O (1) O 34 R16/Cin2 I/O A6 I 9 R37/PWM6 I/O (1) I 35 R15/Cin1 I/O A5 I 10 R36/PWM7 I/O (1) I 36 R14 I/O A4 I 11 R35/Sin/Cin3 I/O A15 I 37 R13 I/O A3 I 12 R34/Sclk I/O A14 I 38 R12 I/O A2 I 13 R33/Sout I/O (1) I 39 R11 I/O A1 I 14 R32/PWM8 I/O (1) I 40 R10 I/O A0 I 15 R31/INT2 I (2) I 41 R07 I/O O7 I/O 16 R30/INT1 I (2) I 42 R06 I/O O6 I/O 17 R27/EC3 I/O CE I 43 R05 I/O O5 I/O 18 R26/EC2 I/O OE I 44 R04 I/O O4 I/O 19 R25/T2048 I/O A13 I 45 R03 I/O O3 I/O 20 R24 I/O A12 I 46 R02 I/O O2 I/O 21 R23 I/O A11 I 47 R01 I/O O1 I/O I/O 22 R22 I/O A10 I 48 R00 I/O O0 23 TEST I VPP - 49 R53/Y O (1) O 24 X IN I (1) I 50 R52/B O (2) O 25 XOUT O (3) O 51 R51/G O (2) O 26 VSS I VSS - 52 R50/R O (2) O NOTES: (1) These pins must be connected to V SS , because these pins are input ports during programming, program verify and reading (2) These pins must be connected to V D D . (3) X O U T pin must be opened during programming. 3 I/O: Input/Output Pin I: Input Pin O: Output Pin GMS84512T/GMS84524T EPROM PROGRAMMING 3. P I N F U N C T I O N ( O T P M o d e ) V PP (Program Voltage) V P P is the input for the program voltage for programming the EPROM. CE ( Chip Enable) CE is the input for programming and verifying internal EPROM. OE (Output Enable) OE is the input of data output control signal for verify. A 0 ~A 15 (Address Bus) A 0 ~A 15 are address input pins for internal EPROM. O 0 ~O 7 (EPROM Data Bus) These are data bus for internal EPROM. 4 GMS84512T/GMS84524T EPROM PROGRAMMING 4. P R O G R A M M I N G The GMS84512T/GMS84524T has two address ranges, Font area and PGM area. Therefore, the programmer should be program twice, each Font and PGM. 4.1 GMS84512T Programming The Font address ranges are from 0000 H to 1FF1 H and PGM addres ranges are from 5000 H to 7FFF H in OTP file. Firstly, the programmer program the Font data into the GMS84512T OTP device ( from 2000 H to 3FF1 H ), and then program the PGM data into the GMS84512T OTP device ( from D000 H to FFFF H ). When the programmer write the Font data 0000 H to 1FF1 H , consequently, the data actually will be written into address 2000 H to 3FF1 H of the GMS84512T OTP device. And PGM data 5000 H to 7FFF H , consequently, the data actually will be written into address D000 H to FFFF H of the GMS84512T OTP device. 1. The data format to be programmed is made up of Motorola S1 format. Ex) "Motorola S1" format; S00800006D633634615C S1130800FFFFFCF0E3E7E7E7E7E7E7E7E7E3F0FC10 S1051800FFFFE4 S1130000FFFF9F87E3F3F3F3F3F3F3F3F3E3879F44 : S1051FF0FFBF2D S11307F0FEFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF06 S10517F0FFFEF6 S12250009FE1C0711B003F1B003E1B043D1BF83C1B213B1BD13A1B00391B63381BC037C5 S123501F1BF0361B011B1BFB1A1B40053BFF1A061A2F1A2E1B232D1B922C1B8F2B1B002A1C : S1217FE02001200120012001200120012001E6012001DA021803BB0320010A1420017B S1057FFEFF2F4F S9030000FC FONT 0000 H ~ 1FF1 H PGM 5000 H ~ 7FFF H 2. Down load above data into programmer from PC. 3. Programming the data from address 0000 H to 1FF1 H and 5000 H to 7FFF H into OTP MCU, the data must be turned over respectively, and then record the data. Ex) 00 →FF, 76 →89, FF →00 etc. 4. Of course, the check sum is result of the sum of whole data from address 0000 H to 7FFF H in the file (not reverse data of OTP MCU). Caution : In the OTP file, data FF H , BF H are written in 1FF0 H and 1FF1 H respectively. However, the OTP chip was written already 49 H , 63 H in that addresses. Therefore, that addresses should be skipped in programming or blank check. And should be treated FF H , BF H in checksum calculation ( READ or VERIFY). On the checksum calculation, not used area data should be regarded as FF H in OTP file . When GMS84512T shipped, the blank data of GMS84512T is initially 00 H (not FF H ). 5 GMS84512T/GMS84524T EPROM PROGRAMMING Programming Flow File Type: Motorola S-format Address GMS84512T x x x x x x x x . O T P Address 0000 H FONT 1FF1 H Not Used 2000 H FONT 3FF1 H Program Verify Reading Down Loading Not Used Universal Programmer 5000 H Not Used PGM D000 H 7FFF H PGM FFFF H Programming Example Programmer Buffer GMS84512T device Data 00 00 60 : : 49 63 : : 00 00 : 60 1E : 00 D0 Data Address 2000 H 2001 H 2002 H : : 3FF0H 3 F F 1 H (1) : : 4000 H 4001 H : A000 H A001 H : FFFE H FFFF H Address FF FF 9F : : FF BF : : FF FF : 9F E1 : FF 2F Program Reading Verify 0000 H 0001 H 0002 H : : 1FF0H Down (1) 1FF1H Loading : : 4000 H 4001 H : Up 5000 H Loading 5001 H : 7FFE H 7FFF H File xxxxxxxx.OTP Data FF FF 9F : : FF BF : : FF FF : 9F E1 : FF 2F Address 0000 H 0001 H 0002 H : : 1FF0H (1) 1FF1H : : 4000 H 4001 H : 5000 H 5001 H : 7FFE H 7FFF H Checksum = FF+FF+9F+ ⋅ ⋅ ⋅ + F F + B F + ⋅ ⋅ ⋅ +FF+FF+ ⋅ ⋅ ⋅ +9F+E1+ ⋅ ⋅ ⋅ +FF+2F (1) 6 GMS84512T/GMS84524T EPROM PROGRAMMING 4.2 GMS84524T Programming The Font address ranges are from 0000 H to 1FF1 H and PGM addres ranges are from 2000 H to 7FFF H in OTP file. Firstly, the programmer program the Font data into the GMS84524T OTP device ( from 2000 H to 3FF1 H ), and then program the PGM data into the GMS84524T OTP device ( from A000 H to FFFF H ). When the programmer write the Font data 0000 H to 1FF1 H , consequently, the data actually will be written into address 2000 H to 3FF1 H of the GMS84524T OTP device. And PGM data 2000 H to 7FFF H , consequently, the data actually will be written into address A000 H to FFFF H of the GMS84524T OTP device. 1. The data format to be programmed is made up of Motorola S1 format. Ex) "Motorola S1" format; S00700006D61696E53 S1130800FFFFFCF0E3E7E7E7E7E7E7E7E7E3F0FC10 S1051800FFFFE4 S1130000FFFF9F87E3F3F3F3F3F3F3F3F3E3879F44 : : S1130FF0BFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF3D S1051FF0FFBF2D S12220009FE1C0711B003F1B003E1B183D1B803C1B283B1BD33A1B00391B63381BFF3711 S123201F1BF0361BFC1B1BFB1A1B40051B0F061BFF433A415B00BA4A8FE9BBE72FED3A4083 : : S1217FE0670B670B670BFF5F670B670B670BCE0C670BFA0BB30BA00D670B991F670B1D S1057FFEFF5F1F S9030000FC FONT 0000 H ~ 1FF1 H PGM 2000 H ~ 7FFF H 2. Down load above data into programmer from PC. 3. Programming the data from address 0000 H to 1FF1 H and 2000 H to 7FFF H into OTP MCU, the data must be turned over respectively, and then record the data. Ex) 00 →FF, 76 →89, FF →00 etc. 4. Of course, the check sum is result of the sum of whole data from address 0000 H to 7FFF H in the file (not reverse data of OTP MCU). Caution : In the OTP file, data FF H , BF H are written in 1FF0 H and 1FF1 H respectively. However, the OTP chip was written already 49 H , 63 H in that addresses. Therefore, that addresses should be skipped in programming or blank check. And should be treated FF H , BF H in checksum calculation ( READ or VERIFY). On the checksum calculation, not used area data should be regarded as FF H in OTP file . When GMS84524T shipped, the blank data of GMS84524T is initially 00 H (not FF H ). 7 GMS84512T/GMS84524T EPROM PROGRAMMING Programming Flow File Type: Motorola S-format Address GMS84524T x x x x x x x x . O T P Address 0000 H FONT 1FF1 H Not Used 2000 H FONT 3FF1 H Program Verify Reading 2000 H Down Loading Universal Programmer Not Used PGM A000 H 7FFF H PGM FFFF H Programming Example Data 00 00 60 : : 49 63 : 60 1E 3F 8E : : 00 A0 Data Address 2000 H 2001 H 2002 H : : 3FF0H (1) 3FF1H : A000 H A001 H A002 H A003 H : : FFFE H FFFF H File xxxxxxxx.OTP Programmer Buffer GMS84524T device Program Reading Verify Address Data Address FF FF 9F : : FF BF 0000 H 0001 H 0002 H : : Down 1FF0H (1) Loading 1FF1H FF FF 9F : : FF BF 0000 H 0001 H 0002 H : : 1FF0H (1) 1FF1H 9F E1 C0 71 : : FF 5F 2000 H 2001 H 2002 H 2003 H : : 7FFE H 7FFF H 9F E1 C0 71 : : FF 5F 2000 H 2001 H 2002 H 2003 H : : 7FFE H 7FFF H Up Loading Checksum = FF+FF+9F+ ⋅ ⋅ ⋅ + F F + B F +9F+E1+C0+71+ ⋅ ⋅ ⋅ +FF+5F (1) 8 GMS84512T/GMS84524T EPROM PROGRAMMING 5. D E V I C E O P E R A T I O N M O D E (T A = 25 °C ± 5 °C) Mode Read CE OE A 0~ A 15 V PP VDD O 0~ O 7 X VDD 5.0V DOUT X Output Disable V IH V IH X VDD 5.0V Hi-Z Programming V IL V IH X V PP VDD D IN X V PP VDD DOUT Program Verify X NOTES: 1. X = Either V IL or V IH 2. See DC Characteristics Table for V D D and V P P voltages during programming. 6. D C C H A R A C T E R I S T I C S (V S S =0 V, T A = 25 °C ± 5 °C) Symbol Item Min Typ Max Unit VPP Intelligent Programming 12.0 - 13.0 V V D D (1) Intelligent Programming 5.75 - 6.25 V I P P (2) V PP supply current 50 mA I D D (2) V D D supply current 30 mA V IH Input high voltage V IL Input low voltage V OH Output high voltage VOL Output low voltage I IL 0.8 V D D V D D -1.0 V V I O H = -2.5 mA 0.4 V I OL = 2.1 mA 5 uA NOTES: 1. V D D must be applied simultaneously or before V PP and removed simultaneously or after V P P . 2. The maximum current value is with outputs O 0 to O 7 unloaded. 9 C E =V IL V 0.2 V D D Input leakage current Test condition GMS84512T/GMS84524T EPROM PROGRAMMING SWITCHING WAVEFORMS WAVEFORM INPUTS OUTPUTS Must be steady W ill be steady May change from H to L W ill be changing from H to L May change from L to H W ill be changing from L to H Do not care any change permitted Changing state unknown Does not apply Center line is high impedance "Off" state READING WAVEFORMS V IH Addresses Address Valid V IL V IH (2) OE V IL t AS tO E tD H V IH High-Z Output Valid Output V IL NOTES: 1. The input timing reference level is 1.0 V for a V IL and 4.0V for a V IH at V D D =5.0V 2. To read the output data, transition requires on the O E from the high to the low after address setup time t A S . 10 GMS84512T/GMS84524T EPROM PROGRAMMING PROGRAMMING ALGORITHM WAVEFORMS Program Verify Program V IH Addresses Address Stable V IL tA S tA H V IH Data High-Z Data In Stable V IL Data out Valid tD H tD S 12.5V VPP V DD tV P S 6.0V VDD 5.0V tV D S V IH CE V IL tO E S tP W tO E V IH OE V IL tO P W NOTES: 1. The input timing reference level is 1.0 V for a V IL and 4.0V for a V IH at V D D =5.0V 11 tD F P GMS84512T/GMS84524T EPROM PROGRAMMING 7. A C R E A D I N G C H A R A C T E R I S T I C S (V S S =0 V, T A = 25 °C ± 5 °C) Symbol Item t AS Address setup time tO E Data output delay time tD H Data hold time Min Typ Max Unit 2 Test condition us 200 ns 0 ns NOTES: 1. V D D must be applied simultaneously or before V PP and removed simultaneously or after V P P . 8. A C P R O G R A M M I N G C H A R A C T E R I S T I C S (V S S =0 V, T A = 25 °C ± 5 °C; See DC Characteristics Table for V D D and V P P voltages.) Symbol t AS Item Min Typ Max Unit Address set-up time 2 us tO E S O E set-up time 2 us tD S Data setup time 2 us tA H Address hold time 0 us tD H Data hold time 1 us tD F P Output disable delay time 0 us tV P S V PP setup time 2 us tV D S V D D setup time 2 us tP W Program pulse width 0.95 CE pulse width when over programming 2.85 tO P W tO E 1.0 Data output delay time Condition* (Note 1) 1.05 ms Intelligent 78.75 ms (Note 2) 200 ns *AC CONDITIONS OF TEST Input Rise and Fall Times (10% to Input Pulse Levels . . . . . . . . Input Timing Reference Level . . Output Timing Reference Level . 90%) . . . . . . . . . . . . . . . . . . . . . 20 ns 0.45V to 4.55V 1.0V to 4.0V 1.0V to 4.0V NOTES: 1. V D D must be applied simultaneously or before V PP and removed simultaneously or after V P P . 2. The length of the overprogram pulse may vary from 2.85 msec to 78.75 msec as a function of the iteration counter value X (Intelligent Programming Algorithm only). Refer to page 13. 12 GMS84512T/GMS84524T EPROM PROGRAMMING Intelligent Programming Algorithm START ADDRESS= FIRST LOCATION V D D = 6.0V V PP = 12.5V X=0 PROGRAM ONE 1 ms PULSE INCREMENT X YES X = 25 ? NO FAIL VERIFY BYTE VERIFY ONE BYTE FAIL PASS PASS PROGRAM ONE PULSE OF 3X msec DURATION INCREMENT ADDRESS NO LAST ADDRESS ? YES V D D = V PP = 5.0V COMPARE ALL BYTES TO ORIGINAL DATA FAIL PASS DEVICE PASSED 13 DEVICE FAILED