CYPRESS CY7C1089DV33_12

CY7C1089DV33
64-Mbit (8 M × 8) Static RAM
Features
Functional Description
■
High speed
❐ tAA = 12 ns
The CY7C1089DV33 is a high-performance CMOS static RAM
organized as 8,388,608 words by 8 bits.
■
Low active power
❐ ICC = 300 mA at 12 ns
■
Low complementary metal oxide semiconductor (CMOS)
standby power
❐ ISB2 = 100 mA
To write to the device, take Chip Enables (CE1 LOW and CE2
HIGH) and Write Enable (WE) input LOW. Data on the eight I/O
pins (I/O0 through I/O7) is then written into the location specified
on the address pins (A0 through A22).
■
Operating voltages of 3.3 ± 0.3 V
■
2.0-V data retention
■
Automatic power-down when deselected
■
Transistor-transistor logic (TTL)-compatible inputs and outputs
■
Easy memory expansion with CE1 and CE2 features
■
Available in Pb-free 48-ball fine ball grid array (FBGA) package
To read from the device, take Chip Enables (CE1 LOW and CE2
HIGH) LOW and Output Enable (OE) LOW while forcing the
Write Enable (WE) HIGH. Under these conditions, the contents
of the memory location specified by the address pins appear on
the I/O pins. See Truth Table on page 9 for a complete
description of Read and Write modes.
The input and output pins (I/O0 through I/O7) are placed in a high
impedance state when the device is deselected (CE1 LOW or
CE2 HIGH), the outputs are disabled (OE HIGH), or during a
write operation (CE1 LOW, CE2 HIGH and WE LOW).
Logic Block Diagram
8M x 8
ARRAY
SENSE AMPS
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
ROW DECODER
INPUT BUFFER
I/O0 – I/O7
WE
COLUMN
DECODER
OE
A10
A11
A 12
A 13
A 14
A 15
A 16
A 17
A18
A19
A20
A21
A22
CE2
CE1
Selection Guide
Description
–12
Unit
Maximum access time
12
ns
Maximum operating current
300
mA
Maximum CMOS standby current
100
mA
Cypress Semiconductor Corporation
Document Number: 001-53993 Rev. *C
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised August 22, 2012
CY7C1089DV33
Contents
Pin Configuration ..............................................................3
Maximum Ratings .............................................................4
Operating Range ...............................................................4
DC Electrical Characteristics ...........................................4
Capacitance .......................................................................4
Thermal Resistance ..........................................................4
Data Retention Characteristics ........................................5
AC Switching Characteristics ..........................................6
Switching Waveforms .......................................................7
Truth Table ........................................................................9
Ordering Information ........................................................9
Ordering Code Definition .............................................9
Document Number: 001-53993 Rev. *C
Package Diagram ............................................................10
Acronyms ........................................................................10
Document Conventions .................................................10
Units of Measure .......................................................10
Document History Page .................................................11
Sales, Solutions, and Legal Information ......................11
Worldwide Sales and Design Support .......................11
Products ....................................................................11
PSoC Solutions .........................................................11
Page 2 of 11
CY7C1089DV33
Pin Configuration
Figure 1. 48-Ball FBGA (Top View) [1]
1
2
3
4
5
6
A22
OE
A0
A1
A2
CE2
A
NC
NC
A3
A4
CE1
NC
B
I/O0
NC
A5
A6
NC
I/O4
C
VSS
I/O1
A17
A7
I/O5
VCC
D
VCC
I/O2
A18
A16
I/O6
VSS
E
I/O3
NC
A14
A15
NC
I/O7
F
NC
A21
A12
A13
WE
NC
G
A19
A8
A9
A10
A11
A20
H
Note
1. NC pins are not connected to the die.
Document Number: 001-53993 Rev. *C
Page 3 of 11
CY7C1089DV33
Maximum Ratings
Exceeding maximum ratings may shorten the useful life of the
device. These user guidelines are not tested.
Current into outputs (LOW) ......................................... 20 mA
Static discharge voltage............................................ >2001 V
Storage temperature ................................ –65 C to +150 C
(MIL-STD-883, Method 3015)
Ambient temperature with
power applied ........................................... –55 C to +125 C
Latch up current....................................................... >140 mA
Supply voltage on VCC relative to GND[2] .....–0.5 V to +4.6 V
Operating Range
DC voltage applied to outputs
in high-Z state[2] ................................... –0.5 V to VCC + 0.5 V
Range
Ambient
Temperature
VCC
DC input voltage[2] ............................... –0.5 V to VCC + 0.5 V
Industrial
–40 C to +85 C
3.3V  0.3V
DC Electrical Characteristics
Over the Operating Range
Parameter
Description
Test Conditions
VOH
Output HIGH voltage
VCC = Min, IOH = –4.0 mA
VOL
Output LOW voltage
VCC = Min, IOL = 8.0 mA
–12
Unit
Min
Max
2.4
–
V
–
0.4
V
VIH
Input HIGH voltage
2.0
VCC + 0.3
V
VIL
Input LOW voltage[2]
–0.3
0.8
V
IIX
Input leakage current
GND < VIN < VCC
–1
+1
A
IOZ
Output leakage current
GND < VOUT < VCC, Output disabled
–1
+1
A
ICC
VCC operating supply current VCC = Max, f = fMAX = 1/tRC, IOUT = 0 mA CMOS levels
–
300
mA
ISB1
Automatic CE power-down
current — TTL inputs
Max VCC, CE1 > VIH, CE2 < VIL,
VIN > VIH or VIN < VIL, f = fMAX
–
120
mA
ISB2
Automatic CE power-down
current —CMOS inputs
Max VCC, CE1 > VCC – 0.3V, CE2 < 0.3V,
VIN > VCC – 0.3V, or VIN < 0.3V, f = 0
–
100
mA
Capacitance
Tested initially and after any design or process changes that may affect these parameters.
Parameter
Description
CIN
Input capacitance
COUT
I/O capacitance
Test Conditions
TA = 25 C, f = 1 MHz, VCC = 3.3 V
FBGA
Unit
32
pF
40
pF
FBGA
Unit
55
C/W
23.04
C/W
Thermal Resistance
Tested initially and after any design or process changes that may affect these parameters.
Parameter
Description
JA
Thermal resistance
(junction to ambient)
JC
Thermal resistance
(junction to case)
Test Conditions
Still air, soldered on a 3 × 4.5 inch,
four layer printed circuit board
Note
2. VIL (min) = –2.0V and VIH(max) = VCC + 2V for pulse durations of less than 20 ns.
Document Number: 001-53993 Rev. *C
Page 4 of 11
CY7C1089DV33
Figure 2. AC Test Loads and Waveforms[3]
High-Z characteristics
3.3 V
50
VTH = 1.5 V
OUTPUT
Z0 = 50
R1 317
OUTPUT
30 pF*
R2
351
5 pF*
(a)
* Capacitive load consists
of all components of the
test environment
ALL INPUT PULSES
INCLUDING
JIG AND
SCOPE
(b)
3.0 V
90%
90%
10%
GND
Rise Time > 1 V/ns
10%
(c)
Fall Time:
> 1 V/ns
Data Retention Characteristics
Over the Operating Range
Parameter
Description
Conditions
Min
Typ
Max
Unit
2
–
–
V
–
–
100
mA
VDR
VCC for data retention
ICCDR
Data retention current
tCDR[4]
Chip deselect to data retention time
0
–
–
ns
tR[ 5]
Operation recovery time
12
–
–
ns
VCC = 2 V, CE1 > VCC – 0.2 V, CE2 < 0.2 V,
VIN > VCC – 0.2 V or VIN < 0.2 V
Figure 3. Data Retention Waveform
DATA RETENTION MODE
3.0V
VCC
tCDR
VDR > 2V
3.0V
tR
CE1
CE2
Notes
3. Valid SRAM operation does not occur until the power supplies have reached the minimum operating VDD (3.0V). 100 s (tpower) after reaching the minimum operating
VDD, normal SRAM operation begins including reduction in VDD to the data retention (VCCDR, 2.0V) voltage.
4. Tested initially and after any design or process changes that may affect these parameters.
5. Full device operation requires linear VCC ramp from VDR to VCC(min.) > 50 s or stable at VCC(min.) > 50 s.
Document Number: 001-53993 Rev. *C
Page 5 of 11
CY7C1089DV33
AC Switching Characteristics
Over the Operating Range [6]
Parameter
–12
Description
Min
Max
Unit
Read Cycle
tpower
VCC(typical) to the first access[7]
100
–
s
tRC
Read cycle time
12
–
ns
tAA
Address to data valid
–
12
ns
tOHA
Data hold from address change
3
–
ns
tACE
CE1 LOW and CE2 HIGH to data valid
–
12
ns
tDOE
OE LOW to data valid
–
7
ns
tLZOE
OE LOW to low-Z
1
–
ns
tHZOE
OE HIGH to high-Z [8]
–
7
ns
3
–
ns
–
7
ns
tLZCE
tHZCE
CE1 LOW and CE2 HIGH to low-Z
[8]
CE1 HIGH and CE2 LOW to high-Z
[8]
[9]
tPU
CE1 LOW and CE2 HIGH to power-up
0
–
ns
tPD
CE1 HIGH and CE2 LOW to power-down [9]
–
12
ns
tWC
Write cycle time
12
–
ns
Write Cycle [10, 11]
tSCE
CE1 LOW and CE2 HIGH to write end
9
–
ns
tAW
Address setup to write end
9
–
ns
tHA
Address hold from write end
0
–
ns
tSA
Address setup to write start
0
–
ns
tPWE
WE pulse width
9
–
ns
tSD
Data setup to write end
7
–
ns
tHD
Data hold from write end
tLZWE
tHZWE
0
–
ns
WE HIGH to
low-Z[8]
3
–
ns
WE LOW to
high-Z[8]
–
7
ns
Notes
6. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, and input pulse levels of 0 to 3.0V. Test conditions for the read cycle use output
loading shown in part a) of AC Test Loads and Waveforms[3], unless specified otherwise.
7. tPOWER gives the minimum amount of time that the power supply is at typical VCC values until the first memory access is performed.
8. tHZOE, tHZCE, tHZWE, tLZOE, tLZCE, and tLZWE are specified with a load capacitance of 5 pF as in (b) of AC Test Loads and Waveforms[3].
9. These parameters are guaranteed by design and are not tested.
10. The internal write time of the memory is defined by the overlap of WE, CE1 = VIL, and CE2 = VIH. Chip enables must be active and WE must be LOW to initiate a write,
and the transition of any of these signals can terminate. The input data setup and hold timing should be referenced to the edge of the signal that terminates the write.
11. The minimum write cycle time for Write Cycle No. 2 (WE controlled, OE LOW) is the sum of tHZWE and tSD.
Document Number: 001-53993 Rev. *C
Page 6 of 11
CY7C1089DV33
Switching Waveforms
Figure 4. Read Cycle No. 1 [12, 13, 14]
tRC
RC
ADDRESS
tAA
tOHA
DATA I/O
PREVIOUS DATA VALID
DATAOUT VALID
Figure 5. Read Cycle No. 2 (OE Controlled) [12, 14, 15]
tRC
ADDRESS
CE
tACE
OE
tHZOE
tDOE
tHZCE
tLZOE
DATA I/O
HIGH IMPEDANCE
tLZCE
VCC
SUPPLY
CURRENT
HIGH
IMPEDANCE
DATAOUT VALID
tPD
tPU
50%
ICC
50%
ISB
Notes
12. CE refers to the internal logical combination of CE1 and CE2 such that when CE1 is LOW and CE2 is HIGH, CE is LOW. For all other combinations, CE is HIGH.
13. The device is continuously selected. CE = VIL.
14. WE is HIGH for read cycle.
15. Address valid before or similar to CE transition LOW.
Document Number: 001-53993 Rev. *C
Page 7 of 11
CY7C1089DV33
Switching Waveforms
(continued)
Figure 6. Write Cycle No. 1 (CE Controlled) [16, 17, 18]
tWC
ADDRESS
tSA
tSCE
CE
tAW
tHA
tPWE
WE
tSD
tHD
DATAIN VALID
DATA I/O
Figure 7. Write Cycle No. 2 (WE Controlled, OE LOW) [16, 17, 18]
tWC
ADDRESS
tSCE
CE
tAW
tHA
tSA
tPWE
WE
tHZWE
DATA I/O
tSD
tHD
DATAIN VALID
tLZWE
Notes
16. CE refers to the internal logical combination of CE1 and CE2 such that when CE1 is LOW and CE2 is HIGH, CE is LOW. For all other combinations, CE is HIGH.
17. Data I/O is high impedance if OE = VIH.
18. If CE goes HIGH simultaneously with WE going HIGH, the output remains in a high impedance state.
Document Number: 001-53993 Rev. *C
Page 8 of 11
CY7C1089DV33
Truth Table
CE1
CE2
OE
WE
I/O0 – I/O7
Mode
Power
H
X
X
X
High-Z
Power down
Standby (ISB)
X
L
X
X
High-Z
Power down
Standby (ISB)
L
H
L
H
Data Out
Read all bits
Active (ICC)
L
H
X
L
Data In
Write all bits
Active (ICC)
L
H
H
H
High-Z
Selected, Outputs disabled
Active (ICC)
Ordering Information
Speed
(ns)
12
Ordering Code
CY7C1089DV33-12BAXI
Package
Diagram
001-50044
Package Type
48-ball FBGA (8 × 9.5 × 1.4 mm) (Pb-free)
Operating
Range
Industrial
Ordering Code Definition
CY 7 C 1 08 9
D V33 - xx xxx x
Temperature Range: x = I
I = Industrial
Package Type: xxx = BAX
BAX = 48-ball FBGA (Pb-free)
Speed: xx = 12 ns
V33 = Voltage range (3 V to 3.6 V)
D = C9, 90 nm Technology
9 = Data width × 8 bits
08 = 64-Mbit density
1 = Fast Asynchronous SRAM family
Technology Code: C = CMOS
7 = SRAM
CY = Cypress
Document Number: 001-53993 Rev. *C
Page 9 of 11
CY7C1089DV33
Package Diagram
Figure 8. 48-Ball FBGA (8 x 9.5 x 1.4 mm) (001-50044)
001-50044 *C
Acronyms
Document Conventions
Description
Units of Measure
CMOS
complementary metal oxide semiconductor
Symbol
FBGA
fine ball grid array
°C
degrees Celsius
I/O
input/output
A
microampere
SRAM
static random access memory
mA
milliampere
TTL
transistor-transistor logic
MHz
megahertz
ns
nanosecond
pF
picofarad
V
volt

ohm
W
watt
Acronym
Document Number: 001-53993 Rev. *C
Unit of Measure
Page 10 of 11
CY7C1089DV33
Document History Page
Document Title: CY7C1089DV33, 64-Mbit (8 M × 8) Static RAM
Document Number: 001-53993
Revision
ECN
Submission
Date
Orig. of
Change
**
2746867
07/31/2009
*A
3100499
12/02/2010
PRAS
*B
3178259
21/02/2011
PRAS
Post to external web.
*C
3720118
08/22/2012
TAVA
Minor Text edits.
Description of Change
VKN/AESA New Data sheet
Updated Note 12.
Changed datasheet status from Preliminary to Final.
Updated Package Diagram and Sales, Solutions, and Legal Information.
Added Acronyms, Document Conventions and Ordering Code Definition.
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© Cypress Semiconductor Corporation, 2009-2012. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of
any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for
medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as
critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems
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Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign),
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and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress
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the express written permission of Cypress.
Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not
assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where
a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer
assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Use may be limited by and subject to the applicable Cypress software license agreement.
Document Number: 001-53993 Rev. *C
Revised August 22, 2012
All products and company names mentioned in this document may be the trademarks of their respective holders.
Page 11 of 11