WS512K32V-XXX HI-RELIABILITY PRODUCT 512Kx32 SRAM 3.3V MODULE ADVANCED* FEATURES ■ Access Times of 70, 85, 100, 120ns ■ Low Voltage • 3.3V ±10% Power Supply ■ Packaging ■ Low Power CMOS • 66-pin, PGA Type, 1.185 inch square, Hermetic Ceramic HIP (Package 401) ■ Built-in Decoupling Caps and Multiple Ground Pins for Low Noise Operation • 68 lead, Hermetic CQFP (G2T), 22.4mm (0.880 inch) square 4.57mm (0.180 inch) high (Package 509). Designed to fit JEDEC 68 lead 0.990" CQFJ footprint. ■ Weight WS512K32V-XG2TX - 8 grams typical WS512K32V-XHX - 13 grams typical ■ Organized as 512Kx32, User Configurable as 1024Kx16 or 2Mx8 * This data sheet describes a product that may or may not be under development and is subject to change or cancellation without notice. ■ Commercial, Industrial and Military Temperature Ranges ■ TTL Compatible Inputs and Outputs FIG. 1 PIN CONFIGURATION FOR WS512K32V-XHX PIN DESCRIPTION TOP VIEW 1 12 23 34 45 56 I/O8 WE2 I/O15 I/O24 VCC I/O31 I/O9 CS2 I/O14 I/O25 CS4 I/O30 I/O10 GND I/O13 I/O26 WE4 I/O29 A13 I/O11 I/O12 A6 I/O27 I/O28 A14 A10 OE A7 A3 A0 A15 A11 A18 NC A4 A1 A16 A12 WE1 A8 A5 A2 A17 VCC I/O7 A9 WE3 I/O23 I/O0 CS1 I/O6 I/O16 CS3 I/O22 I/O1 NC I/O5 I/O17 GND I/O21 I/O4 I/O18 I/O3 I/O2 I/O19 I/O0-31 A0-18 WE1-4 CS1-4 OE VCC GND NC BLOCK DIAGRAM W E1 CS1 22 33 44 512K x 8 W E3 CS3 W E4 CS4 512K x 8 512K x 8 512K x 8 I/O20 55 8 8 8 66 I/O0-7 February 2000 Rev. 2 W E2 CS2 OE A0-18 8 11 Data Inputs/Outputs Address Inputs Write Enables Chip Selects Output Enable Power Supply Ground Not Connected 1 I/O8-15 I/O16-23 I/O24-31 White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com WS512K32V-XXX FIG. 2 PIN CONFIGURATION FOR WS512K32V-XG2TX PIN DESCRIPTION NC A0 A1 A2 A3 A4 A5 CS3 GND CS4 WE1 A6 A7 A8 A9 A10 VCC TOP VIEW I/O0-31 A0-18 WE1-4 CS1-4 OE VCC GND NC 9 8 7 6 5 4 3 2 1 68 67 66 65 64 63 62 61 I/O0 I/O1 I/O2 I/O3 I/O4 I/O5 I/O6 I/O7 GND I/O8 I/O9 I/O10 I/O11 I/O12 I/O13 I/O14 I/O15 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 I/O16 I/O17 I/O18 I/O19 I/O20 I/O21 I/O22 I/O23 GND I/O24 I/O25 I/O26 I/O27 I/O28 I/O29 I/O30 I/O31 0.940" The WEDC 68 lead G2T CQFP fills the same fit and function as the JEDEC 68 lead CQFJ or 68 PLCC. But the G2T has the TCE and lead inspection advantage of the CQFP form. BLOCK DIAGRAM W E1 CS1 W E2 CS2 W E3 CS3 W E4 CS4 OE A0-18 OE CS2 A17 WE2 WE3 WE4 A18 NC NC A16 CS1 A15 A14 A13 A12 A11 VCC 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 512K x 8 8 I/O0-7 White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com Data Inputs/Outputs Address Inputs Write Enables Chip Selects Output Enable Power Supply Ground Not Connected 2 512K x 8 8 I/O8-15 512K x 8 8 I/O16-23 512K x 8 8 I/O24-31 WS512K32V-XXX TRUTH TABLE ABSOLUTE MAXIMUM RATINGS Parameter Symbol Min Max Unit CS OE WE Mode Data I/O Power TA -55 +125 °C °C H L L L X L H X X H H L Standby Read Out Disable Write High Z Data Out High Z Data In Standby Active Active Active Operating Temperature TSTG -65 +150 Signal Voltage Relative to GND VG -0.5 Vcc+0.5 V Junction Temperature TJ 150 °C 4.0 V Storage Temperature Supply Voltage VCC -0.5 CAPACITANCE (TA = +25°C) RECOMMENDED OPERATING CONDITIONS Parameter Parameter Symbol Conditions Symbol Min Max Unit OE Capacitance COE VIN = 0 V, f = 1.0 MHz Supply Voltage VCC 3.0 3.6 V CWE VIN = 0 V, f = 1.0 MHz Input High Voltage VIH 2.2 V CC + 0.3 V Input Low Voltage VIL -0.5 +0.8 V WE Capacitance HIP (PGA) CQFP G2T Operating Temp (Mil) TA -55 +125 °C Max Unit 50 pF pF 20 15 CS Capacitance CCS VIN = 0 V, f = 1.0 MHz 20 pF Data I/O Capacitance CI/O VI/O = 0 V, f = 1.0 MHz 20 pF Address Input Capacitance CAD VIN = 0 V, f = 1.0 MHz 50 pF This parameter is guaranteed by design but not tested. DC CHARACTERISTICS (VCC = 3.3V, VSS = 0V, TA = -55°C to +125°C) Parameter Symbol Conditions Units Min Max 10 µA Input Leakage Current ILI VCC = 3.6, VIN = GND to VCC Output Leakage Current ILO CS = VIH, OE = VIH, VOUT = GND to VCC 10 µA ICC x 32 CS = VIL, OE = VIH, f = 5MHz, Vcc = 3.6 100 mA Standby Current ISB CS = VIH, OE = VIH, f = 5MHz, Vcc = 3.6 2.0 mA Output Low Voltage VOL IOL = 2.1mA, VCC = 3.0 0.4 Output High Voltage VOH IOH = -1.0mA, VCC = 3.0 Operating Supply Current x 32 Mode 2.4 V V NOTE: DC test conditions: VIH = VCC -0.3V, VIL = 0.3V 3 White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com WS512K32V-XXX AC CHARACTERISTICS (VCC = 3.3V, VSS =0V, TA = -55°C to +125°C) Parameter Symbol Read Cycle -70 Min Read Cycle Time t RC Address Access Time t AA Output Hold from Address Change t OH Chip Select Access Time t ACS -85 Max 70 Min Max 85 5 85 5 10 5 ns 120 ns 120 ns ns 50 10 5 Max 5 100 40 10 Min Units 120 100 85 35 t OE t CLZ 1 Max 5 70 Chip Select to Output in Low Z Min -120 100 70 Output Enable to Output Valid -100 60 ns 10 5 ns 5 ns Output Enable to Output in Low Z t OLZ 1 Chip Disable to Output in High Z t CHZ 1 25 25 35 35 ns Output Disable to Output in High Z t OHZ 1 25 25 35 35 ns 1. This parameter is guaranteed by design but not tested. AC CHARACTERISTICS (VCC = 3.3V, VSS =0V, TA = -55°C to +125°C) Parameter Symbol Write Cycle -70 Min -85 Max Min -100 Max Min -120 Max Min Units Max Write Cycle Time t WC 70 85 100 120 ns Chip Select to End of Write t CW 60 75 80 100 ns Address Valid to End of Write t AW 60 75 80 100 ns Data Valid to End of Write t DW 30 30 40 40 ns Write Pulse Width t WP 50 50 60 60 ns Address Setup Time t AS 0 0 0 0 ns Address Hold Time t AH 5 5 5 5 ns Output Active from End of Write t OW 1 5 5 5 5 Write Enable to Output in High Z t WHZ 1 Data Hold from Write Time 25 0 t DH 25 0 ns 35 0 35 ns 0 ns 1. This parameter is guaranteed by design but not tested. FIG. 3 AC TEST CONDITIONS AC TEST CIRCUIT Parameter I OL Current Source VZ D.U.T. ≈ 1.5V (Bipolar Supply) C eff = 50 pf I OH Current Source White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com 4 Typ Unit Input Pulse Levels VIL = 0, VIH = 2.5 V Input Rise and Fall 5 ns Input and Output Reference Level 1.5 V Output Timing Reference Level 1.5 V NOTES: VZ is programmable from -2V to +7V. IOL & I OH programmable from 0 to 16mA. Tester Impedance Z0 = 75 Ω. VZ is typically the midpoint of VOH and VOL . IOL & I OH are adjusted to simulate a typical resistive load circuit. ATE tester includes jig capacitance. WS512K32V-XXX FIG. 4 TIMING WAVEFORM - READ CYCLE tRC ADDRESS tAA CS tRC tCHZ tACS ADDRESS tCLZ tAA OE tOE tOLZ tOH DATA I/O PREVIOUS DATA VALID DATA I/O DATA VALID tOHZ DATA VALID HIGH IMPEDANCE READ CYCLE 1 (CS = OE = VIL, WE = VIH) READ CYCLE 2 (WE = VIH) FIG. 5 WRITE CYCLE - WE CONTROLLED tWC ADDRESS tAW tAH tCW CS tAS tWP WE tOW tWHZ tDW DATA I/O tDH DATA VALID WRITE CYCLE 1, WE CONTROLLED FIG. 6 WRITE CYCLE - CS CONTROLLED tWC WS32K32-XHX ADDRESS tAS tAW tAH tCW CS tWP WE tDW DATA I/O tDH DATA VALID WRITE CYCLE 2, CS CONTROLLED 5 White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com WS512K32V-XXX PACKAGE 401: 66 PIN, PGA TYPE, CERAMIC HEX-IN-LINE PACKAGE, HIP (H) 30.1 (1.185) ± 0.38 (0.015) SQ PIN 1 IDENTIFIER SQUARE PAD ON BOTTOM 25.4 (1.0) TYP 6.22 (0.245) MAX 3.81 (0.150) ± 0.1 (0.005) 1.27 (0.050) ± 0.1 (0.005) 0.76 (0.030) ± 0.1 (0.005) 2.54 (0.100) TYP 15.24 (0.600) TYP 1.27 (0.050) TYP DIA 0.46 (0.018) ± 0.05 (0.002) DIA 25.4 (1.0) TYP ALL LINEAR DIMENSIONS ARE MILLIMETERS AND PARENTHETICALLY IN INCHES White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com 6 WS512K32V-XXX PACKAGE 509: 68 LEAD, CERAMIC QUAD FLAT PACK, CQFP (G2T) 25.15 (0.990) ± 0.26 (0.010) SQ 4.57 (0.180) MAX 22.36 (0.880) ± 0.26 (0.010) SQ 0.27 (0.011) ± 0.04 (0.002) 0.25 (0.010) REF Pin 1 R 0.25 (0.010) 24.03 (0.946) ± 0.26 (0.010) 0.19 (0.007) ± 0.06 (0.002) 1° / 7° 1.0 (0.040) ± 0.127 (0.005) 23.87 (0.940) REF DETAIL A 1.27 (0.050) TYP SEE DETAIL "A" 0.38 (0.015) ± 0.05 (0.002) 20.3 (0.800) REF The WEDC 68 lead G2T CQFP fills the same fit and function as the JEDEC 68 lead CQFJ or 68 PLCC. But the G2T has the TCE and lead inspection advantage of the CQFP form. 0.940" TYP ALL LINEAR DIMENSIONS ARE MILLIMETERS AND PARENTHETICALLY IN INCHES 7 White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com WS512K32V-XXX ORDERING INFORMATION W S 512K 32 X V - XXX X X X LEAD FINISH: Blank = Gold plated leads A = Solder dip leads DEVICE GRADE: Q = MIL-STD-883 Compliant M = Military Screened -55°C to +125°C I = Industrial -40°C to 85°C C = Commercial 0°C to +70°C PACKAGE TYPE: H = Ceramic Hex-In-line Package, HIP (Package 401) G2T = 22.4mm Ceramic Quad Flat Pack, Low Profile CQFP (Package 509) ACCESS TIME (ns) Low Voltage Supply 3.3V ± 10% IMPROVEMENT MARK: N = No Connect at pin 21 and 39 in HIP for Upgrades ORGANIZATION, 512Kx32 User configurable as 1Mx16 or 2Mx8 SRAM WHITE ELECTRONIC DESIGNS CORP. White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com 8