VISHAY IRFP15N60L

IRFP15N60L, SiHFP15N60L
Vishay Siliconix
Power MOSFET
FEATURES
PRODUCT SUMMARY
VDS (V)
• Superfast Body Diode Eliminates the Need for
External Diodes in ZVS Applications
600
RDS(on) (Ω)
VGS = 10 V
0.385
Available
RoHS*
Qg (Max.) (nC)
100
Qgs (nC)
30
• Lower Gate Charge Results in Simple Drive
Requirements
46
• Enhanced dV/dt Capabilities Offer Improved Ruggedness
Qgd (nC)
Configuration
Single
COMPLIANT
• Higher Gate Voltage Threshold Offers Improved Noise
Immunity
D
• Lead (Pb)-free Available
TO-247
APPLICATIONS
G
• Zero Voltage Switching SMPS
• Telecom and Server Power Supplies
S
D
G
• Uninterruptible Power Supplies
S
N-Channel MOSFET
• Motor Control Applications
ORDERING INFORMATION
Package
TO-247
IRFP15N60LPbF
SiHFP15N60L-E3
IRFP15N60L
SiHFP15N60L
Lead (Pb)-free
SnPb
ABSOLUTE MAXIMUM RATINGS TC = 25 °C, unless otherwise noted
PARAMETER
SYMBOL
LIMIT
Drain-Source Voltage
VDS
600
Gate-Source Voltage
VGS
± 30
VGS at 10 V
Continuous Drain Current
Pulsed Drain
TC = 25 °C
ID
TC = 100 °C
Currenta
IDM
Linear Derating Factor
UNIT
V
15
9.7
A
60
2.3
W/°C
mJ
Single Pulse Avalanche Energyb
EAS
320
Repetitive Avalanche Currenta
IAR
15
A
Repetitive Avalanche Energya
EAR
28
mJ
Maximum Power Dissipation
TC = 25 °C
PD
280
W
dV/dt
10
V/ns
TJ, Tstg
- 55 to + 150
Peak Diode Recovery dV/dtc
Operating Junction and Storage Temperature Range
Soldering Recommendations (Peak Temperature)
Mounting Torque
for 10 s
6-32 or M3 screw
300d
°C
10
lbf · in
1.1
N·m
Notes
a. Repetitive rating; pulse width limited by maximum junction temperature (see fig. 11).
b. Starting TJ = 25 °C, L = 2.9 mH, RG = 25 Ω, IAS = 15 A, dV/dt = 10 V/ns (see fig. 12a).
c. ISD ≤ 15 A, dI/dt ≤ 340 A/µs, VDD ≤ VDS, TJ ≤ 150 °C.
d. 1.6 mm from case.
* Pb containing terminations are not RoHS compliant, exemptions may apply
Document Number: 91204
S-Pedning-Rev. B, 24-Jun-08
WORK-IN-PROGRESS
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IRFP15N60L, SiHFP15N60L
Vishay Siliconix
THERMAL RESISTANCE RATINGS
PARAMETER
SYMBOL
TYP.
MAX.
Maximum Junction-to-Ambient
RthJA
-
40
Case-to-Sink, Flat, Greased Surface
RthCS
0.24
-
Maximum Junction-to-Case (Drain)
RthJC
-
0.44
UNIT
°C/W
SPECIFICATIONS TJ = 25 °C, unless otherwise noted
PARAMETER
SYMBOL
TEST CONDITIONS
MIN.
TYP.
MAX.
UNIT
VDS
VGS = 0 V, ID = 250 µA
600
-
-
V
ΔVDS/TJ
Reference to 25 °C, ID = 1 mA
-
0.39
-
V/°C
VGS(th)
VDS = VGS, ID = 250 µA
3.0
-
5.0
V
VGS = ± 30 V
-
-
± 100
nA
VDS = 600 V, VGS = 0 V
-
-
50
µA
Static
Drain-Source Breakdown Voltage
VDS Temperature Coefficient
Gate-Source Threshold Voltage
Gate-Source Leakage
IGSS
Zero Gate Voltage Drain Current
IDSS
Drain-Source On-State Resistance
RDS(on)
Forward Transconductance
gfs
VDS = 480 V, VGS = 0 V, TJ = 125 °C
ID = 9.0 Ab
VGS = 10 V
VDS = 50 V, ID = 9.0 A
-
-
2.0
mA
-
0.385
0.460
Ω
8.3
-
-
S
-
2720
-
Dynamic
Input Capacitance
Ciss
Output Capacitance
Coss
Reverse Transfer Capacitance
Crss
Effective Output Capacitance
Coss eff.
Effective Output Capacitance
(Energy Related)
Coss eff. (ER)
Total Gate Charge
Qg
Gate-Source Charge
Qgs
VGS = 0 V,
VDS = 25 V,
f = 1.0 MHz, see fig. 5
VGS = 0 V,
VDS = 0 V to 480 Vc
VGS = 10 V
ID = 15 A, VDS = 480 V,
see fig. 7 and 15b
-
260
-
-
20
-
-
120
-
-
100
-
-
-
100
-
-
30
Gate-Drain Charge
Qgd
-
-
46
Turn-On Delay Time
td(on)
-
20
-
-
44
-
-
28
-
-
5.5
-
-
-
15
-
-
60
Rise Time
Turn-Off Delay Time
Fall Time
tr
td(off)
VDD = 300 V, ID = 15 A,
RG = 1.8 Ω, VGS = 10 V,
see fig. 11a and 11bb
tf
pF
nC
ns
Drain-Source Body Diode Characteristics
Continuous Source-Drain Diode Current
IS
Pulsed Diode Forward Currenta
ISM
Body Diode Voltage
VSD
Body Diode Reverse Recovery Time
trr
Body Diode Reverse Recovery Charge
Qrr
Reverse Recovery Time
IRRM
Forward Turn-On Time
ton
MOSFET symbol
showing the
integral reverse
p - n junction diode
D
A
G
S
TJ = 25 °C, IS = 15 A, VGS = 0 Vb
-
-
1.5
TJ = 25 °C, IF = 15 A
-
130
200
TJ = 125 °C, dI/dt = 100 A/µsb
-
240
360
TJ = 25 °C, IF = 15 A, VGS = 0 Vb
-
450
670
-
1080
1620
-
5.8
8.7
TJ = 125 °C, dI/dt = 100
TJ = 25 °C
A/µsb
V
ns
nC
A
Intrinsic turn-on time is negligible (turn-on is dominated by LS and LD)
Notes
a. Repetitive rating; pulse width limited by maximum junction temperature (see fig. 11).
b. Pulse width ≤ 300 µs; duty cycle ≤ 2 %.
c. Coss eff. is a fixed capacitance that gives the same charging time as Coss while VDS is rising from 0 to 80 % VDS.
Coss eff. (ER) is a fixed capacitance that stores the same energy as Coss while VDS is rising from 0 to 80 % VDS.
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Document Number: 91204
S-Pedning-Rev. B, 24-Jun-08
IRFP15N60L, SiHFP15N60L
Vishay Siliconix
TYPICAL CHARACTERISTICS 25 °C, unless otherwise noted
1000
100
10
BOTTOM
1000
VGS
15V
12V
10V
9.0V
8.0V
7.0V
6.0V
5.0V
ID, Drain-to-Source Current (Α)
ID, Drain-to-Source Current (A)
TOP
1
5.0V
0.1
0.01
100
T J = 150°C
10
1
T J = 25°C
0.1
VDS = 50V
20μs PULSE WIDTH
20μs PULSE WIDTH
Tj = 25°C
0.001
0.01
0.1
1
10
100
4
VDS, Drain-to-Source Voltage (V)
Fig. 1 - Typical Output Characteristics
8
10
12
14
16
3.0
10
BOTTOM
5.0V
1
0.1
20μs PULSE WIDTH
Tj = 150°C
ID = 15A
2.5
VGS = 10V
2.0
(Normalized)
TOP
VGS
15V
12V
10V
9.0V
8.0V
7.0V
6.0V
5.0V
RDS(on) , Drain-to-Source On Resistance
100
ID, Drain-to-Source Current (A)
6
VGS , Gate-to-Source Voltage (V)
Fig. 3 - Typical Transfer Characteristics
1.5
1.0
0.5
0.0
0.01
0.1
1
10
VDS, Drain-to-Source Voltage (V)
Fig. 2 - Typical Output Characteristics
Document Number: 91204
S-Pedning-Rev. B, 24-Jun-08
100
-60 -40 -20
0
20
40
60
80 100 120 140 160
T J , Junction Temperature (°C)
Fig. 4 - Normalized On-Resistance vs. Temperature
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IRFP15N60L, SiHFP15N60L
Vishay Siliconix
100000
ID= 15A
VGS , Gate-to-Source Voltage (V)
10000
C, Capacitance(pF)
12.0
VGS = 0V,
f = 1 MHZ
Ciss = C gs + Cgd, C ds SHORTED
Crss = Cgd
Coss = Cds + Cgd
Ciss
1000
Coss
100
Crss
10
10.0
VDS= 120V
8.0
6.0
4.0
2.0
0.0
1
1
10
100
0
1000
VDS, Drain-to-Source Voltage (V)
Fig. 5 - Typical Capacitance vs. Drain-to-Source Voltage
25
10
20
30
40
50
60
70
Q G Total Gate Charge (nC)
Fig. 7 - Typical Gate Charge vs. Gate-to-Source Voltage
100.00
ISD, Reverse Drain Current (A)
20
Energy (μJ)
VDS= 480V
VDS= 300V
15
10
5
T J = 150°C
10.00
T J = 25°C
1.00
VGS = 0V
0
0
100
200
300
400
500
600
700
VDS, Drain-to-Source Voltage (V)
Fig. 6 - Typical Output Capacitance Stored Energy vs. VDS
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0.10
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
VSD, Source-to-Drain Voltage (V)
Fig. 8 - Typical Source-Drain Diode Forward Voltage
Document Number: 91204
S-Pedning-Rev. B, 24-Jun-08
IRFP15N60L, SiHFP15N60L
Vishay Siliconix
ID, Drain-to-Source Current (A)
1000
OPERATION IN THIS AREA
LIMITED BY R DS(on)
100
10
100μsec
1msec
1
Tc = 25°C
Tj = 150°C
Single Pulse
10msec
0.1
1
10
100
1000
10000
VDS, Drain-to-Source Voltage (V)
Fig. 9 - Maximum Safe Operating Area
RD
VDS
16
VGS
14
D.U.T.
RG
+
- VDD
ID, Drain Current (A)
12
10 V
10
Pulse width ≤ 1 µs
Duty factor ≤ 0.1 %
8
Fig. 11a - Switching Time Test Circuit
6
4
VDS
90 %
2
0
25
50
75
100
125
150
T C , Case Temperature (°C)
10 %
VGS
td(on)
Fig. 10 - Maximum Drain Current vs. Case Temperature
Document Number: 91204
S-Pedning-Rev. B, 24-Jun-08
tr
td(off) tf
Fig. 11b - Switching Time Waveforms
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IRFP15N60L, SiHFP15N60L
Vishay Siliconix
Thermal Response ( Z thJC )
1
D = 0.50
0.1
0.20
0.10
0.05
0.02
0.01
0.01
P DM
t1
0.001
SINGLE PULSE
( THERMAL RESPONSE )
t2
Notes:
1. Duty factor D =
2. Peak T
0.0001
1E-006
1E-005
0.0001
0.001
t1 / t 2
J = P DM x Z thJC
0.01
+TC
0.1
1
t1 , Rectangular Pulse Duration (sec)
Fig. 12 - Maximum Effective Transient Thermal Impedance, Junction-to-Case
600
EAS , Single Pulse Avalanche Energy (mJ)
VGS(th) Gate threshold Voltage (V)
5.0
4.5
4.0
3.5
ID = 250μA
3.0
2.5
2.0
ID
6.7A
9.5A
BOTTOM 15A
TOP
500
400
300
200
100
0
-75
-50 -25
0
25
50
75
100 125 150 175
25
T J , Temperature ( °C )
50
75
100
125
150
Starting T J , Junction Temperature (°C)
Fig. 13 - Threshold Voltage vs. Temperature
Fig. 14a - Maximum Avalanche Energy vs. Drain Current
VDS
15 V
tp
L
VDS
D.U.T
RG
IAS
20 V
tp
Driver
+
A
- VDD
IAS
0.01 Ω
Fig. 14b - Unclamped Inductive Test Circuit
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A
Fig. 14c - Unclamped Inductive Waveforms
Document Number: 91204
S-Pedning-Rev. B, 24-Jun-08
IRFP15N60L, SiHFP15N60L
Vishay Siliconix
Current regulator
Same type as D.U.T.
50 kΩ
QG
VGS
12 V
QGS
0.2 µF
0.3 µF
QGD
+
D.U.T.
VG
-
VDS
VGS
3 mA
Charge
IG
ID
Current sampling resistors
Fig. 15a - Basic Gate Charge Waveform
Fig. 15b - Gate Charge Test Circuit
Peak Diode Recovery dV/dt Test Circuit
+
D.U.T
Circuit layout considerations
• Low stray inductance
• Ground plane
• Low leakage inductance
current transformer
+
-
-
RG
•
•
•
•
dV/dt controlled by RG
Driver same type as D.U.T.
ISD controlled by duty factor "D"
D.U.T. - device under test
Driver gate drive
P.W.
+
Period
D=
+
-
VDD
P.W.
Period
VGS = 10 V*
D.U.T. ISD waveform
Reverse
recovery
current
Body diode forward
current
dI/dt
D.U.T. VDS waveform
Diode recovery
dV/dt
Re-applied
voltage
VDD
Body diode forward drop
Inductor current
Ripple ≤ 5 %
ISD
* VGS = 5 V for logic level devices
Fig. 16 - For N-Channel
Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon
Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and
reliability data, see http://www.vishay.com/ppg?91204.
Document Number: 91204
S-Pedning-Rev. B, 24-Jun-08
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Disclaimer
All product specifications and data are subject to change without notice.
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(collectively, “Vishay”), disclaim any and all liability for any errors, inaccuracies or incompleteness contained herein
or in any other disclosure relating to any product.
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therein, which apply to these products.
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Document Number: 91000
Revision: 18-Jul-08
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