VISHAY SIHFP32N50K-E3

IRFP32N50K, SiHFP32N50K
Vishay Siliconix
Power MOSFET
FEATURES
PRODUCT SUMMARY
VDS (V)
• Low Gate Charge Qg Results in Simple Drive
Requirement
500
RDS(on) (Ω)
VGS = 10 V
0.135
Qg (Max.) (nC)
190
Qgs (nC)
59
Qgd (nC)
Ruggedness
• Fully Characterized Capacitance and Avalanche Voltage
and Current
84
Configuration
Available
• Improved Gate, Avalanche and Dynamic dV/dt RoHS*
COMPLIANT
Single
• Low RDS(on)
D
• Lead (Pb)-free Available
TO-247
APPLICATIONS
G
• Switch Mode Power Supply (SMPS)
• Uninterruptible Power Supply
S
D
G
S
• High Speed Power Switching
N-Channel MOSFET
• Hard Switching and High Frequency Circuits
ORDERING INFORMATION
Package
TO-247
IRFP32N50KPbF
SiHFP32N50K-E3
IRFP32N50K
SiHFP32N50K
Lead (Pb)-free
SnPb
ABSOLUTE MAXIMUM RATINGS TC = 25 °C, unless otherwise noted
PARAMETER
SYMBOL
LIMIT
Drain-Source Voltage
VDS
500
Gate-Source Voltage
VGS
± 30
Continuous Drain Current
VGS at 10 V
TC = 25 °C
TC = 100 °C
Pulsed Drain Currenta
ID
UNIT
V
32
20
A
IDM
130
3.7
W/°C
Single Pulse Avalanche Energyb
EAS
450
mJ
Repetitive Avalanche Currenta
IAR
32
A
Repetitive Avalanche Energya
EAR
46
mJ
PD
460
W
dV/dt
13
V/ns
TJ, Tstg
- 55 to + 150
Linear Derating Factor
Maximum Power Dissipation
Peak Diode Recovery
TC = 25 °C
dV/dtc
Operating Junction and Storage Temperature Range
Soldering Recommendations (Peak Temperature)
Mounting Torque
for 10 s
6-32 or M3 screw
300d
°C
10
lbf · in
1.1
N·m
Notes
a. Repetitive rating; pulse width limited by maximum junction temperature.
b. Starting TJ = 25 °C, L = 0.87 mH, RG = 25 Ω, IAS = 32 A.
c. ISD ≤ 32 A, dI/dt ≤ 197 A/µs, VDD ≤ VDS, TJ ≤ 150 °C.
d. 1.6 mm from case.
* Pb containing terminations are not RoHS compliant, exemptions may applyrom case.
Document Number: 91221
S-81361-Rev. B, 07-Jul-08
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IRFP32N50K, SiHFP32N50K
Vishay Siliconix
THERMAL RESISTANCE RATINGS
PARAMETER
SYMBOL
TYP.
MAX.
Maximum Junction-to-Ambient
RthJA
-
40
Case-to-Sink, Flat, Greased Surface
RthCS
0.24
-
Maximum Junction-to-Case (Drain)
RthJC
-
0.26
UNIT
°C/W
SPECIFICATIONS TJ = 25 °C, unless otherwise noted
PARAMETER
SYMBOL
TEST CONDITIONS
MIN.
TYP.
MAX.
UNIT
VDS
VGS = 0 V, ID = 250 µA
500
-
-
V
ΔVDS/TJ
Reference to 25 °C, ID = 1 mA
-
0.54
-
V/°C
VGS(th)
VDS = VGS, ID = 250 µA
3.0
-
5.0
V
nA
Static
Drain-Source Breakdown Voltage
VDS Temperature Coefficient
Gate-Source Threshold Voltage
Gate-Source Leakage
Zero Gate Voltage Drain Current
Drain-Source On-State Resistance
Forward Transconductance
IGSS
IDSS
RDS(on)
gfs
VGS = ± 30 V
-
-
± 100
VDS = 500 V, VGS = 0 V
-
-
50
VDS = 400 V, VGS = 0 V, TJ = 150 °C
-
-
250
ID = 32 Ab
VGS = 10 V
VDS = 50 V, ID = 32 A
µA
-
0.135
0.16
Ω
14
-
-
S
-
5280
-
Dynamic
Input Capacitance
Ciss
Output Capacitance
Coss
Reverse Transfer Capacitance
Crss
Output Capacitance
Effective Output Capacitance
Coss
VGS = 0 V,
VDS = 25 V,
f = 1.0 MHz, see fig. 5
VGS = 0 V
Coss eff.
Total Gate Charge
Qg
Gate-Source Charge
Qgs
-
550
-
-
45
-
VDS = 1.0 V, f = 1.0 MHz
-
5630
-
VDS = 400 V, f = 1.0 MHz
-
155
-
-
265
-
-
-
190
-
-
59
VDS = 0 V to 400
VGS = 10 V
Vc
ID = 32 A, VDS = 400 Vb
pF
nC
Gate-Drain Charge
Qgd
-
-
84
Turn-On Delay Time
td(on)
-
28
-
-
120
-
-
48
-
-
54
-
-
-
32
-
-
130
-
-
1.5
-
530
800
ns
-
9.0
13.5
µC
-
30
-
A
Rise Time
Turn-Off Delay Time
Fall Time
tr
td(off)
VDD = 250 V, ID = 32 A,
RG = 4.3 Ω, VGS = 10 Vb
tf
ns
Drain-Source Body Diode Characteristics
Continuous Source-Drain Diode Current
IS
Pulsed Diode Forward Currenta
ISM
Body Diode Voltage
VSD
Body Diode Reverse Recovery Time
trr
Body Diode Reverse Recovery Charge
Qrr
Body Diode Reverse Recovery Current
IRRM
Forward Turn-On Time
ton
MOSFET symbol
showing the
integral reverse
p - n junction diode
D
A
G
S
TJ = 25 °C, IS = 32 A, VGS = 0 Vb
TJ = 25 °C, IF = 32 A, dI/dt = 100 A/µsb
V
Intrinsic turn-on time is negligible (turn-on is dominated by LS and LD)
Notes
a. Repetitive rating; pulse width limited by maximum junction temperature.
b. Pulse width ≤ 400 µs; duty cycle ≤ 2 %.
c. Coss eff. is a fixed capacitance that gives the same charging time as Coss while VDS is rising from 0 to 80 % VDS.
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Document Number: 91221
S-81361-Rev. B, 07-Jul-08
IRFP32N50K, SiHFP32N50K
Vishay Siliconix
TYPICAL CHARACTERISTICS 25 °C, unless otherwise noted
Top
100
Bottom
1000
VGS
15 V
12 V
10 V
8.0 V
7.0 V
6.0 V
5.5 V
5.0 V
ID, Drain-to-Source Current (A)
ID, Drain-to-Source Current (A)
1000
10
1
5.0 V
0.1
100
TJ = 150 °C
10
TJ = 25 °C
1
20 μs PULSE WIDTH
TJ = 25 °C
0.01
0.1
1
10
4
100
VGS
15 V
12 V
10 V
8.0 V
7.0 V
6.0 V
5.5 V
Bottom 5.0 V
ID, Drain-to-Source Current (A)
Top
5.0 V
1
20 μs PULSE WIDTH
TJ = 150 °C
0.1
0.1
1
10
VDS, Drain-to-Source Voltage (V)
Fig. 2 - Typical Output Characteristics
Document Number: 91221
S-81361-Rev. B, 07-Jul-08
8
9
11
12
Fig. 3 - Typical Transfer Characteristics
RDS(on), Drain-to-Source On Resistance (Normalized)
Fig. 1 - Typical Output Characteristics
10
7
5
VGS, Gate-to-Source Voltage (V)
VDS, Drain-to-Source Voltage (V)
100
VDS = 50 V
20 μs PULSE WIDTH
0.1
100
3.0
ID = 32 A
2.5
2.0
1.5
1.0
0.5
0.0
- 60 - 40 - 20 0
20 40
VGS = 10 V
60 80 100 120 140 160
TJ, Junction Temperature
Fig. 4 - Normalized On-Resistance vs. Temperature
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IRFP32N50K, SiHFP32N50K
Vishay Siliconix
VGS = 0 V,
Ciss = Cgs + Cgd, Cds
Crss = Cgd
Coss = Cds + Cgd
10000
C, Capacitance (pF)
1000
f = 1 MHz
SHORTED
ISD, Reverse Drain Current (A)
1000000
Ciss
1000
Coss
100
100
TJ = 150 °C
10
TJ = 25 °C
1
Crss
10
1
10
100
0.1
0.2
1000
VDS, Drain-to-Source Voltage (V)
1.6
VSD, Source-to-Drain Voltage (V)
Fig. 7 - Typical Source-Drain Diode Forward Voltage
Fig. 5 - Typical Capacitance vs. Drain-to-Source Voltage
1000
20
ID = 32 A
OPERATING IN THIS AREA LIMITED
BY RDS(on)
VDS = 400 V
VDS = 250 V
VDS = 100 V
16
ID, Drain Current (A)
VGS, Gate-to-Source Voltage (V)
VGS = 0 V
1.3
0.9
0.6
12
8
100
10 μs
100 μs
10
1 ms
4
0
0
40
160
80
120
QG, Total Gate Charge (nC)
200
Fig. 6 - Typical Gate Charge vs. Gate-to-Source Voltage
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1
10
TC = 25 °C
TJ = 150 °C
Single Pulse
10 ms
100
1000
10000
VDS, Drain-to-Source Voltage (V)
Fig. 8 - Maximum Safe Operating Area
Document Number: 91221
S-81361-Rev. B, 07-Jul-08
IRFP32N50K, SiHFP32N50K
Vishay Siliconix
RD
VDS
35
VGS
25
ID, Drain Current (A)
D.U.T.
RG
30
+
- VDD
10 V
Pulse width ≤ 1 µs
Duty factor ≤ 0.1 %
20
Fig. 10a - Switching Time Test Circuit
15
10
VDS
90 %
5
0
50
25
75
125
100
TC, Case Temperature (°C)
150
10 %
VGS
td(on)
td(off) tf
tr
Fig. 10b - Switching Time Waveforms
Fig. 9 - Maximum Drain Current vs. Case Temperature
Thermal Response (ZthJC)
1
D = 0.50
0.1
0.20
0.10
0.05
0.02
0.01
0.01
PDM
SINGLE PULSE
(THERMAL RESPONSE)
t1
t2
Notes:
1. Duty factor D = t1/ t2
2. Peak TJ = PDM x ZthJC + TC
0.001
0.00001
0.0001
0.001
0.01
0.1
1
t , Rectangular Pulse Duration (sec)
Fig. 11 - Maximum Effective Transient Thermal Impedance, Junction-to-Case
VDS
15 V
L
VDS
D.U.T
RG
IAS
20 V
tp
tp
Driver
+
A
- VDD
0.01 Ω
Fig. 12a - Unclamped Inductive Test Circuit
Document Number: 91221
S-81361-Rev. B, 07-Jul-08
IAS
Fig. 12b - Unclamped Inductive Waveforms
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IRFP32N50K, SiHFP32N50K
Vishay Siliconix
800
EAS, Single Pulse Avalanche Energy (mJ)
TOP
BOTTOM
640
ID
7A
10 A
16 A
480
320
160
0
25
50
75
100
150
125
Starting TJ, Junction Temperature (°C)
Fig. 12c - Maximum Avalanche Energy vs. Drain Current
Current regulator
Same type as D.U.T.
50 kΩ
QG
10 V
12 V
0.2 µF
0.3 µF
QGS
QGD
+
D.U.T.
VG
-
VDS
VGS
3 mA
Charge
IG
ID
Current sampling resistors
Fig. 13a - Basic Gate Charge Waveform
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Fig. 13b - Gate Charge Test Circuit
Document Number: 91221
S-81361-Rev. B, 07-Jul-08
IRFP32N50K, SiHFP32N50K
Vishay Siliconix
Peak Diode Recovery dV/dt Test Circuit
+
D.U.T.
Circuit layout considerations
• Low stray inductance
• Ground plane
• Low leakage inductance
current transformer
+
-
-
RG
•
•
•
•
dV/dt controlled by RG
Driver same type as D.U.T.
ISD controlled by duty factor "D"
D.U.T. - device under test
Driver gate drive
P.W.
+
Period
D=
+
-
VDD
P.W.
Period
VGS = 10 V*
D.U.T. ISD waveform
Reverse
recovery
current
Body diode forward
current
dI/dt
D.U.T. VDS waveform
Diode recovery
dV/dt
Re-applied
voltage
VDD
Body diode forward drop
Inductor current
Ripple ≤ 5 %
ISD
* VGS = 5 V for logic level devices
Fig. 14 - For N-Channel
Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon
Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and
reliability data, see http://www.vishay.com/ppg?91221.
Document Number: 91221
S-81361-Rev. B, 07-Jul-08
www.vishay.com
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Vishay
Disclaimer
All product specifications and data are subject to change without notice.
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(collectively, “Vishay”), disclaim any and all liability for any errors, inaccuracies or incompleteness contained herein
or in any other disclosure relating to any product.
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information provided herein to the maximum extent permitted by law. The product specifications do not expand or
otherwise modify Vishay’s terms and conditions of purchase, including but not limited to the warranty expressed
therein, which apply to these products.
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Document Number: 91000
Revision: 18-Jul-08
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